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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 10:22:22.3103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d937336-6e25-4b42-0bb5-08dcf34c9513 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001504.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8521 Content-Type: text/plain; charset="utf-8" Explicitly rename functions that enable CPPC as *_cppc_*. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 3c14962adeb2..0b4a4d69c14d 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -306,7 +306,7 @@ static int amd_pstate_set_energy_pref_index(struct amd_= cpudata *cpudata, return ret; } =20 -static inline int msr_enable(bool enable) +static inline int msr_cppc_enable(bool enable) { int ret, cpu; unsigned long logical_proc_id_mask =3D 0; @@ -332,7 +332,7 @@ static inline int msr_enable(bool enable) return 0; } =20 -static int shmem_enable(bool enable) +static int shmem_cppc_enable(bool enable) { int cpu, ret =3D 0; struct cppc_perf_ctrls perf_ctrls; @@ -359,11 +359,11 @@ static int shmem_enable(bool enable) return ret; } =20 -DEFINE_STATIC_CALL(amd_pstate_enable, msr_enable); +DEFINE_STATIC_CALL(amd_pstate_cppc_enable, msr_cppc_enable); =20 -static inline int amd_pstate_enable(bool enable) +static inline int amd_pstate_cppc_enable(bool enable) { - return static_call(amd_pstate_enable)(enable); + return static_call(amd_pstate_cppc_enable)(enable); } =20 static int msr_init_perf(struct amd_cpudata *cpudata) @@ -1042,7 +1042,7 @@ static int amd_pstate_cpu_resume(struct cpufreq_polic= y *policy) { int ret; =20 - ret =3D amd_pstate_enable(true); + ret =3D amd_pstate_cppc_enable(true); if (ret) pr_err("failed to enable amd-pstate during resume, return %d\n", ret); =20 @@ -1053,7 +1053,7 @@ static int amd_pstate_cpu_suspend(struct cpufreq_poli= cy *policy) { int ret; =20 - ret =3D amd_pstate_enable(false); + ret =3D amd_pstate_cppc_enable(false); if (ret) pr_err("failed to disable amd-pstate during suspend, return %d\n", ret); =20 @@ -1186,7 +1186,7 @@ static ssize_t show_energy_performance_preference( =20 static void amd_pstate_driver_cleanup(void) { - amd_pstate_enable(false); + amd_pstate_cppc_enable(false); cppc_state =3D AMD_PSTATE_DISABLE; current_pstate_driver =3D NULL; } @@ -1220,7 +1220,7 @@ static int amd_pstate_register_driver(int mode) =20 cppc_state =3D mode; =20 - ret =3D amd_pstate_enable(true); + ret =3D amd_pstate_cppc_enable(true); if (ret) { pr_err("failed to enable cppc during amd-pstate driver registration, ret= urn %d\n", ret); @@ -1599,7 +1599,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudat= a *cpudata) u64 value, max_perf; int ret; =20 - ret =3D amd_pstate_enable(true); + ret =3D amd_pstate_cppc_enable(true); if (ret) pr_err("failed to enable amd pstate during resume, return %d\n", ret); =20 @@ -1686,7 +1686,7 @@ static int amd_pstate_epp_suspend(struct cpufreq_poli= cy *policy) cpudata->suspended =3D true; =20 /* disable CPPC in lowlevel firmware */ - ret =3D amd_pstate_enable(false); + ret =3D amd_pstate_cppc_enable(false); if (ret) pr_err("failed to suspend, return %d\n", ret); =20 @@ -1861,7 +1861,7 @@ static int __init amd_pstate_init(void) current_pstate_driver->adjust_perf =3D amd_pstate_adjust_perf; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 10:22:58.7699 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c08f21b3-877d-4522-f122-08dcf34caacb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004689.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6490 Content-Type: text/plain; charset="utf-8" MSR_AMD_CPPC_ENABLE is a write once register, i.e. attempting to clear it is futile, it will not take effect. Hence, return if disable (0) argument is passed to the msr_cppc_enable() Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 0b4a4d69c14d..576251e61ce0 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -311,6 +311,12 @@ static inline int msr_cppc_enable(bool enable) int ret, cpu; unsigned long logical_proc_id_mask =3D 0; =20 + /* + * MSR_AMD_CPPC_ENABLE is write-once, once set it cannot be cleared. + */ + if (!enable) + return 0; + if (enable =3D=3D cppc_enabled) return 0; =20 --=20 2.34.1 From nobody Mon Nov 25 23:21:54 2024 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2059.outbound.protection.outlook.com [40.107.244.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09ED11A256F; Wed, 23 Oct 2024 10:24:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 10:24:13.9773 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5473d8b4-ba3b-4044-12e0-08dcf34cd7a2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004687.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9348 Content-Type: text/plain; charset="utf-8" The EPP value being set in perf_ctrls.energy_perf is not being propagated to the shared memory, fix that. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 576251e61ce0..bbeddce90823 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1616,8 +1616,9 @@ static void amd_pstate_epp_reenable(struct amd_cpudat= a *cpudata) wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); } else { perf_ctrls.max_perf =3D max_perf; - perf_ctrls.energy_perf =3D AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached= ); cppc_set_perf(cpudata->cpu, &perf_ctrls); + perf_ctrls.energy_perf =3D AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached= ); + cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); } } =20 @@ -1658,8 +1659,9 @@ static void amd_pstate_epp_offline(struct cpufreq_pol= icy *policy) } else { perf_ctrls.desired_perf =3D 0; perf_ctrls.max_perf =3D min_perf; - perf_ctrls.energy_perf =3D AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POW= ERSAVE); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 10:24:49.2820 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 550af205-4ea9-45fa-c0ca-08dcf34cecaa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6160 Content-Type: text/plain; charset="utf-8" Set min_perf to lowest_perf for shared memory systems, similar to the MSR based systems. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index bbeddce90823..206725219d8c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1658,6 +1658,7 @@ static void amd_pstate_epp_offline(struct cpufreq_pol= icy *policy) wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); } else { perf_ctrls.desired_perf =3D 0; + perf_ctrls.min_perf =3D min_perf; perf_ctrls.max_perf =3D min_perf; cppc_set_perf(cpudata->cpu, &perf_ctrls); perf_ctrls.energy_perf =3D AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POW= ERSAVE); --=20 2.34.1