From nobody Tue Nov 26 02:40:32 2024 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E8C819C578; Wed, 23 Oct 2024 09:26:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675591; cv=none; b=fG4F2J74D8CsBrhSWJuPVw6gv3yAZfdzIzyT8JHthu0qV3wBf8cDMSV36u3hw5mKm9FO9Id3SloIZiWTFExfMK4x/VtpHgpUICORD6ZHnpdzmWr5dkKke9glIa5nZQZoEc+PSM2u+F0sdvbdPqXshA8BHexnymvc7M/QrUnj7kE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675591; c=relaxed/simple; bh=76A5hFm+eGno6dvaqQ948Cs/dZz6qtF0onvY+eG9D3o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XarvGUHL2mxAC/ZLYGiNTRhz1EnSD3gftc5VHpfKyQm9HqWr9j0FTJLmnU8/eoA7XGNsW+zSg/iinwA9vZB0w6jTxDt7dhD3r3bt6ZuhkqAB0KAOV1/e5dNXPUPKZpO43qo039iS4vlQa3R18ffamn6EQenVfXTSIhx4/dIp/78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UldUokjd; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UldUokjd" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-20cbb1cf324so57863805ad.0; Wed, 23 Oct 2024 02:26:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729675589; x=1730280389; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1l0j9vhh/TD6rkhjKdYOtzd2DKqn1QYTTqAOmlnUic8=; b=UldUokjdAVzc7Jq0lVxpDUqHocWMmQhbz2Fcr2MK55PkDl9hqijkZyMz6gz/6mfob9 4dVn0WB6nwoax6SLvxDLpHSq5aYC38t6ID/On4XR7Eee0TDb66fPhqIAQwiQVPYvJNVz K8LZ3yymUTTY/W/AGF1Z9jYtwqaoIIsg0xVO25I8pW6egsk8DTseA2+gkoX/WxaTfixQ v0ramh+2ijmjNwEN4lAub2tqRT4Da333pq7A14Q4iqriYvk1qS5unraH+GIcTwKKN2xW p8B0KHquHH/9z74PU2iJ3uvQc9Ee3rKjxPqC78WAzXKO6dC8/QP9Zknb93P7LOE2+PnV /SyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729675589; x=1730280389; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1l0j9vhh/TD6rkhjKdYOtzd2DKqn1QYTTqAOmlnUic8=; b=J3oYJ+2Ndw+vsUIx2Cuk601akJ5gr31D1T0ZRVgaaVOBH/V6GaUoRr2FVk5nTf0pLM e4Az1VPmepyTaUyaTv9RBIuhIS/jurOeUyyl1TAj9JTmfOR+a8VbfKlBpBFEiQdnEgab jw6SE2VWJe4sTEQjbRMsJj0SUpjISlwOfcEfcRHNbM1sFSIHlS6Fhv+KMKYn9sS7uxvV kCDqF/P5Cup1qHTqPseSm7PA4tAC3DD6QRHe4oXY0mwO2VrGyO7U5Xo5ABJL9EKlKB3q IvvErn2W2WEYBrC8EvA9NRxZTKuWxZBM3zB77rvcXwKKjRadHHACVZ+FqgBPXjBz4t1T i+7Q== X-Forwarded-Encrypted: i=1; AJvYcCUsy2nIWnDn2PHNf/8loOaXkPmUC2uY3N+oGV8Jt8iMzRffRI5ZiN/bC3+A5CFMx5BER1yXYk7JUtLjuFie@vger.kernel.org, AJvYcCW0tCpvh9ikzoLqADny+JbAcVu3TNbpIS9pOryd/vNqebQ8HzkFLhaH5PDQvZNd1C53gPRsTVtmvgTa@vger.kernel.org X-Gm-Message-State: AOJu0YyPHJenwLWlAHUqoxiJzLmJJ/sST793pcYC0Z6HkEQVw+jZRypZ hwg/xX+o6O5fohoWTbLe48kdhCos3iDmXuhKejMhAM6y5oXSbCno X-Google-Smtp-Source: AGHT+IHNK3QZiTadf1k9GFkyM3KULXRY3XIOrsnEUvd5SZT0UeNZ8arDmD8PC1rmyez8t+TfH8nFMA== X-Received: by 2002:a17:902:d4cc:b0:20b:b0ab:4fc3 with SMTP id d9443c01a7336-20fab2db85amr24556215ad.49.1729675588725; Wed, 23 Oct 2024 02:26:28 -0700 (PDT) Received: from localhost.localdomain (60-250-192-107.hinet-ip.hinet.net. [60.250.192.107]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0bd376sm54041635ad.132.2024.10.23.02.26.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:26:28 -0700 (PDT) From: Hui-Ping Chen To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nikita.shubin@maquefel.me, arnd@arndb.de, vkoul@kernel.org, esben@geanix.com Cc: linux-arm-kernel@lists.infradead.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hui-Ping Chen Subject: [PATCH v8 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC Date: Wed, 23 Oct 2024 09:26:17 +0000 Message-Id: <20241023092617.108021-3-hpchen0nvt@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241023092617.108021-1-hpchen0nvt@gmail.com> References: <20241023092617.108021-1-hpchen0nvt@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nuvoton MA35 SoCs NAND Flash Interface Controller supports 2kiB, 4kiB and 8kiB page size, and up to 8-bit, 12-bit, and 24-bit hardware ECC calculation circuit to protect data. Signed-off-by: Hui-Ping Chen --- drivers/mtd/nand/raw/Kconfig | 8 + drivers/mtd/nand/raw/Makefile | 1 + .../nand/raw/nuvoton-ma35d1-nand-controller.c | 932 ++++++++++++++++++ 3 files changed, 941 insertions(+) create mode 100644 drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d0aaccf72d78..e3677bcaf035 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -454,6 +454,14 @@ config MTD_NAND_TS72XX help Enables support for NAND controller on ts72xx SBCs. =20 +config MTD_NAND_NUVOTON_MA35 + tristate "Nuvoton MA35 SoC NAND controller" + depends on ARCH_MA35 || COMPILE_TEST + depends on OF + help + Enables support for the NAND controller found on + the Nuvoton MA35 series SoCs. + comment "Misc" =20 config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index d0b0e6b83568..99e79c448847 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_INTEL_LGM) +=3D intel-nand-controll= er.o obj-$(CONFIG_MTD_NAND_ROCKCHIP) +=3D rockchip-nand-controller.o obj-$(CONFIG_MTD_NAND_PL35X) +=3D pl35x-nand-controller.o obj-$(CONFIG_MTD_NAND_RENESAS) +=3D renesas-nand-controller.o +obj-$(CONFIG_MTD_NAND_NUVOTON_MA35) +=3D nuvoton-ma35d1-nand-controller.o =20 nand-objs :=3D nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_id= s.o nand-objs +=3D nand_onfi.o diff --git a/drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c b/driver= s/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c new file mode 100644 index 000000000000..7b581d9d9985 --- /dev/null +++ b/drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c @@ -0,0 +1,932 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Nuvoton Technology Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* NFI Registers */ +#define MA35_NFI_REG_DMACTL 0x400 +#define DMA_EN BIT(0) +#define DMA_RST BIT(1) +#define DMA_BUSY BIT(9) + +#define MA35_NFI_REG_DMASA 0x408 +#define MA35_NFI_REG_GCTL 0x800 +#define GRST BIT(0) +#define NAND_EN BIT(3) + +#define MA35_NFI_REG_NANDCTL 0x8A0 +#define SWRST BIT(0) +#define DMA_R_EN BIT(1) +#define DMA_W_EN BIT(2) +#define ECC_CHK BIT(7) +#define PROT3BEN BIT(8) +#define PSIZE_2K BIT(16) +#define PSIZE_4K BIT(17) +#define PSIZE_8K GENMASK(17, 16) +#define PSIZE_MASK GENMASK(17, 16) +#define BCH_T24 BIT(18) +#define BCH_T8 BIT(20) +#define BCH_T12 BIT(21) +#define BCH_NONE (0x0) +#define BCH_MASK GENMASK(22, 18) +#define ECC_EN BIT(23) +#define DISABLE_CS0 BIT(25) + +#define MA35_NFI_REG_NANDINTEN 0x8A8 +#define MA35_NFI_REG_NANDINTSTS 0x8AC +#define INT_DMA BIT(0) +#define INT_ECC BIT(2) +#define INT_RB0 BIT(10) + +#define MA35_NFI_REG_NANDCMD 0x8B0 +#define MA35_NFI_REG_NANDADDR 0x8B4 +#define ENDADDR BIT(31) + +#define MA35_NFI_REG_NANDDATA 0x8B8 +#define MA35_NFI_REG_NANDRACTL 0x8BC +#define MA35_NFI_REG_NANDECTL 0x8C0 +#define ENABLE_WP 0x0 +#define DISABLE_WP BIT(0) + +#define MA35_NFI_REG_NANDECCES0 0x8D0 +#define ECC_STATUS_MASK GENMASK(1, 0) +#define ECC_ERR_CNT_MASK GENMASK(4, 0) + +#define MA35_NFI_REG_NANDECCEA0 0x900 +#define MA35_NFI_REG_NANDECCED0 0x960 +#define MA35_NFI_REG_NANDRA0 0xA00 + +/* Define for the BCH hardware ECC engine */ +/* define the total padding bytes for 512/1024 data segment */ +#define MA35_BCH_PADDING_512 32 +#define MA35_BCH_PADDING_1024 64 +/* define the BCH parity code length for 512 bytes data pattern */ +#define MA35_PARITY_BCH8 15 +#define MA35_PARITY_BCH12 23 +/* define the BCH parity code length for 1024 bytes data pattern */ +#define MA35_PARITY_BCH24 45 + +#define MA35_MAX_NSELS (2) +#define PREFIX_RA_IS_EMPTY(reg) FIELD_GET(GENMASK(31, 16), (reg)) + +struct ma35_nand_chip { + struct list_head node; + struct nand_chip chip; + + u32 nchunks; + u8 nsels; + u8 sels[] __counted_by(nsels); +}; + +struct ma35_nand_info { + struct nand_controller controller; + struct device *dev; + void __iomem *regs; + int irq; + struct clk *clk; + struct completion complete; + struct list_head chips; + + unsigned long assigned_cs; +}; + +static inline struct ma35_nand_chip *to_ma35_nand(struct nand_chip *chip) +{ + return container_of(chip, struct ma35_nand_chip, chip); +} + +static int ma35_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *oob_region) +{ + struct nand_chip *chip =3D mtd_to_nand(mtd); + + if (section) + return -ERANGE; + + oob_region->length =3D chip->ecc.total; + oob_region->offset =3D mtd->oobsize - oob_region->length; + + return 0; +} + +static int ma35_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *oob_region) +{ + struct nand_chip *chip =3D mtd_to_nand(mtd); + + if (section) + return -ERANGE; + + oob_region->length =3D mtd->oobsize - chip->ecc.total - 2; + oob_region->offset =3D 2; + + return 0; +} + +static const struct mtd_ooblayout_ops ma35_ooblayout_ops =3D { + .free =3D ma35_ooblayout_free, + .ecc =3D ma35_ooblayout_ecc, +}; + +static inline void ma35_clear_spare(struct nand_chip *chip, int size) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + int i; + + for (i =3D 0; i < size / 4; i++) + writel(0xff, nand->regs + MA35_NFI_REG_NANDRA0); +} + +static inline void read_remaining_bytes(struct ma35_nand_info *nand, u32 *= buf, + u32 offset, int size) +{ + u32 value =3D readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset); + u8 *ptr =3D (u8 *)buf; + int i; + + for (i =3D 0; i < size; i++) + ptr[i] =3D (value >> (i * 8)) & 0xff; +} + +static inline void ma35_read_spare(struct nand_chip *chip, int size, u32 *= buf, u32 offset) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + int i, j; + + if ((offset % 4) =3D=3D 0) { + for (i =3D 0, j =3D 0; i < size / 4; i++, j +=3D 4) + *buf++ =3D readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset + j); + + read_remaining_bytes(nand, buf, offset + j, size % 4); + } else { + read_remaining_bytes(nand, buf, offset, 4 - (offset % 4)); + offset +=3D 4; + size -=3D (4 - (offset % 4)); + + for (i =3D 0, j =3D 0; i < size / 4; i++, j +=3D 4) + *buf++ =3D readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset + j); + + read_remaining_bytes(nand, buf, offset + j, size % 4); + } +} + +static inline void ma35_write_spare(struct nand_chip *chip, int size, u32 = *buf) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + u32 value; + int i, j; + u8 *ptr; + + for (i =3D 0, j =3D 0; i < size / 4; i++, j +=3D 4) + writel(*buf++, nand->regs + MA35_NFI_REG_NANDRA0 + j); + + ptr =3D (u8 *)buf; + switch (size % 4) { + case 1: + writel(*ptr, nand->regs + MA35_NFI_REG_NANDRA0 + j); + break; + case 2: + value =3D *ptr | (*(ptr+1) << 8); + writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + j); + break; + case 3: + value =3D *ptr | (*(ptr+1) << 8) | (*(ptr+2) << 16); + writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + j); + break; + default: + break; + } +} + +static void ma35_nand_target_enable(struct nand_chip *chip, unsigned int c= s) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + u32 reg; + + switch (cs) { + case 0: + reg =3D readl(nand->regs + MA35_NFI_REG_NANDCTL); + writel(reg & ~DISABLE_CS0, nand->regs + MA35_NFI_REG_NANDCTL); + + reg =3D readl(nand->regs + MA35_NFI_REG_NANDINTSTS); + reg |=3D INT_RB0; + writel(reg, nand->regs + MA35_NFI_REG_NANDINTSTS); + break; + default: + break; + } +} + +static int ma35_nand_hwecc_init(struct nand_chip *chip, struct ma35_nand_i= nfo *nand) +{ + struct mtd_info *mtd =3D nand_to_mtd(chip); + u32 reg; + + /* Redundant area size */ + writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL); + + /* Protect redundant 3 bytes and disable ECC engine */ + reg =3D readl(nand->regs + MA35_NFI_REG_NANDCTL); + reg |=3D (PROT3BEN | ECC_CHK); + reg &=3D ~ECC_EN; + + if (chip->ecc.strength !=3D 0) { + chip->ecc.steps =3D mtd->writesize / chip->ecc.size; + /* Set BCH algorithm */ + reg &=3D ~BCH_MASK; + switch (chip->ecc.strength) { + case 8: + chip->ecc.total =3D chip->ecc.steps * MA35_PARITY_BCH8; + reg |=3D BCH_T8; + break; + case 12: + chip->ecc.total =3D chip->ecc.steps * MA35_PARITY_BCH12; + reg |=3D BCH_T12; + break; + case 24: + chip->ecc.total =3D chip->ecc.steps * MA35_PARITY_BCH24; + reg |=3D BCH_T24; + break; + default: + dev_err(nand->dev, "ECC strength unsupported\n"); + return -EINVAL; + } + + chip->ecc.bytes =3D chip->ecc.total / chip->ecc.steps; + } + writel(reg, nand->regs + MA35_NFI_REG_NANDCTL); + return 0; +} + +/* Correct data by BCH alrogithm */ +static void ma35_nfi_correct(struct nand_chip *chip, u8 index, + u8 err_cnt, u8 *addr) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + u32 temp_data[24], temp_addr[24]; + u32 padding_len, parity_len; + u32 value, offset, remain; + u32 err_data[6]; + u8 i, j; + + /* Configurations */ + if (chip->ecc.strength <=3D 8) { + parity_len =3D MA35_PARITY_BCH8; + padding_len =3D MA35_BCH_PADDING_512; + } else if (chip->ecc.strength <=3D 12) { + parity_len =3D MA35_PARITY_BCH12; + padding_len =3D MA35_BCH_PADDING_512; + } else if (chip->ecc.strength <=3D 24) { + parity_len =3D MA35_PARITY_BCH24; + padding_len =3D MA35_BCH_PADDING_1024; + } else { + dev_err(nand->dev, "Invalid BCH_TSEL =3D 0x%lx\n", + readl(nand->regs + MA35_NFI_REG_NANDCTL) & BCH_MASK); + return; + } + + /* + * got valid BCH_ECC_DATAx and parse them to temp_data[] + * got the valid register number of BCH_ECC_DATAx since + * one register include 4 error bytes + */ + j =3D (err_cnt + 3) / 4; + j =3D (j > 6) ? 6 : j; + for (i =3D 0; i < j; i++) + err_data[i] =3D readl(nand->regs + MA35_NFI_REG_NANDECCED0 + i * 4); + + for (i =3D 0; i < j; i++) { + temp_data[i*4+0] =3D err_data[i] & 0xff; + temp_data[i*4+1] =3D (err_data[i] >> 8) & 0xff; + temp_data[i*4+2] =3D (err_data[i] >> 16) & 0xff; + temp_data[i*4+3] =3D (err_data[i] >> 24) & 0xff; + } + + /* + * got valid REG_BCH_ECC_ADDRx and parse them to temp_addr[] + * got the valid register number of REG_BCH_ECC_ADDRx since + * one register include 2 error addresses + */ + j =3D (err_cnt + 1) / 2; + j =3D (j > 12) ? 12 : j; + for (i =3D 0; i < j; i++) { + temp_addr[i*2+0] =3D readl(nand->regs + MA35_NFI_REG_NANDECCEA0 + i * 4) + & 0x07ff; + temp_addr[i*2+1] =3D (readl(nand->regs + MA35_NFI_REG_NANDECCEA0 + i * 4) + >> 16) & 0x07ff; + } + + /* pointer to begin address of field that with data error */ + addr +=3D index * chip->ecc.steps; + + /* correct each error bytes */ + for (i =3D 0; i < err_cnt; i++) { + u32 corrected_index =3D temp_addr[i]; + + /* for wrong data in field */ + if (corrected_index < chip->ecc.steps) + *(addr + corrected_index) ^=3D temp_data[i]; + + /* for wrong first-3-bytes in redundancy area */ + else if (corrected_index < (chip->ecc.steps + 3)) { + corrected_index -=3D chip->ecc.steps; + temp_addr[i] +=3D (parity_len * index); /* field offset */ + + value =3D readl(nand->regs + MA35_NFI_REG_NANDRA0); + value ^=3D temp_data[i] << (8 * corrected_index); + writel(value, nand->regs + MA35_NFI_REG_NANDRA0); + } + /* + * for wrong parity code in redundancy area + * BCH_ERR_ADDRx =3D [data in field] + [3 bytes] + [xx] + [parity code] + * |<-- padding bytes -->| + * The BCH_ERR_ADDRx for last parity code always =3D field size + paddin= g size. + * So, the first parity code =3D field size + padding size - parity code= length. + * For example, for BCH T12, the first parity code =3D 512 + 32 - 23 =3D= 521. + * That is, error byte address offset within field is + */ + else { + corrected_index -=3D (chip->ecc.steps + padding_len - parity_len); + + /* + * final address =3D first parity code of first field + + * offset of fields + + * offset within field + */ + offset =3D (readl(nand->regs + MA35_NFI_REG_NANDRACTL) & 0x1ff) - + (parity_len * chip->ecc.steps) + + (parity_len * index) + corrected_index; + + remain =3D offset % 4; + value =3D readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset - remain); + value ^=3D temp_data[i] << (8 * remain); + writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + offset - remain); + } + } +} + +static int ma35_nfi_ecc_check(struct nand_chip *chip, u8 *addr) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + struct ma35_nand_chip *nvtnand =3D to_ma35_nand(chip); + struct mtd_info *mtd =3D nand_to_mtd(chip); + int maxbitflips =3D 0; + int cnt =3D 0; + u32 status; + int i, j; + + for (j =3D 0; j < nvtnand->nchunks; j++) { + status =3D readl(nand->regs + MA35_NFI_REG_NANDECCES0 + j * 4); + if (!status) + continue; + + for (i =3D 0; i < 4; i++) { + if ((status & ECC_STATUS_MASK) =3D=3D 0x01) { + /* Correctable error */ + cnt =3D (status >> 2) & ECC_ERR_CNT_MASK; + ma35_nfi_correct(chip, j * 4 + i, cnt, addr); + maxbitflips =3D max_t(u32, maxbitflips, cnt); + mtd->ecc_stats.corrected +=3D cnt; + } else { + /* Uncorrectable error */ + mtd->ecc_stats.failed++; + dev_warn(nand->dev, "uncorrectable error! 0x%4x\n", status); + return -EBADMSG; + } + status >>=3D 8; + } + } + return maxbitflips; +} + +static void ma35_nand_dmac_init(struct ma35_nand_info *nand) +{ + /* DMAC reset and enable */ + writel(DMA_RST | DMA_EN, nand->regs + MA35_NFI_REG_DMACTL); + writel(DMA_EN, nand->regs + MA35_NFI_REG_DMACTL); + + /* Clear DMA finished flag and enable */ + writel(INT_DMA | INT_ECC, nand->regs + MA35_NFI_REG_NANDINTSTS); + writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTEN); +} + +static int ma35_nand_do_write(struct nand_chip *chip, const u8 *addr, u32 = len) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + struct mtd_info *mtd =3D nand_to_mtd(chip); + dma_addr_t dma_addr; + int ret =3D 0, i; + u32 reg; + + if (len !=3D mtd->writesize) { + for (i =3D 0; i < len; i++) + writel(addr[i], nand->regs + MA35_NFI_REG_NANDDATA); + return 0; + } + + ma35_nand_dmac_init(nand); + + writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL); + + /* To mark this page as dirty. */ + reg =3D readl(nand->regs + MA35_NFI_REG_NANDRA0); + if (reg & 0xffff0000) + writel(reg & 0xffff, nand->regs + MA35_NFI_REG_NANDRA0); + + dma_addr =3D dma_map_single(nand->dev, (void *)addr, len, DMA_TO_DEVICE); + ret =3D dma_mapping_error(nand->dev, dma_addr); + if (ret) { + dev_err(nand->dev, "dma mapping error\n"); + return -EINVAL; + } + dma_sync_single_for_device(nand->dev, dma_addr, len, DMA_TO_DEVICE); + + reinit_completion(&nand->complete); + writel(dma_addr, nand->regs + MA35_NFI_REG_DMASA); + writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_W_EN, + nand->regs + MA35_NFI_REG_NANDCTL); + ret =3D wait_for_completion_timeout(&nand->complete, msecs_to_jiffies(100= 0)); + if (!ret) { + dev_err(nand->dev, "write timeout\n"); + ret =3D -ETIMEDOUT; + } + + dma_unmap_single(nand->dev, dma_addr, len, DMA_TO_DEVICE); + + return ret; +} + +static int ma35_nand_do_read(struct nand_chip *chip, u8 *addr, u32 len) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + struct mtd_info *mtd =3D nand_to_mtd(chip); + int ret =3D 0, cnt =3D 0, i; + dma_addr_t dma_addr; + u32 reg; + + if (len !=3D mtd->writesize) { + for (i =3D 0; i < len; i++) + addr[i] =3D readb(nand->regs + MA35_NFI_REG_NANDDATA); + return 0; + } + + ma35_nand_dmac_init(nand); + + writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL); + + /* Setup and start DMA using dma_addr */ + dma_addr =3D dma_map_single(nand->dev, (void *)addr, len, DMA_FROM_DEVICE= ); + ret =3D dma_mapping_error(nand->dev, dma_addr); + if (ret) { + dev_err(nand->dev, "dma mapping error\n"); + return -EINVAL; + } + + reinit_completion(&nand->complete); + writel(dma_addr, nand->regs + MA35_NFI_REG_DMASA); + writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_R_EN, + nand->regs + MA35_NFI_REG_NANDCTL); + ret =3D wait_for_completion_timeout(&nand->complete, msecs_to_jiffies(100= 0)); + if (!ret) { + dev_err(nand->dev, "read timeout\n"); + ret =3D -ETIMEDOUT; + } + + dma_unmap_single(nand->dev, dma_addr, len, DMA_FROM_DEVICE); + + reg =3D readl(nand->regs + MA35_NFI_REG_NANDINTSTS); + if (reg & INT_ECC) { + cnt =3D ma35_nfi_ecc_check(chip, addr); + if (cnt < 0) { + writel(DMA_RST | DMA_EN, nand->regs + MA35_NFI_REG_DMACTL); + writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | SWRST, + nand->regs + MA35_NFI_REG_NANDCTL); + } + writel(INT_ECC, nand->regs + MA35_NFI_REG_NANDINTSTS); + } + + ret =3D ret < 0 ? ret : cnt; + return ret; +} + +static int ma35_nand_write_page_hwecc(struct nand_chip *chip, const u8 *bu= f, + int oob_required, int page) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + struct mtd_info *mtd =3D nand_to_mtd(chip); + u32 reg; + + /* Enable HW ECC engine */ + reg =3D readl(nand->regs + MA35_NFI_REG_NANDCTL); + writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); + + ma35_nand_target_enable(chip, chip->cur_cs); + + ma35_clear_spare(chip, mtd->oobsize); + ma35_write_spare(chip, mtd->oobsize - chip->ecc.total, + (u32 *)chip->oob_poi); + + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + ma35_nand_do_write(chip, buf, mtd->writesize); + nand_prog_page_end_op(chip); + + ma35_read_spare(chip, chip->ecc.total, + (u32 *)(chip->oob_poi + (mtd->oobsize - chip->ecc.total)), + mtd->oobsize - chip->ecc.total); + + /* Disable HW ECC engine */ + writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); + + return 0; +} + +static int ma35_nand_read_page_hwecc(struct nand_chip *chip, u8 *buf, + int oob_required, int page) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + struct mtd_info *mtd =3D nand_to_mtd(chip); + int bitflips =3D 0; + u32 reg; + + /* Enable HW ECC engine */ + reg =3D readl(nand->regs + MA35_NFI_REG_NANDCTL); + writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); + + ma35_nand_target_enable(chip, chip->cur_cs); + nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); + ma35_write_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi); + + reg =3D readl(nand->regs + MA35_NFI_REG_NANDRA0); + if (PREFIX_RA_IS_EMPTY(reg)) { + memset((void *)buf, 0xff, mtd->writesize); + } else { + nand_read_page_op(chip, page, 0, NULL, 0); + bitflips =3D ma35_nand_do_read(chip, buf, mtd->writesize); + ma35_read_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi, 0); + } + + /* Disable HW ECC engine */ + reg =3D readl(nand->regs + MA35_NFI_REG_NANDCTL); + writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); + + return bitflips; +} + +static int ma35_nand_read_oob_hwecc(struct nand_chip *chip, int page) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + struct mtd_info *mtd =3D nand_to_mtd(chip); + u32 reg; + + ma35_nand_target_enable(chip, chip->cur_cs); + nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); + + /* copy OOB data to controller redundant area for page read */ + ma35_write_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi); + + reg =3D readl(nand->regs + MA35_NFI_REG_NANDRA0); + if (PREFIX_RA_IS_EMPTY(reg)) + memset((void *)chip->oob_poi, 0xff, mtd->oobsize); + + return 0; +} + +static inline void ma35_hw_init(struct ma35_nand_info *nand) +{ + u32 reg; + + /* Disable flash wp. */ + writel(DISABLE_WP, nand->regs + MA35_NFI_REG_NANDECTL); + + /* resets the internal state machine and counters */ + reg =3D readl(nand->regs + MA35_NFI_REG_NANDCTL); + reg |=3D SWRST; + writel(reg, nand->regs + MA35_NFI_REG_NANDCTL); +} + +static irqreturn_t ma35_nand_irq(int irq, void *id) +{ + struct ma35_nand_info *nand =3D (struct ma35_nand_info *)id; + u32 isr; + + isr =3D readl(nand->regs + MA35_NFI_REG_NANDINTSTS); + if (isr & INT_DMA) { + writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTSTS); + complete(&nand->complete); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static int ma35_nand_attach_chip(struct nand_chip *chip) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + struct ma35_nand_chip *nvtnand =3D to_ma35_nand(chip); + struct mtd_info *mtd =3D nand_to_mtd(chip); + struct device *dev =3D mtd->dev.parent; + u32 reg; + + if (chip->options & NAND_BUSWIDTH_16) { + dev_err(dev, "16 bits bus width not supported"); + return -EINVAL; + } + + nvtnand->nchunks =3D mtd->writesize / chip->ecc.steps; + nvtnand->nchunks =3D (nvtnand->nchunks < 4) ? 1 : nvtnand->nchunks / 4; + + reg =3D readl(nand->regs + MA35_NFI_REG_NANDCTL) & (~PSIZE_MASK); + if (mtd->writesize =3D=3D 2048) + writel(reg | PSIZE_2K, nand->regs + MA35_NFI_REG_NANDCTL); + else if (mtd->writesize =3D=3D 4096) + writel(reg | PSIZE_4K, nand->regs + MA35_NFI_REG_NANDCTL); + else if (mtd->writesize =3D=3D 8192) + writel(reg | PSIZE_8K, nand->regs + MA35_NFI_REG_NANDCTL); + + switch (chip->ecc.engine_type) { + case NAND_ECC_ENGINE_TYPE_ON_HOST: + chip->options |=3D NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA; + chip->ecc.write_page =3D ma35_nand_write_page_hwecc; + chip->ecc.read_page =3D ma35_nand_read_page_hwecc; + chip->ecc.read_oob =3D ma35_nand_read_oob_hwecc; + return ma35_nand_hwecc_init(chip, nand); + case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_SOFT: + case NAND_ECC_ENGINE_TYPE_ON_DIE: + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ma35_nfc_exec_instr(struct nand_chip *chip, + const struct nand_op_instr *instr) +{ + struct ma35_nand_info *nand =3D nand_get_controller_data(chip); + unsigned int i; + int ret =3D 0; + u32 status; + + switch (instr->type) { + case NAND_OP_CMD_INSTR: + writel(instr->ctx.cmd.opcode, nand->regs + MA35_NFI_REG_NANDCMD); + break; + case NAND_OP_ADDR_INSTR: + for (i =3D 0; i < instr->ctx.addr.naddrs; i++) { + if (i =3D=3D (instr->ctx.addr.naddrs - 1)) + writel(instr->ctx.addr.addrs[i] | ENDADDR, + nand->regs + MA35_NFI_REG_NANDADDR); + else + writel(instr->ctx.addr.addrs[i], + nand->regs + MA35_NFI_REG_NANDADDR); + } + break; + case NAND_OP_DATA_IN_INSTR: + ret =3D ma35_nand_do_read(chip, instr->ctx.data.buf.in, instr->ctx.data.= len); + break; + case NAND_OP_DATA_OUT_INSTR: + ret =3D ma35_nand_do_write(chip, instr->ctx.data.buf.out, instr->ctx.dat= a.len); + break; + case NAND_OP_WAITRDY_INSTR: + return readl_poll_timeout(nand->regs + MA35_NFI_REG_NANDINTSTS, status, + status & INT_RB0, 20, + instr->ctx.waitrdy.timeout_ms * MSEC_PER_SEC); + default: + ret =3D -EINVAL; + break; + } + + return ret; +} + +static int ma35_nfc_exec_op(struct nand_chip *chip, + const struct nand_operation *op, + bool check_only) +{ + int ret =3D 0; + u32 i; + + if (check_only) + return 0; + + ma35_nand_target_enable(chip, op->cs); + + for (i =3D 0; i < op->ninstrs; i++) { + ret =3D ma35_nfc_exec_instr(chip, &op->instrs[i]); + if (ret) + break; + } + + return ret; +} + +static const struct nand_controller_ops ma35_nfc_ops =3D { + .attach_chip =3D ma35_nand_attach_chip, + .exec_op =3D ma35_nfc_exec_op, +}; + +static int ma35_nand_chip_init(struct device *dev, struct ma35_nand_info *= nand, + struct device_node *np) +{ + struct ma35_nand_chip *nvtnand; + struct nand_chip *chip; + struct mtd_info *mtd; + int nsels; + u32 tmp; + int ret; + int i; + + if (!of_get_property(np, "reg", &nsels)) + return -ENODEV; + + nsels /=3D sizeof(u32); + if (!nsels || nsels > MA35_MAX_NSELS) { + dev_err(dev, "invalid reg property size %d\n", nsels); + return -EINVAL; + } + + nvtnand =3D devm_kzalloc(dev, struct_size(nvtnand, sels, nsels), + GFP_KERNEL); + if (!nvtnand) + return -ENOMEM; + + nvtnand->nsels =3D nsels; + for (i =3D 0; i < nsels; i++) { + ret =3D of_property_read_u32_index(np, "reg", i, &tmp); + if (ret) { + dev_err(dev, "reg property failure : %d\n", ret); + return ret; + } + + if (tmp >=3D MA35_MAX_NSELS) { + dev_err(dev, "invalid CS: %u\n", tmp); + return -EINVAL; + } + + if (test_and_set_bit(tmp, &nand->assigned_cs)) { + dev_err(dev, "CS %u already assigned\n", tmp); + return -EINVAL; + } + + nvtnand->sels[i] =3D tmp; + } + + chip =3D &nvtnand->chip; + chip->controller =3D &nand->controller; + + nand_set_flash_node(chip, np); + nand_set_controller_data(chip, nand); + + mtd =3D nand_to_mtd(chip); + mtd->owner =3D THIS_MODULE; + mtd->dev.parent =3D dev; + + mtd_set_ooblayout(mtd, &ma35_ooblayout_ops); + ret =3D nand_scan(chip, nsels); + if (ret) + return ret; + + ret =3D mtd_device_register(mtd, NULL, 0); + if (ret) { + dev_err(dev, "MTD parse partition error\n"); + nand_cleanup(chip); + return ret; + } + + list_add_tail(&nvtnand->node, &nand->chips); + + return 0; +} + +static void ma35_chips_cleanup(struct ma35_nand_info *nand) +{ + struct ma35_nand_chip *nvtnand, *tmp; + struct nand_chip *chip; + int ret; + + list_for_each_entry_safe(nvtnand, tmp, &nand->chips, node) { + chip =3D &nvtnand->chip; + ret =3D mtd_device_unregister(nand_to_mtd(chip)); + WARN_ON(ret); + nand_cleanup(chip); + list_del(&nvtnand->node); + } +} + +static int ma35_nand_chips_init(struct device *dev, struct ma35_nand_info = *nand) +{ + struct device_node *np =3D dev->of_node, *nand_np; + int nchips =3D of_get_child_count(np); + int ret; + + if (!nchips || nchips > MA35_MAX_NSELS) { + dev_err(dev, "incorrect number of NAND chips (%d)\n", nchips); + return -EINVAL; + } + + for_each_child_of_node(np, nand_np) { + ret =3D ma35_nand_chip_init(dev, nand, nand_np); + if (ret) { + of_node_put(nand_np); + ma35_chips_cleanup(nand); + return ret; + } + } + return 0; +} + +static int ma35_nand_probe(struct platform_device *pdev) +{ + struct ma35_nand_info *nand; + int ret =3D 0; + + nand =3D devm_kzalloc(&pdev->dev, sizeof(*nand), GFP_KERNEL); + if (!nand) + return -ENOMEM; + + nand_controller_init(&nand->controller); + INIT_LIST_HEAD(&nand->chips); + nand->controller.ops =3D &ma35_nfc_ops; + + init_completion(&nand->complete); + + nand->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(nand->regs)) + return PTR_ERR(nand->regs); + + nand->dev =3D &pdev->dev; + + nand->clk =3D devm_clk_get_enabled(&pdev->dev, "nand_gate"); + if (IS_ERR(nand->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(nand->clk), + "failed to find NAND clock\n"); + + nand->irq =3D platform_get_irq(pdev, 0); + if (nand->irq < 0) + return dev_err_probe(&pdev->dev, nand->irq, + "failed to get platform irq\n"); + + ret =3D devm_request_irq(&pdev->dev, nand->irq, ma35_nand_irq, + IRQF_TRIGGER_HIGH, "ma35d1-nand", nand); + if (ret) { + dev_err(&pdev->dev, "failed to request NAND irq\n"); + return -ENXIO; + } + + platform_set_drvdata(pdev, nand); + + writel(GRST | NAND_EN, nand->regs + MA35_NFI_REG_GCTL); + ma35_hw_init(nand); + ret =3D ma35_nand_chips_init(&pdev->dev, nand); + if (ret) { + dev_err(&pdev->dev, "failed to init NAND chips\n"); + clk_disable(nand->clk); + return ret; + } + + return ret; +} + +static void ma35_nand_remove(struct platform_device *pdev) +{ + struct ma35_nand_info *nand =3D platform_get_drvdata(pdev); + + ma35_chips_cleanup(nand); +} + +static const struct of_device_id ma35_nand_of_match[] =3D { + { .compatible =3D "nuvoton,ma35d1-nand" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ma35_nand_of_match); + +static struct platform_driver ma35_nand_driver =3D { + .driver =3D { + .name =3D "ma35d1-nand", + .of_match_table =3D ma35_nand_of_match, + }, + .probe =3D ma35_nand_probe, + .remove =3D ma35_nand_remove, +}; + +module_platform_driver(ma35_nand_driver); + +MODULE_DESCRIPTION("Nuvoton ma35 NAND driver"); +MODULE_AUTHOR("Hui-Ping Chen "); +MODULE_LICENSE("GPL"); --=20 2.25.1