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([77.85.230.22]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a913704easm449177466b.107.2024.10.23.02.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:18:05 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] arm64: dts: exynos8895: Add serial_0/1 nodes Date: Wed, 23 Oct 2024 12:17:33 +0300 Message-ID: <20241023091734.538682-5-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> References: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for serial_0 (UART_DBG) and serial_1 (UART_BT), which allows using them. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/d= ts/exynos/exynos8895.dtsi index e6c8a4966..ad50cd4f6 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -218,6 +218,19 @@ cmu_peric0: clock-controller@10400000 { "usi1", "usi2", "usi3"; }; =20 + serial_0: serial@10430000 { + compatible =3D "samsung,exynos8895-uart"; + reg =3D <0x10430000 0x100>; + clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_bus>; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + pinctrl_peric0: pinctrl@104d0000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x104d0000 0x1000>; @@ -250,6 +263,19 @@ cmu_peric1: clock-controller@10800000 { "usi10", "usi11", "usi12", "usi13"; }; =20 + serial_1: serial@10830000 { + compatible =3D "samsung,exynos8895-uart"; + reg =3D <0x10830000 0x100>; + clocks =3D <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_EXT_UCLK>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_bus>; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + pinctrl_peric1: pinctrl@10980000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x10980000 0x1000>; --=20 2.43.0