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([77.85.230.22]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a913704easm449177466b.107.2024.10.23.02.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:18:01 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] dt-bindings: timer: exynos4210-mct: Add samsung,exynos8895-mct compatible Date: Wed, 23 Oct 2024 12:17:30 +0300 Message-ID: <20241023091734.538682-2-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> References: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Just like most Samsung Exynos SoCs, Exynos8895 uses almost the same Multi-Core Timer block with no functional differences. Add dedicated samsung,exynos8895-mct compatible to the dt-schema for representing the MCT timer of Exynos8895 SoC. Signed-off-by: Ivaylo Ivanov Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/timer/samsung,exynos4210-mct.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct= .yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 774b7992a..02d1c3558 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -33,6 +33,7 @@ properties: - samsung,exynos5420-mct - samsung,exynos5433-mct - samsung,exynos850-mct + - samsung,exynos8895-mct - tesla,fsd-mct - const: samsung,exynos4210-mct =20 @@ -133,6 +134,7 @@ allOf: - samsung,exynos5420-mct - samsung,exynos5433-mct - samsung,exynos850-mct + - samsung,exynos8895-mct then: properties: interrupts: --=20 2.43.0 From nobody Mon Nov 25 23:24:12 2024 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E7161991BF; Wed, 23 Oct 2024 09:18:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675086; cv=none; b=P119qJyzaGbWGsScHN5keWHT6TAoRLsBsYItZMRPpkHaCYBgvcdM+RU2FLHEwyybtfcRo69wJcPNmXf492NpK54tKYoTr8DexlEoekcyrn6DAi5PTTwDqe985bt5BSNReC6JUlbjzaAOJ2eVUkVvwaun9irVA0e0yLWu8RtisVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675086; c=relaxed/simple; bh=2EKDBlrWUyLz/T4sq1AX6uXb3A+w25CeahBa+U/Rh6M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=U2Gojgy58RaChzRoq5Aao4nRkKgv5YHoAFp4X1mugl8vx327AXkfxRpDeHpmYj07KLSGcmu4pk4EP9wPLA93WOtFyRu0MlgBvQFkWG0rJ4KWzJqjnU6UFUd4orZghzKDCKZonqUmsUatCaG8GodB+oHA2kjNiqpFbYJ7EEowVaw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gtg5B9Ry; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gtg5B9Ry" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-5c9428152c0so8448573a12.1; Wed, 23 Oct 2024 02:18:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729675083; x=1730279883; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TukqJrYsDFG1DJAJmueEwaHQL71E3jPssuf+t5HzkMw=; b=gtg5B9RywrpWeB45LWgPJYZ0EXS/if2RRiJ5ZvseRlGUKi2HYHynnMi4+dux4JUG4C BIT0O3M+ZQfUBBMYUXhsySYH6rVkBA6ERlkZFeb3mXIUg3kIX7kwLF6WAOW1nD9cgyar VC77yyDaz0kKDMucQXfkQx4K4z/ZbatrNPtYOoMRaacVtT16UhFuYxnTIAgHANTyPF0B C7GeQAjq8LFGQAWeoRKVzasiLtKSNHMuhkEhjH61XG5fNT7CvGgabtU4jvG6GvdnZVOk 5s2KyAre9wd9g4slHNcKHaKnBVOCElXYlIcViBxQCc7eIt7ZrR9pWHNTqHjDVtiHgqZC 4DQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729675083; x=1730279883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TukqJrYsDFG1DJAJmueEwaHQL71E3jPssuf+t5HzkMw=; b=nEm3ixwUZCDB0ArV4b7fLJ01z77Jgl+Nn8FUSen68UHqgZWOr9v8AOwe6YgfaxaSB6 8FQ34LlPRUMY5rZWsJc3p+1X73y8zFhm7YpqMSxul0HVutVpgY58pNsG3ZjOZffr/O9I 2RVkAUBfZulrRO4flT62d6AvkznQO7Enu2RELAWibrKkFZ4h/7jJm84gcet6EmnQgmI/ N+wJC2kMaAZNm0Ea4yQg9offLYUTVMcCwtMzCgGQIS6v5jGV9SG7tFSgipX6u4CC33fp YE/fjI9ktJ0xLEIWs2n6a+ZuYGjHqZJ4CqCXHyoI8ghj0fAqz0j834iaNcq0W9XS2Fra 05pA== X-Forwarded-Encrypted: i=1; AJvYcCUJ1PpwJTnF+REpq6FrIVUkOL/BfnEFNo2iRcfeBQEDgWLIhfkLMKqKRGwlpnS26f+epdsd9ZG+42JG@vger.kernel.org, AJvYcCVd6vduMS44lwVbgMq2e6iK1jq2QW68mmwGfF8W7XRUHKiaSRby2KRK/TnY9r9TqxKuGuxtLC/6BFyBnXPo@vger.kernel.org X-Gm-Message-State: AOJu0YwyG+LAlRYjoRQwcrGm0aentbwMvQGFieNQvhdq/hZ9eDgPQDyB 990/2m81mIjAa2T4ey1aqm7HOW/kdIu4LDRLLtsIXlIgpCMcHuiO X-Google-Smtp-Source: AGHT+IHZv/+oJUevS4s8PoL1LtsFuNYgQymnDcOySsDEjVW2EW41HdvXfoHIx9nX4R1+73GpfVGcFw== X-Received: by 2002:a17:907:728a:b0:a9a:188f:efd9 with SMTP id a640c23a62f3a-a9abf8a828cmr166012466b.29.1729675083365; Wed, 23 Oct 2024 02:18:03 -0700 (PDT) Received: from ivaylo-T580.. ([77.85.230.22]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a913704easm449177466b.107.2024.10.23.02.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:18:03 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] arm64: dts: exynos8895: Add clock management unit nodes Date: Wed, 23 Oct 2024 12:17:31 +0300 Message-ID: <20241023091734.538682-3-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> References: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clock management unit nodes for: - cmu_top, which provides muxes, divs and gates for other CMUs - cmu_peris, which provides clocks for GIC and MCT - cmu_fsys0, which provides clocks for USBDRD30 - cmu_fsys1, which provides clocks for MMC, UFS and PCIE - cmu_peric0, which provides clocks for UART_DBG, USI00 ~ USI03 - cmu_peric1, which provides clocks for SPI_CAM0/1, UART_BT, USI04 ~ USI13 Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 85 ++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/d= ts/exynos/exynos8895.dtsi index 223ebd482..54037b0dc 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2024, Ivaylo Ivanov */ =20 +#include #include =20 / { @@ -159,6 +160,15 @@ chipid@10000000 { reg =3D <0x10000000 0x24>; }; =20 + cmu_peris: clock-controller@10010000 { + compatible =3D "samsung,exynos8895-cmu-peris"; + reg =3D <0x10010000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIS_BUS>; + clock-names =3D "oscclk", "bus"; + }; + gic: interrupt-controller@10201000 { compatible =3D "arm,gic-400"; reg =3D <0x10201000 0x1000>, @@ -173,24 +183,91 @@ gic: interrupt-controller@10201000 { #size-cells =3D <1>; }; =20 + cmu_peric0: clock-controller@10400000 { + compatible =3D "samsung,exynos8895-cmu-peric0"; + reg =3D <0x10400000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI00>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI01>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI02>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI03>; + clock-names =3D "oscclk", "bus", "uart", "usi0", + "usi1", "usi2", "usi3"; + }; + pinctrl_peric0: pinctrl@104d0000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x104d0000 0x1000>; interrupts =3D ; }; =20 + cmu_peric1: clock-controller@10800000 { + compatible =3D "samsung,exynos8895-cmu-peric1"; + reg =3D <0x10800000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM1>, + <&cmu_top CLK_DOUT_CMU_PERIC1_UART_BT>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI04>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI05>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI06>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI07>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI08>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI09>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI10>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI11>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI12>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI13>; + clock-names =3D "oscclk", "bus", "speedy", "cam0", + "cam1", "uart", "usi4", "usi5", + "usi6", "usi7", "usi8", "usi9", + "usi10", "usi11", "usi12", "usi13"; + }; + pinctrl_peric1: pinctrl@10980000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x10980000 0x1000>; interrupts =3D ; }; =20 + cmu_fsys0: clock-controller@11000000 { + compatible =3D "samsung,exynos8895-cmu-fsys0"; + reg =3D <0x11000000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS0_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS0_DPGTC>, + <&cmu_top CLK_DOUT_CMU_FSYS0_MMC_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS0_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS0_USBDRD30>; + clock-names =3D "oscclk", "bus", "dpgtc", "mmc", + "ufs", "usbdrd30"; + }; + pinctrl_fsys0: pinctrl@11050000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x11050000 0x1000>; interrupts =3D ; }; =20 + cmu_fsys1: clock-controller@11400000 { + compatible =3D "samsung,exynos8895-cmu-fsys1"; + reg =3D <0x11400000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS1_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>, + <&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>, + <&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>; + clock-names =3D "oscclk", "bus", "pcie", "ufs", "mmc"; + }; + pinctrl_fsys1: pinctrl@11430000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x11430000 0x1000>; @@ -213,6 +290,14 @@ pinctrl_busc: pinctrl@15a30000 { interrupts =3D ; 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([77.85.230.22]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a913704easm449177466b.107.2024.10.23.02.18.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:18:04 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] arm64: dts: exynos8895: Add Multi Core Timer (MCT) node Date: Wed, 23 Oct 2024 12:17:32 +0300 Message-ID: <20241023091734.538682-4-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> References: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MCT has one global timer and 8 CPU local timers. The global timer can generate 4 interrupts, and each local timer can generate an interrupt making 12 interrupts in total. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/d= ts/exynos/exynos8895.dtsi index 54037b0dc..e6c8a4966 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -169,6 +169,26 @@ cmu_peris: clock-controller@10010000 { clock-names =3D "oscclk", "bus"; }; =20 + timer@10040000 { + compatible =3D "samsung,exynos8895-mct", + "samsung,exynos4210-mct"; + reg =3D <0x10040000 0x800>; + clocks =3D <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>; + clock-names =3D "fin_pll", "mct"; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + }; + gic: interrupt-controller@10201000 { compatible =3D "arm,gic-400"; reg =3D <0x10201000 0x1000>, --=20 2.43.0 From nobody Mon Nov 25 23:24:12 2024 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C87019CD0B; Wed, 23 Oct 2024 09:18:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675089; cv=none; b=QeFwH+oRmJN6KHf59gF0V2X3DzHpinszC6Q4zAjdFQrNZoLF6K3/dk10ctSjvCE5XaYKL+ImYypfsYsmlStgXP4YMEThuTgsjND8gHKBOia/Gi/frFwFesKIV0r+U5l7L9PNBO/r2ETB0MDIN8hp5PpP/5Nn0CqUrjfACF7t2T8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675089; c=relaxed/simple; bh=G9yQ73mzQfERkRbKc4rb/2hcgcl+vwHdBNXjc0nLNNU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nTuzPKfdMoZ/B7VhO4PMOYynStYzh21Hi0TruAZdRKVxmMtAjE6O4Ms9jydNGr1sdMSeepzXmF7VYXcR+qkIWFrnXtI4mcO3CO6I67emLsg4+d6duuwdUTX9m5tcBfCMFMAt6k8rOa8CLiHv1jfvRsOmq6/ucNswlRGBh3AjEMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=A1oDzSnb; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="A1oDzSnb" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-a99eb8b607aso710876466b.2; Wed, 23 Oct 2024 02:18:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729675086; x=1730279886; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o3oz7XzRnYr4BG8E7Y3NV1EOsqUppoM4Gh7wTtLxU/8=; b=A1oDzSnbZnX/KyFfsFBHp7T54bZIVycVLc0MfaFjxFjbggaBtGABFqDx4c3Gm2Z/V0 NNuNyWNzAQCQd3MZauEErmbVitMxA0VP8VlgTmXtZDUXLLAb5Bra5Zg4uEFI7B7dvDJ2 PB08NzGOkkBPQekXT1aDctSfmW5lqIPs21dRw8BpH/4muroSImP/k69uAZNc9366rP5g ffvxivLizQreKZNgsLgfD8cwivdQTIwbn4ND6mqvT1uSZzrZCGCJtADwTpiTyv9/GvjD WhSH8vr2mkBRgi768Nl+i8lP+Omg4uNXDWSoXy/+GxNPjjhDMLphf5Y9GTXCuTUMCart cIsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729675086; x=1730279886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o3oz7XzRnYr4BG8E7Y3NV1EOsqUppoM4Gh7wTtLxU/8=; b=nwM32S1ZBXstGbmU28pRIH6RzZ467vk9hbvv9DYMG3n+6Opx2F8KloOTBDwFhXBcsx LVG9sf4B0R3kHq8AkLd90IEZpB3VfdPfOk8ftW9Xvls5Ao0yWJbDiy/o4N/4gOz8KGDl 6b573fvfL3WsJmjb6ZTQvxhsPpJ29IFJWEu8nqAlO5ay3HxIBqJZfWWoY9XeaiJSPUb9 MvVGCxHSMxFniCNsAHqgZ81nzYr9RGkobmIe5/NHAZMygbjaPNIVeezTH3A2LlKE8AYE hjL9zZr32st+Xu/HxhEDojzTbKC7bOCbNGdCxxcuNZng643fhL/8IGJd3ect0OFvHCpn Fc/A== X-Forwarded-Encrypted: i=1; AJvYcCUL5Rag0Yp4bXYjmA5ewUytIfC8aEAb/fNgFrpnOSC6I0ZLtRolfnEXsuixcK8Qn/6PQIQfnZea2ntnupSw@vger.kernel.org, AJvYcCXhoR+13PQn1S98mSbrT0w/7tBBqbdvp4rXlfE3m8SZY+mfCjkR7rH/cEC0nGUaHeWbxZvNvkryDLsx@vger.kernel.org X-Gm-Message-State: AOJu0YxFD8C0YBIWICa9ibWO6rz1/GrWNO3e/s8iQgrnybB7MlOU9qV/ duGLWv0IV0pCY/WrLzm5F+ufoKkDwXiE2OopscdJqNkWnUwEao4u X-Google-Smtp-Source: AGHT+IELm5faha5fBkO+OkQZoZplpoZtIS6VuriIaHnZFiemjbiSkn2GUdkWdEFBi9/ZsZQzY2BP8Q== X-Received: by 2002:a17:906:c150:b0:a9a:2afc:e4e3 with SMTP id a640c23a62f3a-a9abf92d226mr174401966b.50.1729675085910; Wed, 23 Oct 2024 02:18:05 -0700 (PDT) Received: from ivaylo-T580.. ([77.85.230.22]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a913704easm449177466b.107.2024.10.23.02.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:18:05 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] arm64: dts: exynos8895: Add serial_0/1 nodes Date: Wed, 23 Oct 2024 12:17:33 +0300 Message-ID: <20241023091734.538682-5-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> References: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for serial_0 (UART_DBG) and serial_1 (UART_BT), which allows using them. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/d= ts/exynos/exynos8895.dtsi index e6c8a4966..ad50cd4f6 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -218,6 +218,19 @@ cmu_peric0: clock-controller@10400000 { "usi1", "usi2", "usi3"; }; =20 + serial_0: serial@10430000 { + compatible =3D "samsung,exynos8895-uart"; + reg =3D <0x10430000 0x100>; + clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_bus>; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + pinctrl_peric0: pinctrl@104d0000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x104d0000 0x1000>; @@ -250,6 +263,19 @@ cmu_peric1: clock-controller@10800000 { "usi10", "usi11", "usi12", "usi13"; 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([77.85.230.22]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a913704easm449177466b.107.2024.10.23.02.18.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:18:06 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] arm64: dts: exynos8895: Add spi_0/1 nodes Date: Wed, 23 Oct 2024 12:17:34 +0300 Message-ID: <20241023091734.538682-6-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> References: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for spi_0 (SPI_CAM0) and spi_1 (SPI_CAM1), which allows using them. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/d= ts/exynos/exynos8895.dtsi index ad50cd4f6..ee393f4f0 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -282,6 +282,36 @@ pinctrl_peric1: pinctrl@10980000 { interrupts =3D ; }; =20 + spi_0: spi@109d0000 { + compatible =3D "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg =3D <0x109d0000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK>; + clock-names =3D "spi", "spi_busclk0"; + interrupts =3D ; + pinctrl-0 =3D <&spi0_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + spi_1: spi@109e0000 { + compatible =3D "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg =3D <0x109e0000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK>; + clock-names =3D "spi", "spi_busclk0"; + interrupts =3D ; + pinctrl-0 =3D <&spi1_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + cmu_fsys0: clock-controller@11000000 { compatible =3D "samsung,exynos8895-cmu-fsys0"; reg =3D <0x11000000 0x8000>; --=20 2.43.0