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Wed, 23 Oct 2024 09:13:18 +0000 From: Bhavin Sharma To: shawnguo@kernel.org Cc: Bhavin Sharma , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Peng Fan , Joao Paulo Goncalves , Hiago De Franco , Hugo Villeneuve , Mathieu Othacehe , Alexander Stein , Michael Walle , Gregor Herburger , Parthiban Nallathambi , Max Merchel , Tim Harvey , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/2] arm64: dts: imx8mp: Add Boundary Device Nitrogen8MP Universal SMARC Carrier Board Date: Wed, 23 Oct 2024 14:41:14 +0530 Message-ID: <20241023091231.10050-2-bhavin.sharma@siliconsignals.io> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241023091231.10050-1-bhavin.sharma@siliconsignals.io> References: <20241023091231.10050-1-bhavin.sharma@siliconsignals.io> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: PN2PEPF000001B4.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c04::6) To PN3P287MB1171.INDP287.PROD.OUTLOOK.COM (2603:1096:c01:1a1::5) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PN3P287MB1171:EE_|PN2PPFDCD372071:EE_ X-MS-Office365-Filtering-Correlation-Id: e45e11d2-7283-463e-4e37-08dcf342eece X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|376014|366016|52116014|38350700014; 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charset="utf-8" Adds the DTSI file for the Nitrogen8MP SMARC System on Module which is delivered with the Nitrogen8MP Universal SMARC Carrier Board. Initial support includes: - Serial console - eMMC - SD card Signed-off-by: Bhavin Sharma --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mp-nitrogen-smarc-som.dtsi | 348 ++++++++++++++++++ .../imx8mp-nitrogen-smarc-universal-board.dts | 17 + 3 files changed, 366 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som= .dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-uni= versal-board.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 9d3df8b218a2..c7f4cf51dc14 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -173,6 +173,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-navqp.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-nitrogen-smarc-universal-board.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-rdk-no-eth-dtbs +=3D imx8mp-phyboard-pollux-rdk.dtb= imx8mp-phycore-no-eth.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-rdk-no-eth.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi b= /arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi new file mode 100644 index 000000000000..a85acb422000 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Boundary Devices + * Copyright 2024 Silicon Signals Pvt. Ltd. + * + * Author : Bhavin Sharma + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model =3D "Boundary Device Nitrogen8MP SMARC SoM"; + compatible =3D "boundary,imx8mp-nitrogen-smarc-som", "fsl,imx8mp"; + + chosen { + stdout-path =3D &uart2; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_led>; + + led-0 { + function =3D LED_FUNCTION_POWER; + gpios =3D <&gpio1 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply =3D <&buck2>; +}; + +&A53_1 { + cpu-supply =3D <&buck2>; +}; + +&A53_2 { + cpu-supply =3D <&buck2>; +}; + +&A53_3 { + cpu-supply =3D <&buck2>; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + status =3D "okay"; + + pmic@25 { + compatible =3D "nxp,pca9450c"; + reg =3D <0x25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <14 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name =3D "BUCK1"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck2: BUCK2 { + regulator-name =3D "BUCK2"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <950000>; + nxp,dvs-standby-voltage =3D <850000>; + }; + + buck4: BUCK4 { + regulator-name =3D "BUCK4"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name =3D "BUCK5"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name =3D "BUCK6"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1600000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name =3D "LDO3"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name =3D "LDO5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c6 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c6>; + status =3D "okay"; + + mcp23018: gpio@20 { + compatible =3D "microchip,mcp23018"; + gpio-controller; + #gpio-cells =3D <0x2>; + reg =3D <0x20>; + interrupts-extended =3D <&gpio4 22 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells =3D <0x2>; + microchip,irq-mirror; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mcp23018>; + reset-gpios =3D <&gpio4 27 GPIO_ACTIVE_LOW>; + }; +}; + +/* Console */ +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +/* SD-card */ +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + status =3D "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_gpio_led: gpioledgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 + >; + }; + + pinctrl_mcp23018: mcp23018grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1c0 + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x100 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x10 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x150 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x150 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x150 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x150 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x150 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x150 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x150 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x150 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x150 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x10 + MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x140 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x14 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x154 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x154 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x154 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x154 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x154 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x154 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x154 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x154 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x154 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x14 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x12 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x152 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x152 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x152 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x152 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x152 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x152 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x152 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x152 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x152 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x12 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-= board.dts b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-b= oard.dts new file mode 100644 index 000000000000..4a08fa38dcde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.d= ts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Boundary Devices + * Copyright 2024 Silicon Signals Pvt. Ltd. + * + * Author : Bhavin Sharma + */ + +/dts-v1/; + +#include "imx8mp-nitrogen-smarc-som.dtsi" + +/ { + model =3D "Boundary Device Nitrogen8MP Universal SMARC Carrier Board"; + compatible =3D "boundary,imx8mp-nitrogen-smarc-universal-board", + "boundary,imx8mp-nitrogen-smarc-som", "fsl,imx8mp"; +}; -- 2.43.0 From nobody Mon Nov 25 23:41:03 2024 Received: from IND01-MAX-obe.outbound.protection.outlook.com (mail-maxind01on2097.outbound.protection.outlook.com [40.107.222.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7A9E15B547; Wed, 23 Oct 2024 09:13:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.222.97 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729674817; cv=fail; b=mZNeY9nv88BXYp8yotcYiFdNQihWWMv+0hQya1DMgPaHFekXBQOzgCBxJMxaoz6UGxPYn8oMhLFqG7a1U0dFGoX8df3cUUrLGcBr+1zRlBL15aYpQeL4qRT9lTMbcLS1145grkvUK2Ig1NpInIKH4vfG8Rf7VMy3YT3/KJR//oQ= ARC-Message-Signature: i=2; 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charset="utf-8" Adds support for the Nitrogen8MP SMARC System on Module and the Nitrogen8MP Universal SMARC Carrier Board. Signed-off-by: Bhavin Sharma Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index b39a7e031177..58979c030519 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1097,6 +1097,12 @@ properties: - const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM - const: fsl,imx8mp =20 + - description: Boundary Device Nitrogen8MP Universal SMARC Carrier B= oard + items: + - const: boundary,imx8mp-nitrogen-smarc-universal-board + - const: boundary,imx8mp-nitrogen-smarc-som + - const: fsl,imx8mp + - description: i.MX8MP DHCOM based Boards items: - enum: --=20 2.43.0