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([77.85.230.22]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a9159a23csm442767466b.205.2024.10.23.02.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:01:43 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] clk: samsung: clk-pll: Add support for pll_{1051x,1052x} Date: Wed, 23 Oct 2024 12:01:35 +0300 Message-ID: <20241023090136.537395-3-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241023090136.537395-1-ivo.ivanov.ivanov1@gmail.com> References: <20241023090136.537395-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These plls are found in the Exynos8895 SoC: - pll1051x: Integer PLL with middle frequency - pll1052x: Integer PLL with low frequency The PLLs are similar enough to pll_0822x, so the same code can handle all. Locktime for 1051x, 1052x is 150 - the same as the pll_0822x lock factor. MDIV, SDIV, PDIV masks and bit shifts are also the same as 0822x. When defining a PLL, the "con" parameter should be set to CON0 register, like this: PLL(pll_1051x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, pll_shared0_rate_table), Signed-off-by: Ivaylo Ivanov --- drivers/clk/samsung/clk-pll.c | 2 ++ drivers/clk/samsung/clk-pll.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index cca3e6309..be6b51694 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1370,6 +1370,8 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, break; case pll_1417x: case pll_1418x: + case pll_1051x: + case pll_1052x: case pll_0818x: case pll_0822x: case pll_0516x: diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 3481941ba..858ab367e 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -43,6 +43,8 @@ enum samsung_pll_type { pll_0517x, pll_0518x, pll_531x, + pll_1051x, + pll_1052x, }; =20 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ --=20 2.43.0