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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 05:51:50.9175 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e64a0c13-c095-48da-591d-08dcf326ca77 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8128 Content-Type: text/plain; charset="utf-8" Add AMDI0015 _HID for Designware I3C driver so that the dw-i3c-master driver can be probed on AMD platforms. Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/dw-i3c-master.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 8d694672c110..1a7c300b6d45 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -1748,12 +1748,19 @@ static const struct of_device_id dw_i3c_master_of_m= atch[] =3D { }; MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); =20 +static const struct acpi_device_id amd_i3c_device_match[] =3D { + { "AMDI0015" }, + { } +}; +MODULE_DEVICE_TABLE(acpi, amd_i3c_device_match); + static struct platform_driver dw_i3c_driver =3D { .probe =3D dw_i3c_probe, .remove_new =3D dw_i3c_remove, .driver =3D { .name =3D "dw-i3c-master", .of_match_table =3D dw_i3c_master_of_match, + .acpi_match_table =3D amd_i3c_device_match, .pm =3D &dw_i3c_pm_ops, }, }; --=20 2.34.1 From nobody Tue Nov 26 01:37:48 2024 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2040.outbound.protection.outlook.com [40.107.93.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BCB2146A68 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 05:51:53.7327 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3eabae4b-8b96-4832-ebf7-08dcf326cc24 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8196 Content-Type: text/plain; charset="utf-8" On AMD platforms, the IRQ lines are shared between two instances of I3C. Add IRQF_SHARED flag during the interrupt registration process. Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/dw-i3c-master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 1a7c300b6d45..fd58a95ae1c3 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -1578,7 +1578,7 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, writel(INTR_ALL, master->regs + INTR_STATUS); irq =3D platform_get_irq(pdev, 0); ret =3D devm_request_irq(&pdev->dev, irq, - dw_i3c_master_irq_handler, 0, + dw_i3c_master_irq_handler, IRQF_SHARED, dev_name(&pdev->dev), master); if (ret) goto err_assert_rst; --=20 2.34.1 From nobody Tue Nov 26 01:37:48 2024 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2068.outbound.protection.outlook.com [40.107.244.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4938C1487D6 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 05:51:55.5921 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b217cab-f281-45b8-a367-08dcf326cd40 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7684 Content-Type: text/plain; charset="utf-8" As of now, the I3C subsystem only has ARM-specific initialization, and there is no corresponding ACPI plumbing present. To address this, ACPI support needs to be added to both the I3C core and DW driver. Add support to get the ACPI handle from the _HID probed and parse the apci object to retrieve the slave information from BIOS. Based on the acpi object information propogated via BIOS, build the i3c board information so that the same information can be used across the driver to handle the slave requests. Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/i3c/internals.h | 2 + drivers/i3c/master.c | 84 ++++++++++++++++++++++++++++++ drivers/i3c/master/dw-i3c-master.c | 7 +++ include/linux/i3c/master.h | 1 + 4 files changed, 94 insertions(+) diff --git a/drivers/i3c/internals.h b/drivers/i3c/internals.h index 433f6088b7ce..d2d6c69b19dd 100644 --- a/drivers/i3c/internals.h +++ b/drivers/i3c/internals.h @@ -10,6 +10,8 @@ =20 #include =20 +#define AMD_I3C_GET_SLAVE_ADDR 0x30 + void i3c_bus_normaluse_lock(struct i3c_bus *bus); void i3c_bus_normaluse_unlock(struct i3c_bus *bus); =20 diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 6f3eb710a75d..7d23c32e1c0f 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -2251,6 +2251,84 @@ static int of_i3c_master_add_dev(struct i3c_master_c= ontroller *master, return ret; } =20 +#if IS_ENABLED(CONFIG_ACPI) +static int i3c_acpi_configure_master(struct i3c_master_controller *master) +{ + struct acpi_buffer buf =3D {ACPI_ALLOCATE_BUFFER, NULL}; + enum i3c_addr_slot_status addrstatus; + struct i3c_dev_boardinfo *boardinfo; + struct device *dev =3D &master->dev; + struct fwnode_handle *fwnode; + struct acpi_device *adev; + u32 slv_addr, num_dev; + acpi_status status; + u64 val; + + status =3D acpi_evaluate_object_typed(master->ahandle, "_DSD", NULL, &buf= , ACPI_TYPE_PACKAGE); + if (ACPI_FAILURE(status)) { + dev_err(&master->dev, "Error reading _DSD:%s\n", acpi_format_exception(s= tatus)); + return -ENODEV; + } + + num_dev =3D device_get_child_node_count(dev); + if (!num_dev) { + dev_err(&master->dev, "Error: no child node present\n"); + return -EINVAL; + } + + device_for_each_child_node(dev, fwnode) { + adev =3D to_acpi_device_node(fwnode); + if (!adev) + return -ENODEV; + + status =3D acpi_evaluate_integer(adev->handle, "_ADR", NULL, &val); + if (ACPI_FAILURE(status)) { + dev_err(&master->dev, "Error: eval _ADR failed\n"); + return -EINVAL; + } + slv_addr =3D val >> AMD_I3C_GET_SLAVE_ADDR; + + boardinfo =3D devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL); + if (!boardinfo) + return -ENOMEM; + + if (slv_addr) { + if (slv_addr > I3C_MAX_ADDR) + return -EINVAL; + + addrstatus =3D i3c_bus_get_addr_slot_status(&master->bus, slv_addr); + if (addrstatus !=3D I3C_ADDR_SLOT_FREE) + return -EINVAL; + } + + boardinfo->static_addr =3D slv_addr; + if (boardinfo->static_addr > I3C_MAX_ADDR) + return -EINVAL; + + addrstatus =3D i3c_bus_get_addr_slot_status(&master->bus, boardinfo->sta= tic_addr); + if (addrstatus !=3D I3C_ADDR_SLOT_FREE) + return -EINVAL; + + boardinfo->pid =3D (val & GENMASK(47, 0)); + if ((boardinfo->pid & GENMASK_ULL(63, 48)) || + I3C_PID_RND_LOWER_32BITS(boardinfo->pid)) + return -EINVAL; + + /* + * According to the specification, SETDASA is not supported for DIMM sla= ves + * during device discovery. Therefore, AMD BIOS will populate same initi= al + * dynamic address as the static address. + */ + boardinfo->init_dyn_addr =3D boardinfo->static_addr; + list_add_tail(&boardinfo->node, &master->boardinfo.i3c); + } + + return 0; +} +#else +static int i3c_acpi_configure_master(struct i3c_master_controller *master)= { return 0; } +#endif + static int of_populate_i3c_bus(struct i3c_master_controller *master) { struct device *dev =3D &master->dev; @@ -2771,6 +2849,12 @@ int i3c_master_register(struct i3c_master_controller= *master, master->dev.coherent_dma_mask =3D parent->coherent_dma_mask; master->dev.dma_parms =3D parent->dma_parms; =20 + if (has_acpi_companion(master->dev.parent)) { + ret =3D i3c_acpi_configure_master(master); + if (ret < 0) + return ret; + } + ret =3D of_populate_i3c_bus(master); if (ret) goto err_put_dev; diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index fd58a95ae1c3..f683e2a398ad 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -1602,6 +1602,13 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, master->maxdevs =3D ret >> 16; master->free_pos =3D GENMASK(master->maxdevs - 1, 0); =20 +#if IS_ENABLED(CONFIG_ACPI) + ACPI_COMPANION_SET(&master->base.dev, ACPI_COMPANION(&pdev->dev)); + master->base.ahandle =3D acpi_device_handle(ACPI_COMPANION(&pdev->dev)); + if (!master->base.ahandle) + dev_err(&pdev->dev, "Failed to get acpi device handle\n"); +#endif + INIT_WORK(&master->hj_work, dw_i3c_hj_work); ret =3D i3c_master_register(&master->base, &pdev->dev, &dw_mipi_i3c_ops, false); diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index 2a1ed05d5782..367faf7c4bf3 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -523,6 +523,7 @@ struct i3c_master_controller { } boardinfo; struct i3c_bus bus; struct workqueue_struct *wq; + acpi_handle ahandle; }; =20 /** --=20 2.34.1 From nobody Tue Nov 26 01:37:49 2024 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2055.outbound.protection.outlook.com [40.107.94.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA2081465AE for ; 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Wed, 23 Oct 2024 00:51:55 -0500 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: , , , Shyam Sundar S K Subject: [PATCH v2 4/6] i3c: master: Add a routine to include the I3C SPD device Date: Wed, 23 Oct 2024 11:21:16 +0530 Message-ID: <20241023055118.1400286-5-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241023055118.1400286-1-Shyam-sundar.S-k@amd.com> References: <20241023055118.1400286-1-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|DM4PR12MB6374:EE_ X-MS-Office365-Filtering-Correlation-Id: ae84aab0-8cc4-47b5-b1d4-08dcf326ce9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 05:51:57.8706 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae84aab0-8cc4-47b5-b1d4-08dcf326ce9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6374 Content-Type: text/plain; charset="utf-8" Implement the i3c_master_add_spd_dev() function in the I3C master to handle SPD (Serial Presence Detect) device creation and map the board information into the I3C device structure. Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/i3c/master.c | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 7d23c32e1c0f..ba6f17cb8aa6 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -1657,6 +1657,45 @@ i3c_master_register_new_i3c_devs(struct i3c_master_c= ontroller *master) } } =20 +static int i3c_master_add_spd_dev(struct i3c_master_controller *master, + struct i3c_dev_boardinfo *boardinfo) +{ + struct i3c_dev_desc *i3cdev; + int ret; + + list_for_each_entry(boardinfo, &master->boardinfo.i3c, node) { + struct i3c_device_info info =3D { + .static_addr =3D boardinfo->static_addr, + }; + + ret =3D i3c_bus_get_addr_slot_status(&master->bus, boardinfo->static_add= r); + if (ret !=3D I3C_ADDR_SLOT_FREE) + return -EBUSY; + + i3cdev =3D i3c_master_alloc_i3c_dev(master, &info); + if (IS_ERR(i3cdev)) + return -ENOMEM; + + i3cdev->boardinfo =3D boardinfo; + ret =3D i3c_master_attach_i3c_dev(master, i3cdev); + if (ret) + goto err_free_dev; + + i3cdev->info.pid =3D i3cdev->boardinfo->pid; + i3cdev->info.dyn_addr =3D i3cdev->boardinfo->init_dyn_addr; + + i3c_bus_normaluse_lock(&master->bus); + i3c_master_register_new_i3c_devs(master); + i3c_bus_normaluse_unlock(&master->bus); + } + + return 0; + +err_free_dev: + i3c_master_free_i3c_dev(i3cdev); + return ret; +} + /** * i3c_master_do_daa() - do a DAA (Dynamic Address Assignment) * @master: master doing the DAA @@ -1814,7 +1853,7 @@ static int i3c_master_bus_init(struct i3c_master_cont= roller *master) { enum i3c_addr_slot_status status; struct i2c_dev_boardinfo *i2cboardinfo; - struct i3c_dev_boardinfo *i3cboardinfo; + struct i3c_dev_boardinfo *i3cboardinfo =3D NULL; struct i2c_dev_desc *i2cdev; int ret; =20 @@ -1868,6 +1907,8 @@ static int i3c_master_bus_init(struct i3c_master_cont= roller *master) goto err_bus_cleanup; } =20 + i3c_master_add_spd_dev(master, i3cboardinfo); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 05:52:00.0500 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1cc4cf09-483f-444f-3ec9-08dcf326cfeb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7822 Content-Type: text/plain; charset="utf-8" I3C devices like DIMMs over SPD use SETAASA for bus discovery instead of SETDASA. Add a new routine for I3C host controller drivers to use. If the I3C slave on the bus is an SPD device, skip the regular DAA process. According to the SPD spec[1], use SETAASA for bus discovery, and avoid sending RSTDAA and DISEC, as they are considered illegal. Skip this entire process if the slave is SPD-compliant, as indicated by the "jdec_spd" flag from the BIOS. [1] https://www.jedec.org/system/files/docs/JESD300-5B.01.pdf (section 2.4 and 2.6.3) Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/i3c/master.c | 32 +++++++++++++++++++++++++++++- drivers/i3c/master/dw-i3c-master.c | 1 + include/linux/i3c/ccc.h | 1 + include/linux/i3c/master.h | 1 + 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index ba6f17cb8aa6..1596efd6d82a 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -1657,6 +1657,21 @@ i3c_master_register_new_i3c_devs(struct i3c_master_c= ontroller *master) } } =20 +static int i3c_master_setaasa_locked(struct i3c_master_controller *master) +{ + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0); + i3c_ccc_cmd_init(&cmd, false, I3C_CCC_SETAASA, &dest, 1); + + ret =3D i3c_master_send_ccc_cmd_locked(master, &cmd); + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + static int i3c_master_add_spd_dev(struct i3c_master_controller *master, struct i3c_dev_boardinfo *boardinfo) { @@ -1684,6 +1699,10 @@ static int i3c_master_add_spd_dev(struct i3c_master_= controller *master, i3cdev->info.pid =3D i3cdev->boardinfo->pid; i3cdev->info.dyn_addr =3D i3cdev->boardinfo->init_dyn_addr; =20 + ret =3D i3c_master_setaasa_locked(master); + if (ret) + goto err_free_dev; + i3c_bus_normaluse_lock(&master->bus); i3c_master_register_new_i3c_devs(master); i3c_bus_normaluse_unlock(&master->bus); @@ -1907,7 +1926,14 @@ static int i3c_master_bus_init(struct i3c_master_con= troller *master) goto err_bus_cleanup; } =20 - i3c_master_add_spd_dev(master, i3cboardinfo); + /* + * If the I3C slave on the bus is SPD device, then do not follow the regu= lar + * DAA process. Also, as per SPD spec SETAASA is required for the bus dis= covery + * and sending RSTDAA and DISEC is considered as illegal. So skip the ent= ire process + * if the jdec_spd flag has been identified from the BIOS. + */ + if (master->jdec_spd) + return i3c_master_add_spd_dev(master, i3cboardinfo); =20 if (master->ops->set_speed) { ret =3D master->ops->set_speed(master, I3C_OPEN_DRAIN_SLOW_SPEED); @@ -2311,6 +2337,10 @@ static int i3c_acpi_configure_master(struct i3c_mast= er_controller *master) return -ENODEV; } =20 + status =3D acpi_evaluate_object(master->ahandle, "_STR", NULL, NULL); + if (ACPI_SUCCESS(status)) + master->jdec_spd =3D true; + num_dev =3D device_get_child_node_count(dev); if (!num_dev) { dev_err(&master->dev, "Error: no child node present\n"); diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index f683e2a398ad..90a43209e55e 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -282,6 +282,7 @@ static bool dw_i3c_master_supports_ccc_cmd(struct i3c_m= aster_controller *m, case I3C_CCC_GETSTATUS: case I3C_CCC_GETMXDS: case I3C_CCC_GETHDRCAP: + case I3C_CCC_SETAASA: return true; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 05:52:03.4094 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79b892f9-7bd3-47a4-d852-08dcf326d1eb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4396 Content-Type: text/plain; charset="utf-8" The AMD Legacy I3C is having a problem with its IP, specifically with the push-pull and open-drain pull-up registers. These registers need to be manually programmed for every CCC submission to align with the duty cycle. Therefore, add a quirk to address this issue. Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/dw-i3c-master.c | 29 ++++++++++++++++++++++++++++- drivers/i3c/master/dw-i3c-master.h | 1 + 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 90a43209e55e..226c9946c4b7 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -220,6 +220,14 @@ =20 #define XFER_TIMEOUT (msecs_to_jiffies(1000)) #define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */ + +/* Timing values to configure 12.5MHz frequency */ +#define AMD_I3C_OD_TIMING 0x4C007C +#define AMD_I3C_PP_TIMING 0x8001A + +/* List of quirks */ +#define AMD_I3C_OD_PP_TIMING BIT(1) + struct dw_i3c_cmd { u32 cmd_lo; u32 cmd_hi; @@ -795,6 +803,12 @@ static int dw_i3c_ccc_get(struct dw_i3c_master *master= , struct i3c_ccc_cmd *ccc) return ret; } =20 +static void amd_configure_od_pp_quirk(struct dw_i3c_master *master) +{ + master->i3c_od_timing =3D AMD_I3C_OD_TIMING; + master->i3c_pp_timing =3D AMD_I3C_PP_TIMING; +} + static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, struct i3c_ccc_cmd *ccc) { @@ -804,6 +818,13 @@ static int dw_i3c_master_send_ccc_cmd(struct i3c_maste= r_controller *m, if (ccc->id =3D=3D I3C_CCC_ENTDAA) return -EINVAL; =20 + /* AMD platform specific OD and PP timings */ + if (master->quirks & AMD_I3C_OD_PP_TIMING) { + amd_configure_od_pp_quirk(master); + writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING); + writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING); + } + ret =3D pm_runtime_resume_and_get(master->dev); if (ret < 0) { dev_err(master->dev, @@ -1610,6 +1631,8 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, dev_err(&pdev->dev, "Failed to get acpi device handle\n"); #endif =20 + master->quirks =3D (unsigned long)device_get_match_data(&pdev->dev); + INIT_WORK(&master->hj_work, dw_i3c_hj_work); ret =3D i3c_master_register(&master->base, &pdev->dev, &dw_mipi_i3c_ops, false); @@ -1683,6 +1706,10 @@ static void dw_i3c_master_restore_addrs(struct dw_i3= c_master *master) =20 static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master) { + /* AMD platform specific OD and PP timings */ + if (master->quirks & AMD_I3C_OD_PP_TIMING) + amd_configure_od_pp_quirk(master); + writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING); writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING); writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING); @@ -1757,7 +1784,7 @@ static const struct of_device_id dw_i3c_master_of_mat= ch[] =3D { MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); =20 static const struct acpi_device_id amd_i3c_device_match[] =3D { - { "AMDI0015" }, + { "AMDI0015", AMD_I3C_OD_PP_TIMING }, { } }; MODULE_DEVICE_TABLE(acpi, amd_i3c_device_match); diff --git a/drivers/i3c/master/dw-i3c-master.h b/drivers/i3c/master/dw-i3c= -master.h index 219ff815d3a7..c5cb695c16ab 100644 --- a/drivers/i3c/master/dw-i3c-master.h +++ b/drivers/i3c/master/dw-i3c-master.h @@ -50,6 +50,7 @@ struct dw_i3c_master { u32 bus_free_timing; u32 i2c_fm_timing; u32 i2c_fmp_timing; + u32 quirks; /* * Per-device hardware data, used to manage the device address table * (DAT) --=20 2.34.1