From nobody Tue Nov 26 02:28:00 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBF581A29A for ; Wed, 23 Oct 2024 00:09:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729642172; cv=none; b=ZKwJ191dtPMzwzaMbMceKvISzI5M+4BypBCNg2gK2Puy5iI3AQJz1sacRtK0ihUEgwpq+3YooXqFOa2UQibqlK1e8lInfwJzZNzhxR5juRMj9s60OWJnWnEjNuL+kqQPNqETxBD52VqqeWyTQ5Ajp7hBOXoDlSGKVSEpHuqrwFw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729642172; c=relaxed/simple; bh=bMrbyixiaTcC6Gds/aupKMLHu7/KWuPTgmG7iuWeJzA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hMtBS+z/ng/jb3p0pFfuiicYw+gsymy/U8Vx/Vr5LC+eD5IS0AC8HdhIGolL+5LylAvk0LK/Hj8lf6btPc40MMWjkC893GfS9gJr84XFbZD/HksP4MuerELFbIdAXJX6b4zt+moyW5SffsN7crGFSvjMVaytEpjuxl9Xi2aglLY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qI+Ib8ad; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qI+Ib8ad" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 59707C4CEEB; Wed, 23 Oct 2024 00:09:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729642172; bh=bMrbyixiaTcC6Gds/aupKMLHu7/KWuPTgmG7iuWeJzA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qI+Ib8adVXoFyAH5MTW9Fle/MgxaJ0Oy29gZwuUR2jUQKZ6x85b11WxETOHSofKID aPstWvIw5gA4Xl9cid5AOqXUBj6CFWNqIsGyth5xq+9TRdFDQWLKKpjubYxNdcxy9c 72TiYtJJUvIR5rEP8DNjZ8BVaSIW59gMqJz8vr8ZRvrgwBa1ZgGhZfbgq1T8xwuDUt CRiMA72ai1fOOgmZmhEop4PXCURcmnaBa1/FCwMtDQZGjENT8Eb95UVWR3AEecxI0e PbjLf0xOos2g7hKPZaARYrzh4HGPdv7n+90WqrU6DvrHuMjQznZlX+7dtx+YQY4AyL n4oF707CdmaEg== From: Namhyung Kim To: Peter Zijlstra , Ingo Molnar Cc: Kan Liang , Mark Rutland , Alexander Shishkin , Arnaldo Carvalho de Melo , LKML , Stephane Eranian , Ravi Bangoria , Sandipan Das , Ananth Narayan Subject: [PATCH v4 5/5] perf/x86: Relax privilege filter restriction on AMD IBS Date: Tue, 22 Oct 2024 17:09:28 -0700 Message-ID: <20241023000928.957077-6-namhyung@kernel.org> X-Mailer: git-send-email 2.47.0.105.g07ac214952-goog In-Reply-To: <20241023000928.957077-1-namhyung@kernel.org> References: <20241023000928.957077-1-namhyung@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While IBS is available for per-thread profiling, still regular users cannot open an event due to the default paranoid setting (2) which doesn't allow unprivileged users to get kernel samples. That means it needs to set exclude_kernel bit in the attribute but IBS driver would reject it since it has PERF_PMU_CAP_NO_EXCLUDE. This is not what we want and I've been getting requests to fix this issue. This should be done in the hardware, but until we get the HW fix we may allow exclude_{kernel,user,hv} in the attribute and silently drop the samples in the PMU IRQ handler. It won't guarantee the sampling frequency or even it'd miss some with fixed period too. Not ideal, but that'd still be helpful to regular users. To minimize the confusion, let's add 'swfilt' bit to attr.config2 which is exposed in the sysfs format directory so that users can figure out if the kernel support the privilege filters by software. $ perf record -e ibs_op/swfilt=3D1/u true This uses perf_exclude_event() which checks regs->cs. But it should be fine because set_linear_ip() also updates the CS according to the RIP provided by IBS. Cc: Ravi Bangoria Cc: Ananth Narayan Cc: Sandipan Das Cc: Stephane Eranian Signed-off-by: Namhyung Kim --- arch/x86/events/amd/ibs.c | 59 +++++++++++++++++++++++++++------------ 1 file changed, 41 insertions(+), 18 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index e91970b01d6243e4..d89622880a9fbbb9 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -31,6 +31,8 @@ static u32 ibs_caps; #define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT) #define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT =20 +/* attr.config2 */ +#define IBS_SW_FILTER_MASK 1 =20 /* * IBS states: @@ -290,6 +292,16 @@ static int perf_ibs_init(struct perf_event *event) if (has_branch_stack(event)) return -EOPNOTSUPP; =20 + /* handle exclude_{user,kernel} in the IRQ handler */ + if (event->attr.exclude_host || event->attr.exclude_guest || + event->attr.exclude_idle) + return -EINVAL; + + if (!(event->attr.config2 & IBS_SW_FILTER_MASK) && + (event->attr.exclude_kernel || event->attr.exclude_user || + event->attr.exclude_hv)) + return -EINVAL; + ret =3D validate_group(event); if (ret) return ret; @@ -550,24 +562,14 @@ static struct attribute *attrs_empty[] =3D { NULL, }; =20 -static struct attribute_group empty_format_group =3D { - .name =3D "format", - .attrs =3D attrs_empty, -}; - static struct attribute_group empty_caps_group =3D { .name =3D "caps", .attrs =3D attrs_empty, }; =20 -static const struct attribute_group *empty_attr_groups[] =3D { - &empty_format_group, - &empty_caps_group, - NULL, -}; - PMU_FORMAT_ATTR(rand_en, "config:57"); PMU_FORMAT_ATTR(cnt_ctl, "config:19"); +PMU_FORMAT_ATTR(swfilt, "config2:0"); PMU_EVENT_ATTR_STRING(l3missonly, fetch_l3missonly, "config:59"); PMU_EVENT_ATTR_STRING(l3missonly, op_l3missonly, "config:16"); PMU_EVENT_ATTR_STRING(zen4_ibs_extensions, zen4_ibs_extensions, "1"); @@ -578,8 +580,9 @@ zen4_ibs_extensions_is_visible(struct kobject *kobj, st= ruct attribute *attr, int return ibs_caps & IBS_CAPS_ZEN4 ? attr->mode : 0; } =20 -static struct attribute *rand_en_attrs[] =3D { +static struct attribute *fetch_attrs[] =3D { &format_attr_rand_en.attr, + &format_attr_swfilt.attr, NULL, }; =20 @@ -593,9 +596,9 @@ static struct attribute *zen4_ibs_extensions_attrs[] = =3D { NULL, }; =20 -static struct attribute_group group_rand_en =3D { +static struct attribute_group group_fetch_formats =3D { .name =3D "format", - .attrs =3D rand_en_attrs, + .attrs =3D fetch_attrs, }; =20 static struct attribute_group group_fetch_l3missonly =3D { @@ -611,7 +614,7 @@ static struct attribute_group group_zen4_ibs_extensions= =3D { }; =20 static const struct attribute_group *fetch_attr_groups[] =3D { - &group_rand_en, + &group_fetch_formats, &empty_caps_group, NULL, }; @@ -628,6 +631,11 @@ cnt_ctl_is_visible(struct kobject *kobj, struct attrib= ute *attr, int i) return ibs_caps & IBS_CAPS_OPCNT ? attr->mode : 0; } =20 +static struct attribute *op_attrs[] =3D { + &format_attr_swfilt.attr, + NULL, +}; + static struct attribute *cnt_ctl_attrs[] =3D { &format_attr_cnt_ctl.attr, NULL, @@ -638,6 +646,11 @@ static struct attribute *op_l3missonly_attrs[] =3D { NULL, }; =20 +static struct attribute_group group_op_formats =3D { + .name =3D "format", + .attrs =3D op_attrs, +}; + static struct attribute_group group_cnt_ctl =3D { .name =3D "format", .attrs =3D cnt_ctl_attrs, @@ -650,6 +663,12 @@ static struct attribute_group group_op_l3missonly =3D { .is_visible =3D zen4_ibs_extensions_is_visible, }; =20 +static const struct attribute_group *op_attr_groups[] =3D { + &group_op_formats, + &empty_caps_group, + NULL, +}; + static const struct attribute_group *op_attr_update[] =3D { &group_cnt_ctl, &group_op_l3missonly, @@ -667,7 +686,6 @@ static struct perf_ibs perf_ibs_fetch =3D { .start =3D perf_ibs_start, .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, - .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSFETCHCTL, .config_mask =3D IBS_FETCH_CONFIG_MASK, @@ -691,7 +709,6 @@ static struct perf_ibs perf_ibs_op =3D { .start =3D perf_ibs_start, .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, - .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSOPCTL, .config_mask =3D IBS_OP_CONFIG_MASK, @@ -1111,6 +1128,12 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf= _ibs, struct pt_regs *iregs) regs.flags |=3D PERF_EFLAGS_EXACT; } =20 + if ((event->attr.config2 & IBS_SW_FILTER_MASK) && + perf_exclude_event(event, ®s)) { + throttle =3D perf_event_account_interrupt(event); + goto out; + } + if (event->attr.sample_type & PERF_SAMPLE_RAW) { raw =3D (struct perf_raw_record){ .frag =3D { @@ -1228,7 +1251,7 @@ static __init int perf_ibs_op_init(void) if (ibs_caps & IBS_CAPS_ZEN4) perf_ibs_op.config_mask |=3D IBS_OP_L3MISSONLY; =20 - perf_ibs_op.pmu.attr_groups =3D empty_attr_groups; + perf_ibs_op.pmu.attr_groups =3D op_attr_groups; perf_ibs_op.pmu.attr_update =3D op_attr_update; =20 return perf_ibs_pmu_init(&perf_ibs_op, "ibs_op"); --=20 2.47.0.105.g07ac214952-goog