From nobody Tue Nov 26 00:49:34 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CBF4154BFB; Wed, 23 Oct 2024 06:57:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729666675; cv=none; b=kNQopYGs478eMyjkNNVHhaIxTOPt0eDERP8MjOx/tflMNLrKAVo/XYEm4mpx1AE5TqbaIvnXzrN9fm2b+vwoOQDxYqVgtZR/ZPLnUsLlBg3fm9nJ5etmlfyiVMP4blxPYOUHWiFpWiW+hz7uy0e/Zz+eoqwxwhbevb/UCcvfTnk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729666675; c=relaxed/simple; bh=KZbHZuHPzVVOw5/YUibS3MIHFAN3oLZJ7JtB4e4b3KM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=BjHGCPCW+v6jO7OA9m6gsh7UKaO6V2x7AC44bwve9Ni/Mf7fdeLnyznSIZ+8HT/FxuEgavSiCAbxn3KbfacuQj7i2juprCi/uXdTj5BdtP3z8uuAagt1X1egMsfPxyH/J3DoCyXHcflJdd4o5odR/JLyg5dGfDfzCIQXkiRjm0g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=SpgrGPUV; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="SpgrGPUV" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vfMt056462; Wed, 23 Oct 2024 01:57:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729666661; bh=ndyJdRvJJnqCdNLgocPXEINIW2HGhAp3Lnlb9t5J8js=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=SpgrGPUV81Nf2WL5y6CfkBa02mkw6n6ivqBQ44Xd6IzXxurM9KoILood4qPUElao7 xYXH7fFhNbkUuTzEMzBD+7d6P38p1p7LVmh4SQrUBbf6pSBDOiJDT4GhpQrurdyvyb jhXLyrq17e7VMLN/YOLY6CpChHQOnIAG/Ixx3CLg= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49N6vfse055595 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 23 Oct 2024 01:57:41 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 23 Oct 2024 01:57:41 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 23 Oct 2024 01:57:41 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vWUO129058; Wed, 23 Oct 2024 01:57:37 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:15 +0530 Subject: [PATCH v5 01/12] arm64: dts: ti: k3-j784s4-j742s2-mcu-wakeup: Move bootph from mcu_timer1 to mcu_timer0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-1-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=1093; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=KZbHZuHPzVVOw5/YUibS3MIHFAN3oLZJ7JtB4e4b3KM=; b=8VnuLOoOXQlehXw9bV+vBEl161PuwhiheueLlTeggB0eRFDJtvw+HewfR2F7vM7WCK5NHeqSx Zf4ZPuGuiOxC5mwCYsUgmzpgtZJ/jEPfd8uhpzSpuPwOwJLQ9V6mbWF X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Bootloader are using mcu_timer0 instead of mcu_timer1. Adds bootph to mcu_timer0 instead of mcu_timer1. Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi= b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index cba8d0e64f2e..9899da73a905 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -172,13 +172,13 @@ mcu_timer0: timer@40400000 { assigned-clocks =3D <&k3_clks 35 2>; assigned-clock-parents =3D <&k3_clks 35 3>; power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-all; ti,timer-pwm; /* Non-MPU Firmware usage */ status =3D "reserved"; }; =20 mcu_timer1: timer@40410000 { - bootph-all; compatible =3D "ti,am654-timer"; reg =3D <0x00 0x40410000 0x00 0x400>; interrupts =3D ; --=20 2.46.0 From nobody Tue Nov 26 00:49:34 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66BC215530B; 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Wed, 23 Oct 2024 01:57:45 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 23 Oct 2024 01:57:45 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 23 Oct 2024 01:57:45 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vWUP129058; Wed, 23 Oct 2024 01:57:41 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:16 +0530 Subject: [PATCH v5 02/12] arm64: dts: ti: k3-j784s4-j742s2-mcu-wakeup: Remove parent nodes bootph-* Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-2-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=1466; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=TWueD0JQPwhx4GLWqtuVNGZP+TyqKya0NYgWWgv5uEo=; b=MvoJOBYMw3QCS3GhxQBsc5yC/tGDJAyrCFFrNRnSQ/hGoACep+R+dWy9e+zuSAfsWiCMCMnBq wQk/th6tpM0BQsDge1xH/8o5YSDGxoWz0FAvxMQaG9G5puAm/kPRaVG X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adding bootph properties on leaf nodes imply that they are applicable to the parent nodes as well. Bootloaders can derive the parent nodes when bootph is available in the leaf nodes. Remove the bootph-* properties from parent nodes as they are redundant. Signed-off-by: Manorit Chawdhry Reviewed-by: Aniket Limaye --- Notes: It wasn't existing previously in U-boot but the following patch fixes i= t [0] =20 [0]: https://lore.kernel.org/u-boot/20231217163627.2339802-10-sjg@chrom= ium.org/ arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi= b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index 9899da73a905..46bc2a3e4aea 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -7,7 +7,6 @@ =20 &cbass_mcu_wakeup { sms: system-controller@44083000 { - bootph-all; compatible =3D "ti,k2g-sci"; ti,host-id =3D <12>; =20 @@ -39,7 +38,6 @@ k3_reset: reset-controller { }; =20 wkup_conf: bus@43000000 { - bootph-all; compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; @@ -458,7 +456,6 @@ mcu_spi2: spi@40320000 { }; =20 mcu_navss: bus@28380000 { - bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; --=20 2.46.0 From nobody Tue Nov 26 00:49:34 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08A4414F9EE; Wed, 23 Oct 2024 06:57:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729666676; cv=none; b=nd97iyZoQ4fDnVANEMv9wWJbLzwy+bytgh/qMfzASfQE3aLCU14SFD1eBAx2RjchxXjYMQc6mnLEnO4N5ABOsW0DJRFDai/73IiiAuPg13tl5i+Dot2fdcAGtCrWUjG1mwukGVETueIIaNcfGC7On4JMjw0jxwVytVuqmlnoGJQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729666676; c=relaxed/simple; bh=/Coo0U9uL2C7A0CVAS1yhyVpTodVMH6Z95XOj8p/pP4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; 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Wed, 23 Oct 2024 01:57:45 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:17 +0530 Subject: [PATCH v5 03/12] arm64: dts: ti: k3-j784s4: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-3-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=1672; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=/Coo0U9uL2C7A0CVAS1yhyVpTodVMH6Z95XOj8p/pP4=; b=jetovDRRJ/ChlmxUdczGBNJYapvUmAXMPLIugmrq08j1vMZj7aNeSKuYWdd7QBkCUAUujS1JT ySoeYIkz18YBeIsTUY+aNC1k9AwqRiH/iNp8BRs0kpcuk99wFHW/4RF X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea The following nodes are being used in the bootloaders. Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi= b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index 46bc2a3e4aea..9638130caece 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -57,6 +57,8 @@ secure_proxy_sa3: mailbox@43600000 { reg =3D <0x00 0x43600000 0x00 0x10000>, <0x00 0x44880000 0x00 0x20000>, <0x00 0x44860000 0x00 0x20000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -512,6 +514,8 @@ secure_proxy_mcu: mailbox@2a480000 { reg =3D <0x00 0x2a480000 0x00 0x80000>, <0x00 0x2a380000 0x00 0x80000>, <0x00 0x2a400000 0x00 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -629,6 +633,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x42050000 0x00 0x350>; power-domains =3D <&k3_pds 243 TI_SCI_PD_SHARED>; #thermal-sensor-cells =3D <1>; + bootph-pre-ram; }; =20 tscadc0: tscadc@40200000 { --=20 2.46.0 From nobody Tue Nov 26 00:49:34 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BEEE156644; Wed, 23 Oct 2024 06:57:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729666681; cv=none; b=deHkSyiRTl21ZlvEV9L99LGzr/RPRVgh0PiCmQFfvNeymSXyaDbJv+OnIivOTF1QqTTB/b3a7ORSnZvzgEoPxnWzLR4wU2kEJBlgw9fNyZQ6nqkJY0f6nPFK1lB1xAUM/WqWTgdNsOgWKhInviBETJuEatqq8PJbSbrF4C8pVU8= ARC-Message-Signature: i=1; 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Wed, 23 Oct 2024 01:57:53 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vWUR129058; Wed, 23 Oct 2024 01:57:50 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:18 +0530 Subject: [PATCH v5 04/12] arm64: dts: ti: k3-j721s2: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-4-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=4018; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=SD0t/sB4jMcLlaeRbo582FoNZeHhndtyvenkgionDlM=; b=CwFi3pQ98wLrQyFXukPwk5HZ9zt0+bKKLDVOo+oWjl0gyvSIlQuFbIo15meX/URo/h12xgAD8 hxOGsCoQZ0PAJhztft7yFwIGYDVGfiUp3B14aFLXNmpeDhbGYzYbZyA X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - System controller nodes that allow controlling power domain, clocks, etc. - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - mcu_ringacc/mcu_udmap for DMA to SMS - chipid for detection soc information. - mcu_timer0 for bootloader tick-timer. - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Reviewed-by: Andrew Davis Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v3 ( Andrew ) arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 9ed6949b40e9..9889144d665a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -816,6 +816,7 @@ secure_proxy_main: mailbox@32c00000 { <0x00 0x32800000 0x00 0x100000>; interrupt-names =3D "rx_011"; interrupts =3D ; + bootph-all; }; =20 hwspinlock: spinlock@30e00000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 9d96b19d0e7c..c36888c45531 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -21,16 +21,19 @@ sms: system-controller@44083000 { k3_pds: power-controller { compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; + bootph-all; }; =20 k3_clks: clock-controller { compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; + bootph-all; }; =20 k3_reset: reset-controller { compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; + bootph-all; }; }; =20 @@ -43,6 +46,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible =3D "ti,am654-chipid"; reg =3D <0x14 0x4>; + bootph-all; }; }; =20 @@ -53,6 +57,8 @@ secure_proxy_sa3: mailbox@43600000 { reg =3D <0x00 0x43600000 0x00 0x10000>, <0x00 0x44880000 0x00 0x20000>, <0x00 0x44860000 0x00 0x20000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -167,6 +173,7 @@ mcu_timer0: timer@40400000 { assigned-clocks =3D <&k3_clks 35 1>; assigned-clock-parents =3D <&k3_clks 35 2>; power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; /* Non-MPU Firmware usage */ status =3D "reserved"; @@ -361,6 +368,7 @@ wkup_i2c0: i2c@42120000 { clocks =3D <&k3_clks 223 1>; clock-names =3D "fck"; power-domains =3D <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + bootph-all; status =3D "disabled"; }; =20 @@ -469,6 +477,7 @@ mcu_ringacc: ringacc@2b800000 { <0x0 0x2a500000 0x0 0x40000>, <0x0 0x28440000 0x0 0x40000>; reg-names =3D "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings =3D <286>; ti,sci-rm-range-gp-rings =3D <0x1>; ti,sci =3D <&sms>; @@ -488,6 +497,7 @@ mcu_udmap: dma-controller@285c0000 { "tchan", "rchan", "rflow"; msi-parent =3D <&main_udmass_inta>; #dma-cells =3D <1>; + bootph-all; =20 ti,sci =3D <&sms>; ti,sci-dev-id =3D <273>; @@ -507,6 +517,8 @@ secure_proxy_mcu: mailbox@2a480000 { reg =3D <0x00 0x2a480000 0x00 0x80000>, <0x00 0x2a380000 0x00 0x80000>, <0x00 0x2a400000 0x00 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -667,6 +679,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x42050000 0x0 0x350>; power-domains =3D <&k3_pds 180 TI_SCI_PD_SHARED>; #thermal-sensor-cells =3D <1>; + bootph-pre-ram; }; =20 mcu_r5fss0: r5fss@41000000 { --=20 2.46.0 From nobody Tue Nov 26 00:49:34 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C273C157495; Wed, 23 Oct 2024 06:58:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729666685; cv=none; b=mch9Chq+8TgYTEp7NtJuJzczqjJyt8jynAdrHQ4W4DHoPYJyoYrQiF34qHwy4YN+4MZX4ob9jgm3hORwZ1NzUYcvxbyjSLI+CMhPJ8WVPGMjDKiheiDrnM7oP/3brx5t9z5Gt4wfHy/lewyiidIb32rYJaHViyerzhzFijk++pI= ARC-Message-Signature: i=1; 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Wed, 23 Oct 2024 01:57:58 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vWUS129058; Wed, 23 Oct 2024 01:57:54 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:19 +0530 Subject: [PATCH v5 05/12] arm64: dts: ti: k3-j721e: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-5-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=3940; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=321qdMBvKZl38Iov3lF4qlALZCMva5GifB0mZSEMoBk=; b=TuRNyCzJftCOGZKV17jxQVEU2PUP95806mFPyh8SKMlKteXXRO791zZ7EtlUgj3lL96Hq8KPB /Auzj4qA/O+DJccbdpAcKPTk6/wGT/dFSC2nRQAk+qjrIOneXI/WNH2 X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - System controller nodes that allow controlling power domain, clocks, etc. - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - mcu_ringacc/mcu_udmap for DMA to SMS - chipid for detection soc information. - mcu_timer0 for bootloader tick-timer. - hbmc_mux for enabling Hyperflash support - ESM nodes for enabling ESM support. - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Signed-off-by: Manorit Chawdhry Reviewed-by: Neha Malcom Francis --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 0da785be80ff..af3d730154ac 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -226,6 +226,7 @@ secure_proxy_main: mailbox@32c00000 { <0x00 0x32800000 0x00 0x100000>; interrupt-names =3D "rx_011"; interrupts =3D ; + bootph-all; }; =20 smmu0: iommu@36600000 { @@ -2853,6 +2854,7 @@ main_spi7: spi@2170000 { main_esm: esm@700000 { compatible =3D "ti,j721e-esm"; reg =3D <0x0 0x700000 0x0 0x1000>; + bootph-pre-ram; ti,esm-pins =3D <344>, <345>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 3731ffb4a5c9..cf5fb1160ada 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 { k3_pds: power-controller { compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; + bootph-all; }; =20 k3_clks: clock-controller { compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; + bootph-all; }; =20 k3_reset: reset-controller { compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; + bootph-all; }; }; =20 @@ -61,6 +64,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible =3D "ti,am654-chipid"; reg =3D <0x14 0x4>; + bootph-all; }; }; =20 @@ -112,6 +116,7 @@ mcu_timer0: timer@40400000 { assigned-clocks =3D <&k3_clks 35 1>; assigned-clock-parents =3D <&k3_clks 35 2>; power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; /* Non-MPU Firmware usage */ status =3D "reserved"; @@ -362,6 +367,7 @@ hbmc_mux: mux-controller@47000004 { reg =3D <0x00 0x47000004 0x00 0x4>; #mux-control-cells =3D <1>; mux-reg-masks =3D <0x0 0x2>; /* HBMC select */ + bootph-all; }; =20 hbmc: hyperbus@47034000 { @@ -470,6 +476,7 @@ mcu_ringacc: ringacc@2b800000 { <0x0 0x2a500000 0x0 0x40000>, <0x0 0x28440000 0x0 0x40000>; reg-names =3D "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings =3D <286>; ti,sci-rm-range-gp-rings =3D <0x1>; /* GP ring range */ ti,sci =3D <&dmsc>; @@ -489,6 +496,7 @@ mcu_udmap: dma-controller@285c0000 { "tchan", "rchan", "rflow"; msi-parent =3D <&main_udmass_inta>; #dma-cells =3D <1>; + bootph-all; =20 ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <236>; @@ -509,6 +517,7 @@ secure_proxy_mcu: mailbox@2a480000 { reg =3D <0x0 0x2a480000 0x0 0x80000>, <0x0 0x2a380000 0x0 0x80000>, <0x0 0x2a400000 0x0 0x80000>; + bootph-pre-ram; /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -687,6 +696,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x43000300 0x00 0x10>; power-domains =3D <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells =3D <1>; + bootph-pre-ram; }; =20 mcu_esm: esm@40800000 { --=20 2.46.0 From nobody Tue Nov 26 00:49:34 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F117F15853E; Wed, 23 Oct 2024 06:58:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729666691; cv=none; b=InzK2OX8lj+uZ1BedcVaSEn9DGNxlk6zwZSY5rDOGhnrNOxHlVsRnirKqTp4tpbctPfzPDApZcnGk9YBlkegOwFEVpaV5tmlHMhoJ+Go5DcA8LFqxDPH9d8hpoeEp6C4r0uUx5M4bjW87Qt0wYZuU5PnJEM+9QHwUuJN1HXCLug= ARC-Message-Signature: i=1; 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Wed, 23 Oct 2024 01:58:04 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vWUT129058; Wed, 23 Oct 2024 01:57:58 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:20 +0530 Subject: [PATCH v5 06/12] arm64: dts: ti: k3-j7200: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-6-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=3883; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=jfhR6o+OxuLC73jUZM+AI82eotkh8amZ1FwWcjhibEw=; b=ckUfhJMXbfghdr2pMEpSCNk6t+A4aaODUFsz50VIZoYC9qcmeruOn0Dejg1jg/pamYagy1p+a n9gtPZli8CaBaZy4jVr9cwoFyA7lRYGOsdWaTJFIk0IVj5ZXRFzD8ZL X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - System controller nodes that allow controlling power domain, clocks, etc. - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - mcu_ringacc/mcu_udmap for DMA to SMS - chipid for detection soc information. - mcu_timer0 for bootloader tick-timer. - hbmc_mux for enabling Hyperflash support - ESM nodes for enabling ESM support. - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Signed-off-by: Manorit Chawdhry Reviewed-by: Aniket Limaye --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 9386bf3ef9f6..ac9c0a939461 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 { <0x00 0x32800000 0x00 0x100000>; interrupt-names =3D "rx_011"; interrupts =3D ; + bootph-all; }; =20 hwspinlock: spinlock@30e00000 { @@ -1527,6 +1528,7 @@ main_r5fss0_core1: r5f@5d00000 { main_esm: esm@700000 { compatible =3D "ti,j721e-esm"; reg =3D <0x0 0x700000 0x0 0x1000>; + bootph-pre-ram; ti,esm-pins =3D <656>, <657>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 5097d192c2b2..7e9ad2301937 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 { k3_pds: power-controller { compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; + bootph-all; }; =20 k3_clks: clock-controller { compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; + bootph-all; }; =20 k3_reset: reset-controller { compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; + bootph-all; }; }; =20 @@ -44,6 +47,7 @@ mcu_timer0: timer@40400000 { assigned-clocks =3D <&k3_clks 35 1>; assigned-clock-parents =3D <&k3_clks 35 2>; power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; }; =20 @@ -191,6 +195,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible =3D "ti,am654-chipid"; reg =3D <0x14 0x4>; + bootph-all; }; }; =20 @@ -344,6 +349,7 @@ mcu_ringacc: ringacc@2b800000 { <0x00 0x28440000 0x00 0x40000>; reg-names =3D "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings =3D <286>; ti,sci-rm-range-gp-rings =3D <0x1>; /* GP ring range */ ti,sci =3D <&dmsc>; @@ -363,6 +369,7 @@ mcu_udmap: dma-controller@285c0000 { "tchan", "rchan", "rflow"; msi-parent =3D <&main_udmass_inta>; #dma-cells =3D <1>; + bootph-all; =20 ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <236>; @@ -383,6 +390,8 @@ secure_proxy_mcu: mailbox@2a480000 { reg =3D <0x0 0x2a480000 0x0 0x80000>, <0x0 0x2a380000 0x0 0x80000>, <0x0 0x2a400000 0x0 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -534,6 +543,7 @@ hbmc_mux: mux-controller@47000004 { reg =3D <0x00 0x47000004 0x00 0x4>; #mux-control-cells =3D <1>; mux-reg-masks =3D <0x0 0x2>; /* HBMC select */ + bootph-all; }; =20 hbmc: hyperbus@47034000 { @@ -652,6 +662,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x42050000 0x00 0x350>; power-domains =3D <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells =3D <1>; + bootph-pre-ram; }; =20 mcu_esm: esm@40800000 { --=20 2.46.0 From nobody Tue Nov 26 00:49:34 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB7961537AC; Wed, 23 Oct 2024 06:58:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729666698; cv=none; b=gUAe3lfjGuaCblR4t8eGo6Rfj8LQyEHkN7hE5FRXFJkU2GL4n+uJMnU7Pqxs3sv+SRaSV4TVPIORqCxjb+TGp3qHZPHA1W3NJbu9DZDXmqQgUHkjQmgZLt7z5kFohMykzOBimkrbzTv/zDYmxqmIPN6eRwGwxJ7P/LQ6QjPi3cc= ARC-Message-Signature: i=1; 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Wed, 23 Oct 2024 01:58:10 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vWUU129058; Wed, 23 Oct 2024 01:58:05 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:21 +0530 Subject: [PATCH v5 07/12] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Remove parent nodes bootph-* Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-7-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=2292; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=fsgEeowNfLZ+AEu0rnrEvO6+4zAPScFF0LW6LOvL5Sc=; b=lL3+BOnSSkmHrG3il7RUQ0d7ieM8eZaDa87FZTMlaqXUbVhznJUhopOtXW0nyidRzJaL+d3dV N40RZz1jBMZB1RYQmLUGua/NwZ6pteOhxq1+gOX8Hzz19fP9mHBK/wk X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adding bootph properties on leaf nodes imply that they are applicable to the parent nodes as well. Bootloaders can derive the parent nodes when bootph is available in the leaf nodes. Remove the bootph-* properties from parent nodes as they are redundant. Signed-off-by: Manorit Chawdhry Reviewed-by: Aniket Limaye --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index 98453171a179..b2e2b9f507a9 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -305,7 +305,6 @@ &wkup_gpio0 { }; =20 &main_pmx0 { - bootph-all; main_cpsw2g_default_pins: main-cpsw2g-default-pins { pinctrl-single,pins =3D < J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ @@ -432,7 +431,6 @@ J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.A= UDIO_EXT_REFCLK1 */ }; =20 &wkup_pmx2 { - bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -548,7 +546,6 @@ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) }; =20 &wkup_pmx0 { - bootph-all; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -568,7 +565,6 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSP= I0_DQS */ }; =20 &wkup_pmx1 { - bootph-all; mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -740,18 +736,15 @@ &ufs_wrapper { }; =20 &fss { - bootph-all; status =3D "okay"; }; =20 &ospi0 { - bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_def= ault>; =20 flash@0 { - bootph-all; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-tx-bus-width =3D <8>; @@ -808,13 +801,11 @@ partition@3fc0000 { }; =20 &ospi1 { - bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; =20 flash@0 { - bootph-all; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-tx-bus-width =3D <1>; --=20 2.46.0 From nobody Tue Nov 26 00:49:34 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F1E915A86A; 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Wed, 23 Oct 2024 01:58:17 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 23 Oct 2024 01:58:16 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 23 Oct 2024 01:58:16 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vWUV129058; Wed, 23 Oct 2024 01:58:11 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:22 +0530 Subject: [PATCH v5 08/12] arm64: dts: ti: k3-j721s2-evm*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-8-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=5042; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=qUvWem0cL99Oxp7SbUsQAAdeviSA7ZzljlX6DsjUkUg=; b=Cf5t3SnQkimaZBJoSXyz07O2RSoBuZ9pXxAvZBGNKQ4ey5/461oq6Q0KuNT9svw3zlXi5/bL5 W4p8znVwPADAyRK1XJBfWxIzSS2IH+DSQTrYTqGjFeuAiJo2R5Dv0ah X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - pmic regulator for enabling AVS Support - main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc0, mmc1, usb0, ospi0, ospi1 for enabling various bootmodes. Reviewed-by: Andrew Davis Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v3 ( Andrew ) arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 3 +++ 2 files changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index c5a0b7cbb14f..e2fc1288ed07 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -138,6 +138,7 @@ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR= 1.UART8_RTSn */ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; + bootph-all; }; =20 main_i2c3_pins_default: main-i2c3-default-pins { @@ -165,6 +166,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; =20 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -177,6 +179,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; + bootph-all; }; =20 main_mcan3_pins_default: main-mcan3-default-pins { @@ -200,6 +203,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; + bootph-all; }; =20 mcu_uart0_pins_default: mcu-uart0-default-pins { @@ -209,6 +213,7 @@ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_G= PIO0_15.MCU_UART0_RTSn */ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0= _RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART= 0_TXD */ >; + bootph-all; }; =20 mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -301,6 +306,7 @@ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSP= I1_D3 */ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ >; + bootph-all; }; }; =20 @@ -316,12 +322,14 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart8 { @@ -330,6 +338,7 @@ &main_uart8 { pinctrl-0 =3D <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains =3D <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; }; =20 &main_i2c0 { @@ -383,6 +392,7 @@ &main_sdhci0 { /* eMMC */ status =3D "okay"; non-removable; + bootph-all; ti,driver-strength-ohm =3D <50>; disable-wp; }; @@ -395,6 +405,7 @@ &main_sdhci1 { disable-wp; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv>; + bootph-all; }; =20 &mcu_cpsw { @@ -444,6 +455,7 @@ &usbss0 { status =3D "okay"; pinctrl-0 =3D <&main_usbss0_pins_default>; pinctrl-names =3D "default"; + bootph-all; ti,vbus-divider; ti,usb2-only; }; @@ -451,6 +463,7 @@ &usbss0 { &usb0 { dr_mode =3D "otg"; maximum-speed =3D "high-speed"; + bootph-all; }; =20 &ospi1 { @@ -464,6 +477,7 @@ flash@0 { spi-tx-bus-width =3D <1>; spi-rx-bus-width =3D <4>; spi-max-frequency =3D <40000000>; + bootph-all; cdns,tshsl-ns =3D <60>; cdns,tsd2d-ns =3D <60>; cdns,tchsh-ns =3D <60>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index 89252e4a5f1b..b3a0385ed3d8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -170,6 +170,7 @@ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSP= I0_D7 */ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ >; + bootph-all; }; }; =20 @@ -188,6 +189,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ >; + bootph-pre-ram; }; }; =20 @@ -440,6 +442,7 @@ flash@0 { spi-tx-bus-width =3D <8>; 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Wed, 23 Oct 2024 01:58:17 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:23 +0530 Subject: [PATCH v5 09/12] arm64: dts: ti: k3-am68-sk*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-9-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=3843; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=Q6AEzA9B//pSElsKicBAhYC55/J10Sfu9iiUgEPtJsE=; b=hOkNXIYTCsaHHCajd1Kc7vVAZx0TG5fNc2yYXpWx35ZehGwzKonrSvxGSdC/ITC1pTh9lCNIP 9dVfHCGMKIQCSUfELDs6S4G+4KiTjCvfj8YTtSKTA16Gyvbv5K6qSD+ X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc1, ospi0 for enabling various bootmodes. - eeprom for board detection Reviewed-by: Udit Kumar Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v4 ( Udit ) arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 5 +++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index d5ceab79536c..11522b36e0ce 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -184,6 +184,7 @@ main_uart8_pins_default: main-uart8-default-pins { J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; + bootph-all; }; =20 main_i2c0_pins_default: main-i2c0-default-pins { @@ -211,6 +212,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; =20 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -313,6 +315,7 @@ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_G= PIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; + bootph-all; }; =20 mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -372,6 +375,7 @@ mcu_uart0_pins_default: mcu-uart0-default-pins { J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0= _RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART= 0_TXD */ >; + bootph-all; }; =20 mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { @@ -413,6 +417,7 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &wkup_i2c0 { @@ -495,6 +500,7 @@ &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart8 { @@ -503,6 +509,7 @@ &main_uart8 { pinctrl-0 =3D <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains =3D <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; }; =20 &main_i2c0 { @@ -597,6 +604,7 @@ &main_sdhci1 { disable-wp; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv>; + bootph-all; }; =20 &mcu_cpsw { diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/d= ts/ti/k3-am68-sk-som.dtsi index 5bc0d2fb4b8f..4ca2d4e2fb9b 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -156,6 +156,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ >; + bootph-all; }; }; =20 @@ -169,6 +170,7 @@ eeprom@51 { /* AT24C512C-MAHM-T */ compatible =3D "atmel,24c512"; reg =3D <0x51>; + bootph-all; }; }; =20 @@ -190,7 +192,6 @@ flash@0 { cdns,read-delay =3D <4>; =20 partitions { - bootph-all; compatible =3D "fixed-partitions"; #address-cells =3D <1>; #size-cells =3D <1>; @@ -226,9 +227,9 @@ partition@800000 { }; =20 partition@3fc0000 { - bootph-pre-ram; label =3D "ospi.phypattern"; reg =3D <0x3fc0000 0x40000>; + bootph-all; }; }; }; --=20 2.46.0 From nobody Tue Nov 26 00:49:34 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A3321662F1; Wed, 23 Oct 2024 06:58:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729666714; cv=none; b=E5fxfB41Sch5eUYMl7XNzgwxNC6uWZCWGN6D+O5Y7Yopf7Xk4L+z2BJMSkG2FKQqx/AOuIDthqnR4NMEK3PNdtJhPkzKHy02DRpv2axn+VKqX0uaj22pO/9m4SpP8XRF7r4xKXA6KwjJJ3lwvEELBvahXI4I2KAxUibqrCuWkDk= ARC-Message-Signature: i=1; a=rsa-sha256; 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Wed, 23 Oct 2024 01:58:27 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vWUX129058; Wed, 23 Oct 2024 01:58:23 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:24 +0530 Subject: [PATCH v5 10/12] arm64: dts: ti: k3-j721e-evm*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-10-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=5924; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=tew9JNhPhAeqYeQUqkgNOxX+WWvWtySM+AIf07Mqu8E=; b=KbddTU8WxVXdqWJjQqVg1UkdagYdm+b9WMBAzUawt8hL1MrNe014ZWrbxKv4+N0pKMlkDRciw S4P6I00gMprBOqrfazJS3Mg2v0z7GO+wvQIOuLfS6RY1UBA+wVd0E8c X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc0, mmc1, usb0, ospi0, ospi1, hbmc for enabling various bootmodes. Signed-off-by: Manorit Chawdhry Reviewed-by: Neha Malcom Francis --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 5 +++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 8230d53cd696..4c1e02a4e7a2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -193,6 +193,7 @@ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UAR= T0_RTSn */ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; + bootph-all; }; =20 main_uart1_pins_default: main-uart1-default-pins { @@ -234,6 +235,7 @@ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ >; + bootph-all; }; =20 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { @@ -247,6 +249,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; + bootph-all; }; =20 main_usbss1_pins_default: main-usbss1-default-pins { @@ -342,6 +345,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ >; + bootph-all; }; =20 mcu_uart0_pins_default: mcu-uart0-default-pins { @@ -351,6 +355,7 @@ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPI= O0_15.MCU_UART0_RTSn */ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_R= XD */ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_= TXD */ >; + bootph-all; }; =20 sw11_button_pins_default: sw11-button-default-pins { @@ -370,6 +375,7 @@ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1= _D3 */ J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ >; + bootph-all; }; =20 mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -435,12 +441,14 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart0 { @@ -449,6 +457,7 @@ &main_uart0 { pinctrl-0 =3D <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains =3D <&k3_pds 146 TI_SCI_PD_SHARED>; + bootph-all; }; =20 &main_uart1 { @@ -487,6 +496,7 @@ &main_sdhci0 { /* eMMC */ status =3D "okay"; non-removable; + bootph-all; ti,driver-strength-ohm =3D <50>; disable-wp; }; @@ -498,12 +508,14 @@ &main_sdhci1 { vqmmc-supply =3D <&vdd_sd_dv_alt>; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_pins_default>; + bootph-all; ti,driver-strength-ohm =3D <50>; disable-wp; }; =20 &usb_serdes_mux { idle-states =3D <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ + bootph-all; }; =20 &serdes_ln_ctrl { @@ -513,6 +525,7 @@ &serdes_ln_ctrl { , , , , , ; + bootph-all; }; =20 &serdes_wiz3 { @@ -533,6 +546,7 @@ serdes3_usb_link: phy@0 { &usbss0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; }; =20 @@ -541,6 +555,7 @@ &usb0 { maximum-speed =3D "super-speed"; phys =3D <&serdes3_usb_link>; phy-names =3D "cdns3,usb3-phy"; + bootph-all; }; =20 &usbss1 { @@ -613,6 +628,7 @@ partition@800000 { partition@3fe0000 { label =3D "qspi.phypattern"; reg =3D <0x3fe0000 0x20000>; + bootph-all; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j721e-som-p0.dtsi index cef47c67493f..0722f6361cc8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -151,6 +151,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; + bootph-all; }; =20 pmic_irq_pins_default: pmic-irq-default-pins { @@ -173,6 +174,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6= */ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; + bootph-all; }; =20 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { @@ -192,6 +194,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_= DQ5 */ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ >; + bootph-all; }; }; =20 @@ -422,6 +425,7 @@ partition@800000 { partition@3fe0000 { label =3D "ospi.phypattern"; reg =3D <0x3fe0000 0x20000>; + bootph-all; }; }; }; @@ -440,6 +444,7 @@ &hbmc { flash@0,0 { compatible =3D "cypress,hyperflash", "cfi-flash"; reg =3D <0x00 0x00 0x4000000>; + bootph-all; =20 partitions { compatible =3D "fixed-partitions"; --=20 2.46.0 From nobody Tue Nov 26 00:49:34 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41F7C14AD3F; Wed, 23 Oct 2024 06:58:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 23 Oct 2024 01:58:33 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 23 Oct 2024 01:58:33 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vWUY129058; Wed, 23 Oct 2024 01:58:28 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:25 +0530 Subject: [PATCH v5 11/12] arm64: dts: ti: k3-j721e-sk*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-11-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=4723; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=KVKnuqjy5Rm9jG5FobTuyuDNsw+FIlWGSMffuz21vD8=; b=HC/oPyjq16BP4OKFTfLyh9RAfPybvKJUmx43G0lYm5zu4qbTdb8AFZAyxzVQAs0ItHudUgrgB 3I8FufcOXUJAgaLkNeUG+g20xRVk4dnzvGWm6wbM5heKBhOB3V5A67Z X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc1, usb0, usb1, ospi0 for enabling various bootmodes. Signed-off-by: Manorit Chawdhry Reviewed-by: Neha Malcom Francis --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 6285e8d94dde..69b3d1ed8a21 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -346,6 +346,7 @@ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ >; + bootph-all; }; =20 main_uart0_pins_default: main-uart0-default-pins { @@ -355,6 +356,7 @@ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; + bootph-all; }; =20 main_uart1_pins_default: main-uart1-default-pins { @@ -390,12 +392,14 @@ main_usbss0_pins_default: main-usbss0-default-pins { J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; + bootph-all; }; =20 main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins =3D < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; + bootph-all; }; =20 main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { @@ -594,6 +598,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0= _D6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ >; + bootph-all; }; =20 vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { @@ -622,6 +627,7 @@ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_= SDA.MCU_UART0_RTSn */ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_R= XD */ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_T= XD */ >; + bootph-all; }; =20 wkup_i2c0_pins_default: wkup-i2c0-default-pins { @@ -629,6 +635,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; + bootph-all; }; =20 mcu_mcan0_pins_default: mcu-mcan0-default-pins { @@ -657,6 +664,7 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &wkup_i2c0 { @@ -821,6 +829,7 @@ &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart0 { @@ -829,6 +838,7 @@ &main_uart0 { pinctrl-0 =3D <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains =3D <&k3_pds 146 TI_SCI_PD_SHARED>; + bootph-all; }; =20 &main_uart1 { @@ -844,6 +854,7 @@ &main_sdhci1 { vqmmc-supply =3D <&vdd_sd_dv_alt>; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_pins_default>; + bootph-all; ti,driver-strength-ohm =3D <50>; disable-wp; }; @@ -908,6 +919,7 @@ partition@800000 { partition@3fc0000 { label =3D "ospi.phypattern"; reg =3D <0x3fc0000 0x40000>; + bootph-all; }; }; }; @@ -1003,6 +1015,7 @@ &wkup_gpio0 { =20 &usb_serdes_mux { idle-states =3D <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ + bootph-all; }; =20 &serdes_ln_ctrl { @@ -1012,6 +1025,7 @@ &serdes_ln_ctrl { , , , , , ; + bootph-all; }; =20 &serdes_wiz3 { @@ -1050,6 +1064,7 @@ &mhdp { &usbss0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; }; =20 @@ -1058,6 +1073,7 @@ &usb0 { maximum-speed =3D "super-speed"; phys =3D <&serdes3_usb_link>; phy-names =3D "cdns3,usb3-phy"; + bootph-all; }; =20 &serdes2 { @@ -1073,6 +1089,7 @@ serdes2_usb_link: phy@1 { &usbss1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_usbss1_pins_default>; + bootph-all; ti,vbus-divider; }; =20 @@ -1081,6 +1098,7 @@ &usb1 { maximum-speed =3D "super-speed"; phys =3D <&serdes2_usb_link>; phy-names =3D "cdns3,usb3-phy"; + bootph-all; }; =20 &mcu_cpsw { --=20 2.46.0 From nobody Tue Nov 26 00:49:34 2024 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A682839ACC; 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Wed, 23 Oct 2024 01:58:39 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 23 Oct 2024 01:58:38 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 23 Oct 2024 01:58:38 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6vWUZ129058; Wed, 23 Oct 2024 01:58:33 -0500 From: Manorit Chawdhry Date: Wed, 23 Oct 2024 12:27:26 +0530 Subject: [PATCH v5 12/12] arm64: dts: ti: k3-j7200-evm*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241023-b4-upstream-bootph-all-v5-12-a974d06370ab@ti.com> References: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> In-Reply-To: <20241023-b4-upstream-bootph-all-v5-0-a974d06370ab@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729666652; l=5151; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=kGOoXzqHWopCxpKtguf76g6UKzPxXde3feM93X+DlEA=; b=/j5HzF/0nCaugkxmilZyxakpRdL+nC1Jz/V+nTvaZsmYbmc/h2SPw8yoPoU1ygXMFgLbFgoh1 bAIyYc6R4exC9rFY91SuBOLdLNDPvpYBw60NH3SYtxONyHvy0cAAosZ X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - pmic regulator for enabling AVS Support - main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc0, mmc1, usb0, ospi0, ospi1, hbmc for enabling various bootmodes. Signed-off-by: Manorit Chawdhry Reviewed-by: Aniket Limaye --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 13 +++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 6593c5da82c0..d03690b8d652 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -129,6 +129,7 @@ J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART= 0_RTSn */ J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ >; + bootph-all; }; =20 wkup_uart0_pins_default: wkup-uart0-default-pins { @@ -136,6 +137,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ >; + bootph-all; }; =20 mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -204,6 +206,7 @@ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ >; + bootph-all; }; =20 main_uart1_pins_default: main-uart1-default-pins { @@ -238,6 +241,7 @@ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; =20 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -259,6 +263,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins =3D < J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; + bootph-all; }; }; =20 @@ -267,12 +272,14 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart0 { @@ -281,6 +288,7 @@ &main_uart0 { power-domains =3D <&k3_pds 146 TI_SCI_PD_SHARED>; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; + bootph-all; }; =20 &main_uart1 { @@ -379,6 +387,7 @@ &main_sdhci0 { /* eMMC */ status =3D "okay"; non-removable; + bootph-all; ti,driver-strength-ohm =3D <50>; disable-wp; }; @@ -390,6 +399,7 @@ &main_sdhci1 { pinctrl-names =3D "default"; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv>; + bootph-all; ti,driver-strength-ohm =3D <50>; disable-wp; }; @@ -401,11 +411,13 @@ &serdes_ln_ctrl { =20 &usb_serdes_mux { idle-states =3D <1>; /* USB0 to SERDES lane 3 */ + bootph-all; }; =20 &usbss0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; ti,usb2-only; }; @@ -413,6 +425,7 @@ &usbss0 { &usb0 { dr_mode =3D "otg"; maximum-speed =3D "high-speed"; + bootph-all; }; =20 &tscadc0 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j7200-som-p0.dtsi index e78b4622a7d1..291ab9bb414d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_= D5.MCU_HYPERBUS0_DQ5 */ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0= _DQ6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0= _DQ7 */ >; + bootph-all; }; =20 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { @@ -137,6 +138,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6= */ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ >; + bootph-all; }; }; =20 @@ -146,6 +148,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ >; + bootph-all; }; }; =20 @@ -186,6 +189,7 @@ &hbmc { flash@0,0 { compatible =3D "cypress,hyperflash", "cfi-flash"; reg =3D <0x00 0x00 0x4000000>; + bootph-all; =20 partitions { compatible =3D "fixed-partitions"; @@ -347,6 +351,7 @@ bucka1: buck1 { regulator-max-microvolt =3D <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; =20 bucka2: buck2 { @@ -520,6 +525,7 @@ partition@800000 { partition@3fc0000 { label =3D "ospi.phypattern"; reg =3D <0x3fc0000 0x40000>; + bootph-all; }; }; }; --=20 2.46.0