From nobody Mon Nov 25 23:36:29 2024 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6B3A1991A9 for ; Wed, 23 Oct 2024 09:19:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675186; cv=none; b=sto1qlxzUwLgalBqajEFVSJNwKaDVyGUeBoveUbNaR6rC0cEvsRchHzMqM7CHPQ1pXCkTANc9tVEfddQb7Z2ByGL0RA8XKORUx+bQMnABURnAKITxesk+FtOkDG0zvFVgVJ6TqVUn0IFhMXIKcUssiDEZx1mk3cpzpkygdzY7CE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675186; c=relaxed/simple; bh=71SFQ7URbRm1unU+yOo+bsXksMKw0BZgy2kSE2RSd6w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=O7WKlnjLvGcNuXDGSUWLwqgiQXMfLB3bQrhYEcAmWg1500B+Oa+gSG14Gyg2rRmeNLcqh0O4BpBVDsU3lzPlV5vB7sw7m/ZWe+WNcz3TjChamROIb06RgVfyMrjDC678NdrOU6QcZS1sn1heW3z1U2iPXjP6csYR5ylNkcqnfgk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=zM0MFb4H; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="zM0MFb4H" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-37d4c1b1455so4360851f8f.3 for ; Wed, 23 Oct 2024 02:19:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1729675183; x=1730279983; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=920ffWWvUWDGbBU56/ZZKeI4adOcPBv24vNwmVJoAN4=; b=zM0MFb4H9fBppw7eZfX4UAXCqC/xpgVo98XzEV5FeoW6FwqAsgsyNmUulLf+EVxiCc cNnKw/EKIi5bL5gUwScQjQrDiO9Y5lRb2fIcLjm1QK6sDjPSvU2vMprCOFjrzxacKbFx 5opONSyDuuZwm12e2Ut6OF3nPWdX4aoGb7+VsgEzuGbJPslWQu926nr9Us8H1Inf/OPG lNxqmqBgIOmuyGGdlfKmgbbJpiB4w/LE5aEkUdHzOLkdxJrakYl+6AMFoemMpkq4k0MG ArMPm3gkrp7WG/UyjJQABCDsCUHhRU/YVBy1fGc1aoks9jH+HsaPyVTvErn43kAJHNnI eKpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729675183; x=1730279983; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=920ffWWvUWDGbBU56/ZZKeI4adOcPBv24vNwmVJoAN4=; b=S84Xio7pbuAvIcroaONApWJfitK6x7ornhFdeAojHStyiztRx3+Tw1kS3vTZAC4hsx CDXHgJMuhwzRcg9MCXbY79QAorD1jGtNv6YbB2220tKUP/tHJpN6S6ieMFkKWH6OktvO Wwb+NZx6xUwjiRYID/j3MED/hn5qKVQdMlBnWMZkTOh5i0CXn4Ybzb/4v9fvHMtJMoCy d3R7HlA1ZtGOzFQBlCnDFZTDVCFjhPV3fD2R+zZH0QZpluw+aTyx2TW0fUe5fHBSnSLO kLJ9qeUvFlbbygqwnfseVsbedqdtENO1SLvA1WW7LzVdQ8Najk1G8KScDyCAZ3Ifdvqd 1Ptw== X-Forwarded-Encrypted: i=1; AJvYcCUHr8u5AMFtmE///TCZgTivLWCMdvRmytuMB39tN6kpKzkaGmiXkcT6RkvNlVmZcscjF0BAxknKznuBiqw=@vger.kernel.org X-Gm-Message-State: AOJu0YztVoKOLq0E5Wa48sHjUZo/iwsNB8G849+hPK0yCYxwpJM+OykP xsTUqJ19dvL8rnDYqsqrKzC1x0rQ5eJUXTSAjyciHnEZqx3/GPNCT8qNOhrNwNA= X-Google-Smtp-Source: AGHT+IH0jz7mpDLs/+ZuOO4mKfYMLL4LeUUNinNhp/bMdj9LMhJOzXhq9AHgvCKl8rFH7mcBjviykw== X-Received: by 2002:adf:f58e:0:b0:37d:39aa:b9f4 with SMTP id ffacd0b85a97d-37efcf1a775mr1188313f8f.26.1729675182928; Wed, 23 Oct 2024 02:19:42 -0700 (PDT) Received: from [192.168.1.62] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0b94363sm8515796f8f.73.2024.10.23.02.19.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:19:42 -0700 (PDT) From: Julien Stephan Date: Wed, 23 Oct 2024 11:19:33 +0200 Subject: [PATCH v2 1/4] dt-bindings: iio: adc: ad7380: add adaq4370-4 and adaq4380-4 compatible parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241023-ad7380-add-adaq4380-4-support-v2-1-d55faea3bedf@baylibre.com> References: <20241023-ad7380-add-adaq4380-4-support-v2-0-d55faea3bedf@baylibre.com> In-Reply-To: <20241023-ad7380-add-adaq4380-4-support-v2-0-d55faea3bedf@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 adaq4370-4 (2MSPS) and adaq4380-4 (4MSPS) are quad-channel precision data acquisition signal chain =CE=BCModule solutions compatible with the ad738x family, with the following differences: - pin selectable gain in front of each 4 adc - internal reference is 3V derived from refin-supply (5V) - additional supplies To select the gain a new patternProperties is added to describe each channel. It is restricted to adaq devices. Signed-off-by: Julien Stephan --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 121 +++++++++++++++++= ++++ 1 file changed, 121 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index 0065d650882489e21b952bb9fb25f1e3a070ee68..d5eaa2d667eb4310daf0d35e852= 16363c14956da 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -25,6 +25,8 @@ description: | * https://www.analog.com/en/products/ad7386-4.html * https://www.analog.com/en/products/ad7387-4.html * https://www.analog.com/en/products/ad7388-4.html + * https://www.analog.com/en/products/adaq4370-4.html + * https://www.analog.com/en/products/adaq4380-4.html =20 =20 $ref: /schemas/spi/spi-peripheral-props.yaml# @@ -46,6 +48,8 @@ properties: - adi,ad7386-4 - adi,ad7387-4 - adi,ad7388-4 + - adi,adaq4370-4 + - adi,adaq4380-4 =20 reg: maxItems: 1 @@ -70,6 +74,20 @@ properties: refin-supply: description: A 2.5V to 3.3V supply for external reference voltage, for ad7380-4 o= nly. + For adaq devices, a 5V supply voltage. A 3.3V internal reference is + derived from it. Connect to vs-p-supply for normal operation. + + vs-p-supply: + description: + Amplifiers positive supply. + + vs-n-supply: + description: + Amplifiers negative supply. + + ldo-supply: + description: + LDO supply. Connect to vs-p-supply or a 3.6 to 5.5 V supply. =20 aina-supply: description: @@ -97,12 +115,46 @@ properties: specify the ALERT interrupt. maxItems: 1 =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + required: - compatible - reg - vcc-supply - vlogic-supply =20 +patternProperties: + "^channel@([0-3])$": + $ref: adc.yaml + type: object + + properties: + reg: + description: + The channel number. From 0 to 3 corresponding to channels A,B,C,D + items: + minimum: 0 + maximum: 3 + + adi,gain-milli: + description: + The hardware gain applied to the ADC input (in milli units). + If not present, default to 1000 (no actual gain applied). + Refer to the typical connection diagrams section of the datashee= t for + pin wiring. + $ref: /schemas/types.yaml#/definitions/uint16 + enum: [300, 600, 1000, 1600] + default: 1000 + + required: + - reg + + additionalProperties: false + unevaluatedProperties: false =20 allOf: @@ -140,6 +192,7 @@ allOf: aind-supply: false =20 # ad7380-4 uses refin-supply as external reference. + # adaq devices use internal reference only, derived from refin-supply # All other chips from ad738x family use refio as optional external refe= rence. # When refio-supply is omitted, internal reference is used. - if: @@ -147,6 +200,8 @@ allOf: compatible: enum: - adi,ad7380-4 + - adi,adaq4370-4 + - adi,adaq4380-4 then: properties: refio-supply: false @@ -156,6 +211,27 @@ allOf: properties: refin-supply: false =20 + # adaq devices need more supplies and using channel to declare gain prop= erty + # only applies to adaq devices + - if: + properties: + compatible: + enum: + - adi,adaq4370-4 + - adi,adaq4380-4 + then: + required: + - vs-p-supply + - vs-n-supply + - ldo-supply + else: + properties: + vs-p-supply: false + vs-n-supply: false + ldo-supply: false + patternProperties: + "^channel@([0-3])$": false + examples: - | #include @@ -180,3 +256,48 @@ examples: refio-supply =3D <&supply_2_5V>; }; }; + + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,adaq4380-4"; + reg =3D <0>; + + spi-cpol; + spi-cpha; + spi-max-frequency =3D <80000000>; + + interrupts =3D <27 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent =3D <&gpio0>; + + vcc-supply =3D <&supply_3_3V>; + vlogic-supply =3D <&supply_3_3V>; + refin-supply =3D <&supply_5V>; + vs-p-supply =3D <&supply_5V>; + vs-n-supply =3D <&supply_0V>; + ldo-supply =3D <&supply_5V>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { + reg =3D <0>; + adi,gain-milli =3D /bits/ 16 <300>; + }; + + channel@2 { + reg =3D <2>; + adi,gain-milli =3D /bits/ 16 <600>; + }; + + channel@3 { + reg =3D <3>; + adi,gain-milli =3D /bits/ 16 <1000>; + }; + }; + }; --=20 2.47.0 From nobody Mon Nov 25 23:36:29 2024 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1ECCF199E8D for ; Wed, 23 Oct 2024 09:19:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675187; cv=none; b=FPjAkMKY3XGlnkGGkIBE9PG9kTmwpIOekBbzjfM2s4l5C21OGmvJQpAgoJvSqd5+Kqe45pWfO4NKS/BjHMNc7BaH/yZoZchnB1K4foItGdjeiNepmkFehk067xUhG9x5Bcd31p17mD555/NEk7YtmXVhX92DQ3O+iznYi0Lclds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675187; c=relaxed/simple; bh=5SRDC9p9MKxswYnd7y6LZi2xIt2zZS6yBwCYc+hydFo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Y4COxjB2Usrjhp6sYM9TxXYfsXJAyYQUOS6H2yJSe3PxeucuQlbUjQFnQDgvzMoErR0+yZZFnZ3L3Kli/h0T6wKrK9uaEr0abdejcAczEzYmn+AoZ3rc87m8cIpGNb3KPcqkkr9gsfwfGoZmHX9Dm7Aq0zJpWuBHGSDnSxf4FnY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=CsMjOjtH; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="CsMjOjtH" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-43159c9f617so63456405e9.2 for ; Wed, 23 Oct 2024 02:19:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1729675184; x=1730279984; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cUAWPNA4323qWrX/2WYrVLftIYuIj6SGZHxAGWq4jNw=; b=CsMjOjtHvRXQRmEf5IvFY1TN/CQOSTPCIwET47Y9gQm3bkudfjMSmdEC9NnnlcflBy 3Ok5H7nB/taNEeIEtDgsthVVGbFu1ptCy2IAAZWVz2ghMJ3n+VNR/mpxiwL9GVAJr8af vBUck34qnR/2T51eXzg+mjJkTw4t1YkGLNbgsKLijqB0kdQWqsple1vFcE6VtEDEThJo 5Dqzy7gtSL8rlEbhu7dvC18a+QF6uGOPVPDlkyZAGxrypuBUiI119qj7eAWuWlBDoQuY kQ6TM0VD2Q2qYwoZHoUtzfiwHCjBp4AV2yZfM8S3CfccSHtPQQgdgeQslsWM/EXt+Jxx szxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729675184; x=1730279984; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cUAWPNA4323qWrX/2WYrVLftIYuIj6SGZHxAGWq4jNw=; b=Npo7RDRuf+Xv3sWA6r6bYH0ppcnWlQzGScXGDChTxYBphk1X3YROZynr3LSckJmRzp HF19WYCC0M9859mwAkT5MmtQ8KDSFLDsfbxeujNUnVg6I6BmhNYR0rHmToU2Tiy/1+Wp 5SaMBnRW+BszaTiJXM+jd/zR1AmpnIm2YF9K2sEjeHSr69Sv6TmH85XEVaZxkHjb/Qr/ wXZe9lynmPSvuyStPZZ7QRZJhA198lHWOLFKR9lQ97AP5qKZZ2EnXg8s3010TFxtz4rX 44cK/Gz+2+pZfGVqM5ktU1o6mN2a2h+5JmpqXpYtmUQF7OexBFaoAjkzq3i5M18EvqPY QsGA== X-Forwarded-Encrypted: i=1; AJvYcCVU4K+Q7DGp5NXMSq7+9yGRFxHRauLDaIqGORIG2fu+jbet42oNuZCe8bIzyYDXFdO6a3L9heR65gxoTLY=@vger.kernel.org X-Gm-Message-State: AOJu0Yzg40GpgKGGm3WKOHmeZjkuFNdqp5bN0ZSAoAUaxOBmCS01PKaK nzvO3L5GxAnXw5Mk7qqLXIdOiTt9HwdldXtWEhDWNEM7/yZ+2NDyfe3B/SYrRhU= X-Google-Smtp-Source: AGHT+IG/VNM8c02tydtDKFpvCLc9ekaOX1xJn8EkpeM34xOF4e3DBVakwkBUmUTvjMsgb3ifjqeRGQ== X-Received: by 2002:a05:600c:4f43:b0:431:3bf9:3ebb with SMTP id 5b1f17b1804b1-431841860eemr18352885e9.24.1729675184343; Wed, 23 Oct 2024 02:19:44 -0700 (PDT) Received: from [192.168.1.62] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0b94363sm8515796f8f.73.2024.10.23.02.19.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:19:43 -0700 (PDT) From: Julien Stephan Date: Wed, 23 Oct 2024 11:19:34 +0200 Subject: [PATCH v2 2/4] iio: adc: ad7380: fix oversampling formula Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241023-ad7380-add-adaq4380-4-support-v2-2-d55faea3bedf@baylibre.com> References: <20241023-ad7380-add-adaq4380-4-support-v2-0-d55faea3bedf@baylibre.com> In-Reply-To: <20241023-ad7380-add-adaq4380-4-support-v2-0-d55faea3bedf@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 The formula in the datasheet for oversampling time conversion seems to be valid when device is at full speed using the maximum number of SDO lines. The driver currently support only 1 SDO line. The formula will produce larger delays than what is currently set, but some devices actually require it. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index fb728570debe6432d5f991595cb35e9e7af8b740..d57e17f38925da5fb7c8a0a2320= a21474ba04b37 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -77,6 +77,12 @@ #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ #define T_POWERUP_US 5000 /* Power up */ =20 +/* + * AD738x support several SDO lines to increase throughput, but driver cur= rently + * supports only 1 SDO line (standard SPI transaction) + */ +#define AD7380_NUM_SDO_LINES 1 + struct ad7380_timing_specs { const unsigned int t_csh_ns; /* CS minimum high time */ }; @@ -649,7 +655,8 @@ static int ad7380_set_ch(struct ad7380_state *st, unsig= ned int ch) =20 if (st->oversampling_ratio > 1) xfer.delay.value =3D T_CONVERT_0_NS + - T_CONVERT_X_NS * (st->oversampling_ratio - 1); + T_CONVERT_X_NS * (st->oversampling_ratio - 1) * + st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; =20 return spi_sync_transfer(st->spi, &xfer, 1); } @@ -667,12 +674,13 @@ static void ad7380_update_xfers(struct ad7380_state *= st, =20 /* * In the case of oversampling, conversion time is higher than in normal - * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use - * the maximum value for simplicity for now. + * mode: t_convert =3D T_CONVERT_0_NS + T_CONVERT_X_NS*(x - 1)*num_channe= l/number_of_sdo_lines + * where x is the oversampling ratio */ if (st->oversampling_ratio > 1) t_convert =3D T_CONVERT_0_NS + T_CONVERT_X_NS * - (st->oversampling_ratio - 1); + (st->oversampling_ratio - 1) * + st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; =20 if (st->seq) { xfer[0].delay.value =3D xfer[1].delay.value =3D t_convert; @@ -1021,7 +1029,8 @@ static int ad7380_init(struct ad7380_state *st, bool = external_ref_en) /* SPI 1-wire mode */ return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, AD7380_CONFIG2_SDO, - FIELD_PREP(AD7380_CONFIG2_SDO, 1)); + FIELD_PREP(AD7380_CONFIG2_SDO, + AD7380_NUM_SDO_LINES)); } =20 static int ad7380_probe(struct spi_device *spi) --=20 2.47.0 From nobody Mon Nov 25 23:36:29 2024 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20D58199249 for ; Wed, 23 Oct 2024 09:19:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675189; cv=none; b=u8IWUzmWsvFYKp8hXyKbtVjVlkluYH78E5184Sn0iVRHEYJtWsaN2dE15gAFWqhmu2EK8Cz3QBJI3Xia+GFol42PLcXdzBhFgqxP4/O5licaoDnyTVzngqxzckfIBek9GB/FJM/8P9rv8gCx3xFDpQ2RHre019DWkjho0hE9qOk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675189; c=relaxed/simple; bh=QhSgXw9+FxAVu3KIGAcZuLYrsqUjXs1NwiZ5dTJtzkM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L3yrThQMG0civKLhuDmGaKjcUP/GqMeYyrzy4zRtLwhARxQUfIfDB+37kFe5AaEWsU0K+jrKVK0e3ldDlzhCIzO6GMdikrFkTnPrDNZ4IXvBqIl/uHY/wvPlBYd9+w+Ss4I5veLYov9vFkh+lhhJObPsTt8Th++bL0ngJtpUJSE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=bF3ydEjC; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="bF3ydEjC" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4314a26002bso72448665e9.0 for ; Wed, 23 Oct 2024 02:19:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1729675185; x=1730279985; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=r9ZTZkJcchnwItyNdW/fmdcznA8MqL8OTNkbgt7Dhqk=; b=bF3ydEjC5ICKIVirnYrP2jDr8Oq2ioo0jLfeI1g6Nm/t3IoRtJGNUO/MEHIXukrYlZ 4/n0OxUOZ9Y8spJ84Br5R6N1NRASZ7or7h6XpAGsJUhlu/h7V52cqvSH234dpJPvONOa xBRieCafhrUdmqbTYdtoYOYV2d4CcawOSf85FrkiBqlrdC9n2yQi6yIYqkDxN5vvTgOB GUjxjqwFJrjm/7tEQrQf6aZuXX2GkEPZQyeZF7Z9SYFnwbfMbJ+o1tS+ATn2WeEhiZRn b4fyeyAKxkgk/ipABq1Z/nkOAxYShvu79Zovlv7JHHvi5KIDX4JFxXzwQ4WpttQRSNOi uqiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729675185; x=1730279985; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r9ZTZkJcchnwItyNdW/fmdcznA8MqL8OTNkbgt7Dhqk=; b=AjK2y8vOx6PU02u6+Qvj5pxWucCAkGabl1hvo8/98ivBgdBerm6AigEUxkBOdkcVqk Xl0S9ebztQ6IwcNKT1/gvGafFD4K/LHjm4z0xMrqs/j2nhao91D92AtEoJlDlSGZOBcf PDEflhWsh7pQMHU4E/KhL4mhFt0s2YH/AMPyVhqL6LstAiKCa0OYK6m08AUmeXkw7SmO TahMyam4/eOrb8gvHJyN6Frd2KmC+BVmqagf9DuRAL4Sl0WrovhkQGjZw68L+8u1hLNY DaA7kpDY1lrvKwdf828gTQGjVpmoj5vPsce3MKI8W6vda2qKJD9JRwesL1ZKBqUsj4Rv w9nA== X-Forwarded-Encrypted: i=1; AJvYcCVggUSLn9jw8y7ARvHlZ6VnSWtJ9Hc/2XSEO8mnbMhoPsAe0t/CTeLfkDx41cqOmi2EbJJvvQ4wpwPMujM=@vger.kernel.org X-Gm-Message-State: AOJu0YxR175DJXUIzLUHVKpfR9V1hDehpPP2upj2j8G4iDuSiacmo3NH 8/qLQcY+ooNt3kS0kcv2hlGtZTcTSG50bU40n5Wyvte9xwao+hHF1DFYSxF+QLg= X-Google-Smtp-Source: AGHT+IGI5JkLtZOklAyF9qDgpeZR5hHRe4UkAIO8ixgJX7CRl1M32U3FnDPmO2N0+O/WzKvw7SKSxg== X-Received: by 2002:a05:600c:1c9c:b0:431:1a98:cb40 with SMTP id 5b1f17b1804b1-4318415b234mr15067035e9.18.1729675185188; Wed, 23 Oct 2024 02:19:45 -0700 (PDT) Received: from [192.168.1.62] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0b94363sm8515796f8f.73.2024.10.23.02.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:19:44 -0700 (PDT) From: Julien Stephan Date: Wed, 23 Oct 2024 11:19:35 +0200 Subject: [PATCH v2 3/4] iio: adc: ad7380: add support for adaq4370-4 and adaq4380-4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241023-ad7380-add-adaq4380-4-support-v2-3-d55faea3bedf@baylibre.com> References: <20241023-ad7380-add-adaq4380-4-support-v2-0-d55faea3bedf@baylibre.com> In-Reply-To: <20241023-ad7380-add-adaq4380-4-support-v2-0-d55faea3bedf@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 adaq4370-4 (2MSPS) and adaq4380-4 (4MSPS) are quad-channel precision data acquisition signal chain =CE=BCModule solutions compatible with the ad738x family, with the following differences: - pin selectable gain in front of each 4 adc - internal reference is 3V derived from refin-supply (5V) - additional supplies This implies that IIO_CHAN_INFO_SCALE can not be shared by type. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 130 +++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 126 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index d57e17f38925da5fb7c8a0a2320a21474ba04b37..f36dc27b8f9da7ebc7551193b5d= 847f7e8bef396 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -13,6 +13,8 @@ * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7381-4.pdf * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/ad7383-4-ad7384-4.pdf * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/= data-sheets/ad7386-4-7387-4-7388-4.pdf + * adaq4370-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/adaq4370-4.pdf + * adaq4380-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/adaq4380-4.pdf */ =20 #include @@ -22,11 +24,14 @@ #include #include #include +#include #include #include #include #include #include +#include +#include =20 #include #include @@ -36,6 +41,8 @@ #define MAX_NUM_CHANNELS 8 /* 2.5V internal reference voltage */ #define AD7380_INTERNAL_REF_MV 2500 +/* 3.3V internal reference voltage for ADAQ */ +#define ADAQ4380_INTERNAL_REF_MV 3300 =20 /* reading and writing registers is more reliable at lower than max speed = */ #define AD7380_REG_WR_SPEED_HZ 10000000 @@ -82,6 +89,7 @@ * supports only 1 SDO line (standard SPI transaction) */ #define AD7380_NUM_SDO_LINES 1 +#define AD7380_DEFAULT_GAIN_MILLI 1000 =20 struct ad7380_timing_specs { const unsigned int t_csh_ns; /* CS minimum high time */ @@ -92,10 +100,12 @@ struct ad7380_chip_info { const struct iio_chan_spec *channels; unsigned int num_channels; unsigned int num_simult_channels; + bool has_hardware_gain; bool has_mux; const char * const *supplies; unsigned int num_supplies; bool external_ref_only; + bool adaq_internal_ref_only; const char * const *vcm_supplies; unsigned int num_vcm_supplies; const unsigned long *available_scan_masks; @@ -187,11 +197,12 @@ static const struct iio_scan_type ad7380_scan_type_16= _u[] =3D { }, }; =20 -#define AD7380_CHANNEL(index, bits, diff, sign) { \ +#define _AD7380_CHANNEL(index, bits, diff, sign, gain) { \ .type =3D IIO_VOLTAGE, \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ - .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ + .info_mask_shared_by_type =3D ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_type_available =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ @@ -205,6 +216,12 @@ static const struct iio_scan_type ad7380_scan_type_16_= u[] =3D { .num_ext_scan_type =3D ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \ } =20 +#define AD7380_CHANNEL(index, bits, diff, sign) \ + _AD7380_CHANNEL(index, bits, diff, sign, false) + +#define ADAQ4380_CHANNEL(index, bits, diff, sign) \ + _AD7380_CHANNEL(index, bits, diff, sign, true) + #define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \ static const struct iio_chan_spec name[] =3D { \ AD7380_CHANNEL(0, bits, diff, sign), \ @@ -221,6 +238,15 @@ static const struct iio_chan_spec name[] =3D { \ IIO_CHAN_SOFT_TIMESTAMP(4), \ } =20 +#define DEFINE_ADAQ4380_4_CHANNEL(name, bits, diff, sign) \ +static const struct iio_chan_spec name[] =3D { \ + ADAQ4380_CHANNEL(0, bits, diff, sign), \ + ADAQ4380_CHANNEL(1, bits, diff, sign), \ + ADAQ4380_CHANNEL(2, bits, diff, sign), \ + ADAQ4380_CHANNEL(3, bits, diff, sign), \ + IIO_CHAN_SOFT_TIMESTAMP(4), \ +} + #define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \ static const struct iio_chan_spec name[] =3D { \ AD7380_CHANNEL(0, bits, diff, sign), \ @@ -239,6 +265,7 @@ DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s); DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s); DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s); DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s); +DEFINE_ADAQ4380_4_CHANNEL(adaq4380_4_channels, 16, 1, s); /* pseudo differential */ DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s); DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s); @@ -257,6 +284,10 @@ static const char * const ad7380_supplies[] =3D { "vcc", "vlogic", }; =20 +static const char * const adaq4380_supplies[] =3D { + "ldo", "vcc", "vlogic", "vs-p", "vs-n", "refin", +}; + static const char * const ad7380_2_channel_vcm_supplies[] =3D { "aina", "ainb", }; @@ -347,6 +378,11 @@ static const int ad7380_oversampling_ratios[] =3D { 1, 2, 4, 8, 16, 32, }; =20 +/* Gains stored as fractions of 1000 so they can be expressed by integers.= */ +static const int ad7380_gains[] =3D { + 300, 600, 1000, 1600, +}; + static const struct ad7380_chip_info ad7380_chip_info =3D { .name =3D "ad7380", .channels =3D ad7380_channels, @@ -516,6 +552,32 @@ static const struct ad7380_chip_info ad7388_4_chip_inf= o =3D { .timing_specs =3D &ad7380_4_timing, }; =20 +static const struct ad7380_chip_info adaq4370_4_chip_info =3D { + .name =3D "adaq4370-4", + .channels =3D adaq4380_4_channels, + .num_channels =3D ARRAY_SIZE(adaq4380_4_channels), + .num_simult_channels =3D 4, + .supplies =3D adaq4380_supplies, + .num_supplies =3D ARRAY_SIZE(adaq4380_supplies), + .adaq_internal_ref_only =3D true, + .has_hardware_gain =3D true, + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info adaq4380_4_chip_info =3D { + .name =3D "adaq4380-4", + .channels =3D adaq4380_4_channels, + .num_channels =3D ARRAY_SIZE(adaq4380_4_channels), + .num_simult_channels =3D 4, + .supplies =3D adaq4380_supplies, + .num_supplies =3D ARRAY_SIZE(adaq4380_supplies), + .adaq_internal_ref_only =3D true, + .has_hardware_gain =3D true, + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; @@ -526,6 +588,7 @@ struct ad7380_state { bool seq; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; + unsigned int gain_milli[MAX_NUM_CHANNELS]; /* xfers, message an buffer for reading sample data */ struct spi_transfer normal_xfer[2]; struct spi_message normal_msg; @@ -876,8 +939,15 @@ static int ad7380_read_raw(struct iio_dev *indio_dev, * * (2 =C3=97 VREF) / 2^N, for differential chips * * VREF / 2^N, for pseudo-differential chips * where N is the ADC resolution (i.e realbits) + * + * The gain is stored as a fraction of 1000 and, as we need to + * divide vref_mv by the gain, we invert the gain/1000 fraction. */ - *val =3D st->vref_mv; + if (st->chip_info->has_hardware_gain) + *val =3D mult_frac(st->vref_mv, MILLI, + st->gain_milli[chan->scan_index]); + else + *val =3D st->vref_mv; *val2 =3D scan_type->realbits - chan->differential; =20 return IIO_VAL_FRACTIONAL_LOG2; @@ -1058,7 +1128,19 @@ static int ad7380_probe(struct spi_device *spi) "Failed to enable power supplies\n"); fsleep(T_POWERUP_US); =20 - if (st->chip_info->external_ref_only) { + if (st->chip_info->adaq_internal_ref_only) { + /* + * ADAQ chips use fixed internal reference but still + * require a specific reference supply to power it. + * "refin" is already enabled with other power supplies + * in bulk_get_enable(). + */ + + st->vref_mv =3D ADAQ4380_INTERNAL_REF_MV; + + /* these chips don't have a register bit for this */ + external_ref_en =3D false; + } else if (st->chip_info->external_ref_only) { ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "refin"); if (ret < 0) @@ -1104,6 +1186,42 @@ static int ad7380_probe(struct spi_device *spi) st->vcm_mv[i] =3D ret / 1000; } =20 + for (i =3D 0; i < MAX_NUM_CHANNELS; i++) + st->gain_milli[i] =3D AD7380_DEFAULT_GAIN_MILLI; + + if (st->chip_info->has_hardware_gain) { + device_for_each_child_node_scoped(&spi->dev, node) { + unsigned int channel, gain; + int gain_idx; + + ret =3D fwnode_property_read_u32(node, "reg", &channel); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to read reg property\n"); + + if (channel >=3D st->chip_info->num_channels - 1) + return dev_err_probe(&spi->dev, -EINVAL, + "Invalid channel number %i\n", + channel); + + ret =3D fwnode_property_read_u32(node, "adi,gain-milli", + &gain); + if (ret && ret !=3D -EINVAL) + return dev_err_probe(&spi->dev, ret, + "Failed to read gain for channel %i\n", + channel); + if (ret !=3D -EINVAL) { + /* + * Match gain value from dt to one of supported + * gains + */ + gain_idx =3D find_closest(gain, ad7380_gains, + ARRAY_SIZE(ad7380_gains)); + st->gain_milli[channel] =3D ad7380_gains[gain_idx]; + } + } + } + st->regmap =3D devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_confi= g); if (IS_ERR(st->regmap)) return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), @@ -1186,6 +1304,8 @@ static const struct of_device_id ad7380_of_match_tabl= e[] =3D { { .compatible =3D "adi,ad7386-4", .data =3D &ad7386_4_chip_info }, { .compatible =3D "adi,ad7387-4", .data =3D &ad7387_4_chip_info }, { .compatible =3D "adi,ad7388-4", .data =3D &ad7388_4_chip_info }, + { .compatible =3D "adi,adaq4370-4", .data =3D &adaq4370_4_chip_info }, + { .compatible =3D "adi,adaq4380-4", .data =3D &adaq4380_4_chip_info }, { } }; =20 @@ -1204,6 +1324,8 @@ static const struct spi_device_id ad7380_id_table[] = =3D { { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info }, { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info }, { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info }, + { "adaq4370-4", (kernel_ulong_t)&adaq4370_4_chip_info }, + { "adaq4380-4", (kernel_ulong_t)&adaq4380_4_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad7380_id_table); --=20 2.47.0 From nobody Mon Nov 25 23:36:29 2024 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F50A19F421 for ; Wed, 23 Oct 2024 09:19:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675190; cv=none; b=qNj//8RnRzB0LBNbjwx0GCpCBhFpzh7Ymob8pPbDSJXAXlyL0dzXTrnNQui+xrVVNWrcGIEQzQj4bLvwvaopcovL2Lw8SuplJzTLmM6U+NCHs+aPATqUb6rPheFbR4vNudXbNCjXqA37w1F3g6xPPIF5tDZkPexyE0ZxOTvfFJk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729675190; c=relaxed/simple; bh=ur2xrohuXdp+XK2W9kNkEGxeD+PeEi9hqLfcXSWTqkM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PKsWZBpK87IV7viXZ5RuXTWteDHDdCROHgPrf3TiPfOawDLa3Qc5lfYAhKRVCSqqivXNK5/TFjxhzUAEqoyJLpf/394bdfNnSpYUuofuFvOUd/vAe/ealJTctqV7iMzLlx35RLt6VSqFtOimnJzt8jOhD4X3SQhgJBEjnKYkLG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=KmlhUT+J; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="KmlhUT+J" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-37d41894a32so450276f8f.1 for ; Wed, 23 Oct 2024 02:19:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1729675186; x=1730279986; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jrgH1600uHhvBk1qPJnNVTmvv8RgMwdXL0zxz051j4c=; b=KmlhUT+JjIRVhP2l2zNPEE/84mI9pAV6iVZWqbqJ6m2dzxhf6tYzDLtN9zVLucsvwO 6P4MP4GEINB2bBDEDD4ddY2Tr7FAuEpv2bL6rJZN3c2jfB1sFiRZx5KtPm2GTQHPcQI7 VDh1bWnPsdN5oYODf7zvbJ3Af3UkPeDDTCevNupm4e34j4q9iaIpjdLkoiENUbHRowo4 B2ZgfgYZP2aEAlBo3PjltnPIsm/6ZHp0Ty4mOtWn7Ik0++m8Nv/LOf0lp5LrV4+SF70T imhhxEo8UAcramYveXDXxTUw7ViFviN8VSNVLFo7/I/Ls84aleU0l35dfOGvdjDYaXJE 3FXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729675186; x=1730279986; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jrgH1600uHhvBk1qPJnNVTmvv8RgMwdXL0zxz051j4c=; b=BdCm/DoVZhQN8bEtjryW0JbittkXwYXdjtfoavGGViPIsUKF65n8tPXqF2+KKWjS3B m4lIkU4Bm7juq6EFnoavLJZrepCTPMSe6pSWu1QiWVHqTKR3pfaEMmoCMra8+Brj0bTl 0D7E4SCjf4820dE9EZb/jo69Vx2TAksZNrAyvRopskTE5PN3se4Qh5StiRt2zINQDbzm Npopg6nzP11gu6iDwSvi1dAXFM8TzgsYirdkeQ13rovjlXAbTVXfL8nqauU6FsYfs3Xy usbG3iOjzDMBHb00DnhY/EZcvXUg32RFfyNoMLPPrsaNOmpv7Rk2auuykTuoc1vIuuWR b3rA== X-Forwarded-Encrypted: i=1; AJvYcCXkMZmOzONqTyoX0uckWWwgex93Sn8YWum0FCYYE4In3570tPL7rm4OYWUDMFimP2j4tVk7ZgpUC480EcI=@vger.kernel.org X-Gm-Message-State: AOJu0YwjfV7C6dtDx1qVknLKLgAg/THc3CjATjuyOGNiwjdMcBUhfG9C /pJ31LRTNsw+ApVFg78fonQU/X9+yvzH7Iohmv9sKoC3FuNyoAsbMOhrZm0CrD0= X-Google-Smtp-Source: AGHT+IG7i9cBORVipXN1XrnApLPL139RzqZXid7n7NRI2h7TniBq6yDje6T+sE35UDZsVYVp9lNWOQ== X-Received: by 2002:adf:fe03:0:b0:37d:3f81:153f with SMTP id ffacd0b85a97d-37efc5f0b29mr1109962f8f.17.1729675186417; Wed, 23 Oct 2024 02:19:46 -0700 (PDT) Received: from [192.168.1.62] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0b94363sm8515796f8f.73.2024.10.23.02.19.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:19:45 -0700 (PDT) From: Julien Stephan Date: Wed, 23 Oct 2024 11:19:36 +0200 Subject: [PATCH v2 4/4] docs: iio: ad7380: add adaq4370-4 and adaq4380-4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241023-ad7380-add-adaq4380-4-support-v2-4-d55faea3bedf@baylibre.com> References: <20241023-ad7380-add-adaq4380-4-support-v2-0-d55faea3bedf@baylibre.com> In-Reply-To: <20241023-ad7380-add-adaq4380-4-support-v2-0-d55faea3bedf@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 Adding documentation for adaq4370-4 and adaq4380-4 supported devices. In particular, document the reference voltage mechanism and the gain parameter that are specific to adaq devices. Signed-off-by: Julien Stephan --- Documentation/iio/ad7380.rst | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/iio/ad7380.rst b/Documentation/iio/ad7380.rst index 6f70b49b9ef27c1ac32acaefecd1146e5c8bd6cc..ae408ff2fa9c97427a9fef57020= fb54203d2d33e 100644 --- a/Documentation/iio/ad7380.rst +++ b/Documentation/iio/ad7380.rst @@ -27,6 +27,8 @@ The following chips are supported by this driver: * `AD7386-4 `_ * `AD7387-4 `_ * `AD7388-4 `_ +* `ADAQ4370-4 `_ +* `ADAQ4380-4 `_ =20 =20 Supported features @@ -47,6 +49,12 @@ ad7380-4 ad7380-4 supports only an external reference voltage (2.5V to 3.3V). It mu= st be declared in the device tree as ``refin-supply``. =20 +adaq devices +~~~~~~~~~~~~ + +adaq4370-4 and adaq4380-4 don't have an external reference, but use a 3V +internal reference derived from one of its supplies (``refin-supply``) + All other devices from ad738x family ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ =20 @@ -121,6 +129,16 @@ Example for AD7386/7/8 (2 channels parts): =20 When enabling sequencer mode, the effective sampling rate is divided by tw= o. =20 + +Gain (adaq devices only) +~~~~~~~~~~~~~~~~~~~~~~~~ + +adaq devices have a pin selectable gain in front of each adc. The appropri= ate +gain is selectable from device tree using the ``adi,gain-milli`` property. +Refer to the typical connection diagrams section of the datasheet for pin +wiring. + + Unimplemented features ---------------------- =20 --=20 2.47.0