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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000989EC.mail.protection.outlook.com (10.167.241.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Tue, 22 Oct 2024 19:42:49 +0000 Received: from titanite-d354host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Oct 2024 14:42:48 -0500 From: Avadhut Naik To: , , CC: , , , , , , , , , , Subject: [PATCH v7 3/5] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers Date: Tue, 22 Oct 2024 19:36:29 +0000 Message-ID: <20241022194158.110073-4-avadhut.naik@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241022194158.110073-1-avadhut.naik@amd.com> References: <20241022194158.110073-1-avadhut.naik@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|LV8PR12MB9136:EE_ X-MS-Office365-Filtering-Correlation-Id: 8415452b-5876-4c08-fb89-08dcf2d1b63c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2024 19:42:49.7741 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8415452b-5876-4c08-fb89-08dcf2d1b63c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9136 Content-Type: text/plain; charset="utf-8" Starting with Zen4, AMD's Scalable MCA systems incorporate two new registers: MCA_SYND1 and MCA_SYND2. These registers will include supplemental error information in addition to the existing MCA_SYND register. The data within these registers is considered valid if MCA_STATUS[SyndV] is set. Userspace error decoding tools like the rasdaemon gather related hardware error information through the tracepoints. As such, these two registers should be exported through the mce_record tracepoint so that tools like rasdaemon can parse them and output the supplemental error information like FRU Text contained in them. [Yazen: Drop Yazen's Co-developed-by tag and moved SoB tag.] Signed-off-by: Avadhut Naik Signed-off-by: Yazen Ghannam Signed-off-by: Avadhut Naik --- Changes in v2: [1] https://lore.kernel.org/linux-edac/20240521125434.1555845-1-yazen.ghann= am@amd.com/ [2] https://lore.kernel.org/linux-edac/20240523155641.2805411-1-yazen.ghann= am@amd.com/ 1. Drop dependencies on sets [1] and [2] above and rebase on top of tip/master. Changes in v3: 1. Move wrapper changes required in mce_read_aux() and mce_no_way_out() from this patch to the first patch. 2. Add comments to explain the new wrapper's purpose. 3. Modify commit message per feedback received. 4. Fix SoB chain to properly reflect the patch path. Changes in v4: 1. Rebase on top of tip/master to avoid merge conflicts. Changes in v5: 1. Remove "len" field since the length of a dynamic array can be fetched from its metadata. 2. Substitute __print_array() with __print_dynamic_array(). Changes in v6: 1. Rebase on top of tip/master. 2. Use the newly introduced to_mce_hw_err macro in amd_decode_mce(). Changes in v7: 1. Rebase on top of tip/master. 2. Change second parameter of __print_dynamic_array from 8 to sizeof(u8) to ensure that the dynamic array is parsed using a u8 pointer instead of u64 pointer. --- arch/x86/include/asm/mce.h | 22 ++++++++++++++++++++++ arch/x86/include/uapi/asm/mce.h | 3 ++- arch/x86/kernel/cpu/mce/amd.c | 5 ++++- arch/x86/kernel/cpu/mce/core.c | 9 ++++++++- drivers/edac/mce_amd.c | 8 ++++++-- include/trace/events/mce.h | 7 +++++-- 6 files changed, 47 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 4e45f45673a3..c2466b20fe79 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -122,6 +122,9 @@ #define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008 #define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009 #define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a +/* Registers MISC2 to MISC4 are at offsets B to D. */ +#define MSR_AMD64_SMCA_MC0_SYND1 0xc000200e +#define MSR_AMD64_SMCA_MC0_SYND2 0xc000200f #define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x)) #define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x)) #define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x)) @@ -132,6 +135,8 @@ #define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x)) #define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x)) #define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (= 0x10*(x))) +#define MSR_AMD64_SMCA_MCx_SYND1(x) (MSR_AMD64_SMCA_MC0_SYND1 + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_SYND2(x) (MSR_AMD64_SMCA_MC0_SYND2 + 0x10*(x)) =20 #define XEC(x, mask) (((x) >> 16) & mask) =20 @@ -190,9 +195,26 @@ enum mce_notifier_prios { /** * struct mce_hw_err - Hardware Error Record. * @m: Machine Check record. + * @vendor: Vendor-specific error information. + * + * Vendor-specific fields should not be added to struct mce. + * Instead, vendors should export their vendor-specific data + * through their structure in the vendor union below. + * + * AMD's vendor data is parsed by error decoding tools for + * supplemental error information. Thus, current offsets of + * existing fields must be maintained. + * Only add new fields at the end of AMD's vendor structure. */ struct mce_hw_err { struct mce m; + + union vendor_info { + struct { + u64 synd1; /* MCA_SYND1 MSR */ + u64 synd2; /* MCA_SYND2 MSR */ + } amd; + } vendor; }; =20 #define to_mce_hw_err(mce) container_of(mce, struct mce_hw_err, m) diff --git a/arch/x86/include/uapi/asm/mce.h b/arch/x86/include/uapi/asm/mc= e.h index db9adc081c5a..cb6b48a7c22b 100644 --- a/arch/x86/include/uapi/asm/mce.h +++ b/arch/x86/include/uapi/asm/mce.h @@ -8,7 +8,8 @@ /* * Fields are zero when not available. Also, this struct is shared with * userspace mcelog and thus must keep existing fields at current offsets. - * Only add new fields to the end of the structure + * Only add new, shared fields to the end of the structure. + * Do not add vendor-specific fields. */ struct mce { __u64 status; /* Bank's MCi_STATUS MSR */ diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 5b4d266500b2..6ca80fff1fea 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -797,8 +797,11 @@ static void __log_error(unsigned int bank, u64 status,= u64 addr, u64 misc) if (mce_flags.smca) { rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid); =20 - if (m->status & MCI_STATUS_SYNDV) + if (m->status & MCI_STATUS_SYNDV) { rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd); + rdmsrl(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1); + rdmsrl(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2); + } } =20 mce_log(&err); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 3611366d56b7..fca23fe16abe 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -202,6 +202,10 @@ static void __print_mce(struct mce_hw_err *err) if (mce_flags.smca) { if (m->synd) pr_cont("SYND %llx ", m->synd); + if (err->vendor.amd.synd1) + pr_cont("SYND1 %llx ", err->vendor.amd.synd1); + if (err->vendor.amd.synd2) + pr_cont("SYND2 %llx ", err->vendor.amd.synd2); if (m->ipid) pr_cont("IPID %llx ", m->ipid); } @@ -678,8 +682,11 @@ static noinstr void mce_read_aux(struct mce_hw_err *er= r, int i) if (mce_flags.smca) { m->ipid =3D mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); =20 - if (m->status & MCI_STATUS_SYNDV) + if (m->status & MCI_STATUS_SYNDV) { m->synd =3D mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); + err->vendor.amd.synd1 =3D mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND1(i)); + err->vendor.amd.synd2 =3D mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND2(i)); + } } } =20 diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 8130c3dc64da..194d9fd47d20 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -793,6 +793,7 @@ static int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) { struct mce *m =3D (struct mce *)data; + struct mce_hw_err *err =3D to_mce_hw_err(m); unsigned int fam =3D x86_family(m->cpuid); int ecc; =20 @@ -850,8 +851,11 @@ amd_decode_mce(struct notifier_block *nb, unsigned lon= g val, void *data) if (boot_cpu_has(X86_FEATURE_SMCA)) { pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid); =20 - if (m->status & MCI_STATUS_SYNDV) - pr_cont(", Syndrome: 0x%016llx", m->synd); + if (m->status & MCI_STATUS_SYNDV) { + pr_cont(", Syndrome: 0x%016llx\n", m->synd); + pr_emerg(HW_ERR "Syndrome1: 0x%016llx, Syndrome2: 0x%016llx", + err->vendor.amd.synd1, err->vendor.amd.synd2); + } =20 pr_cont("\n"); =20 diff --git a/include/trace/events/mce.h b/include/trace/events/mce.h index 65aba1afcd07..c1c50df9ecfd 100644 --- a/include/trace/events/mce.h +++ b/include/trace/events/mce.h @@ -43,6 +43,7 @@ TRACE_EVENT(mce_record, __field( u8, bank ) __field( u8, cpuvendor ) __field( u32, microcode ) + __dynamic_array(u8, v_data, sizeof(err->vendor)) ), =20 TP_fast_assign( @@ -65,9 +66,10 @@ TRACE_EVENT(mce_record, __entry->bank =3D err->m.bank; __entry->cpuvendor =3D err->m.cpuvendor; __entry->microcode =3D err->m.microcode; + memcpy(__get_dynamic_array(v_data), &err->vendor, sizeof(err->vendor)); ), =20 - TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, IPID: %016Lx, ADDR: = %016Lx, MISC: %016Lx, SYND: %016Lx, RIP: %02x:<%016Lx>, TSC: %llx, PPIN: %l= lx, vendor: %u, CPUID: %x, time: %llu, socket: %u, APIC: %x, microcode: %x", + TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016llx, IPID: %016llx, ADDR= : %016llx, MISC: %016llx, SYND: %016llx, RIP: %02x:<%016llx>, TSC: %llx, PP= IN: %llx, vendor: %u, CPUID: %x, time: %llu, socket: %u, APIC: %x, microcod= e: %x, vendor data: %s", __entry->cpu, __entry->mcgcap, __entry->mcgstatus, __entry->bank, __entry->status, @@ -83,7 +85,8 @@ TRACE_EVENT(mce_record, __entry->walltime, __entry->socketid, __entry->apicid, - __entry->microcode) + __entry->microcode, + __print_dynamic_array(v_data, sizeof(u8))) ); =20 #endif /* _TRACE_MCE_H */ --=20 2.43.0