From nobody Tue Nov 26 01:59:04 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABFD619B5B4; Tue, 22 Oct 2024 15:45:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611914; cv=none; b=DrDfaZ8TJUXFlZHiTCnSF8HSNrbjRZAcrwW1EKVSwns4MR5VC1gS5FPRJsGLkQ/65HGEgCWbKwvu+JlLUS560aUdlyQN7T3I6tztBcvuMko7jzOx6Eo0/UJvSRqtUcvByqvhPGcvW/HVHWMZqFQ9RBae7iMrba6tmNB4aTdWIhk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611914; c=relaxed/simple; bh=O5swrGRgXY7L7+HtzQsEkzO+Z95c/1GCTlkAs6oxEew=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bNFm0tAzWIdQV8c2zA3b5G2JMMA0qp4O7FwiuTq/DeO8hUXVARQk5udkDctb1rESlBrsUv9vKnEiacgAW/HXMEixvnnuqxfGib/YdZbD+lw1/PD+S558Glr8YimuFQ6ymg2DtT98jU9DbT1DnzZO11VTDkXM3+uXHinMOeaEEZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=NJmsV0IK; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="NJmsV0IK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1729611909; bh=O5swrGRgXY7L7+HtzQsEkzO+Z95c/1GCTlkAs6oxEew=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NJmsV0IKI06XGV5IUdfoca8QXYx9RIflAofFkxHLgL0MhQCw/M2yeVbdog43y4aai mybhNVd3wW1ERUoehxibW0/mb92THtAxkdySCZritT1Hw0AvHjQy921erX2zGXOSGt C0uRPr9/Vbx5gmPgeKScQlWKS8lwaGE/+zQ3XPPKF/nZniTXH2oshV67SG3gbPho6/ aSm9NHi6PISyPubRJyIR8tzBpITe8dbJi9W4mdA1VPd/HA+b/G8bj9EkZV0MZzMZxv qgEQkVvLuFbvAp5FUfPIcN5bcNtekPl8hJzVgGFRHFLmdZk60agoiyZwEAaSby/RvD 27QiM5PFn4tgw== Received: from jupiter.universe (dyndsl-091-248-085-026.ewe-ip-backbone.de [91.248.85.26]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id B6C3D17E367B; Tue, 22 Oct 2024 17:45:09 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 661C74800E4; Tue, 22 Oct 2024 17:45:09 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson , Mark Brown Cc: Liam Girdwood , Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 1/7] regulator: Add (devm_)of_regulator_get() Date: Tue, 22 Oct 2024 17:41:46 +0200 Message-ID: <20241022154508.63563-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241022154508.63563-1-sebastian.reichel@collabora.com> References: <20241022154508.63563-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Rockchip power-domain controller also plans to make use of per-domain regulators similar to the MediaTek power-domain controller. Since existing DTs are missing the regulator information, the kernel should fallback to the automatically created dummy regulator if necessary. Thus the version without the _optional suffix is needed. The Rockchip driver plans to use the managed version, but to be consistent with existing code the unmanaged version is added at the same time. Signed-off-by: Sebastian Reichel Tested-by: Heiko Stuebner --- drivers/regulator/devres.c | 17 +++++++++++++++++ drivers/regulator/of_regulator.c | 21 +++++++++++++++++++++ include/linux/regulator/consumer.h | 6 ++++++ 3 files changed, 44 insertions(+) diff --git a/drivers/regulator/devres.c b/drivers/regulator/devres.c index 36164aec30e8..a3a3ccc711fc 100644 --- a/drivers/regulator/devres.c +++ b/drivers/regulator/devres.c @@ -771,6 +771,23 @@ static struct regulator *_devm_of_regulator_get(struct= device *dev, struct devic return regulator; } =20 +/** + * devm_of_regulator_get - Resource managed of_regulator_get() + * @dev: device used for dev_printk() messages and resource lifetime manag= ement + * @node: device node for regulator "consumer" + * @id: supply name or regulator ID. + * + * Managed of_regulator_get(). Regulators returned from this + * function are automatically regulator_put() on driver detach. See + * of_regulator_get() for more information. + */ +struct regulator *devm_of_regulator_get(struct device *dev, struct device_= node *node, + const char *id) +{ + return _devm_of_regulator_get(dev, node, id, NORMAL_GET); +} +EXPORT_SYMBOL_GPL(devm_of_regulator_get); + /** * devm_of_regulator_get_optional - Resource managed of_regulator_get_opti= onal() * @dev: device used for dev_printk() messages and resource lifetime manag= ement diff --git a/drivers/regulator/of_regulator.c b/drivers/regulator/of_regula= tor.c index 3d85762beda6..31a5bacd99b4 100644 --- a/drivers/regulator/of_regulator.c +++ b/drivers/regulator/of_regulator.c @@ -682,6 +682,27 @@ struct regulator *_of_regulator_get(struct device *dev= , struct device_node *node return _regulator_get_common(r, dev, id, get_type); } =20 +/** + * of_regulator_get - get regulator via device tree lookup + * @dev: device used for dev_printk() messages + * @node: device node for regulator "consumer" + * @id: Supply name + * + * Return: pointer to struct regulator corresponding to the regulator prod= ucer, + * or PTR_ERR() encoded error number. + * + * This is intended for use by consumers that want to get a regulator + * supply directly from a device node. This will _not_ consider supply + * aliases. See regulator_dev_lookup(). + */ +struct regulator *of_regulator_get(struct device *dev, + struct device_node *node, + const char *id) +{ + return _of_regulator_get(dev, node, id, NORMAL_GET); +} +EXPORT_SYMBOL_GPL(of_regulator_get); + /** * of_regulator_get_optional - get optional regulator via device tree look= up * @dev: device used for dev_printk() messages diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/c= onsumer.h index 8c3c372ad735..5903ae7444ae 100644 --- a/include/linux/regulator/consumer.h +++ b/include/linux/regulator/consumer.h @@ -169,6 +169,12 @@ void regulator_put(struct regulator *regulator); void devm_regulator_put(struct regulator *regulator); =20 #if IS_ENABLED(CONFIG_OF) +struct regulator *__must_check of_regulator_get(struct device *dev, + struct device_node *node, + const char *id); +struct regulator *__must_check devm_of_regulator_get(struct device *dev, + struct device_node *node, + const char *id); struct regulator *__must_check of_regulator_get_optional(struct device *de= v, struct device_node *node, const char *id); --=20 2.45.2 From nobody Tue Nov 26 01:59:04 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9674519ABB7; Tue, 22 Oct 2024 15:45:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611913; cv=none; b=cSZN0XmL7kZFY/0wNR09YG2/8J8S7pJUnzrAmBvGCqe0hgW+zxxY7N3V/iblfGUjVrKNcVYX2V4NKjWem+a4sp5qDzNAhPrrpnrTTnJKOKLc7lzLq5DLs7WoyUMN5nJ1Ijxe+DZzbZ4RndaxyUN13MDNyLtzfWiwam7kP9ufdLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611913; c=relaxed/simple; bh=fC0pCAo2XvTLTelwyvhpjGUBmtu099+nMxksrhgRHPU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VmVxi+qF+lRxoqASz5aKbMLCMymcICDZuEwFBUbjwC/xIFFMRqVyHi/A1jcgpf2p7GYc6OLT3NfwFRVVnGMDSSZdJ0bYsrOh3jaDBqYDjHcUM4PurlcgviHbs+oramgQWOTRjaAAyB8H431RWl72wcGEEoVZ3cPgIV3KqoodB3Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Ja9imMJ+; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Ja9imMJ+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1729611909; bh=fC0pCAo2XvTLTelwyvhpjGUBmtu099+nMxksrhgRHPU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ja9imMJ+elCRsbzxDyBlRoZnwAByzcNQmFMh2KAfgYZ9UGqb8kKDNWEw524a1XtC5 oInk7uRf9N1Iqwh3KwWkLtARtX//M5m64qAbkuzNtcZlrvEervIevbR5AYRsDGxEGX fV/M6RYNRXDugoGHGMu2mCH7ZYl2/WZwlyyDko2eD8/RalYq5l9nNuYznE9iFPVSLf AtSmiDSfhJoC3c2uKgb+kpK+Nx8kTqxM9KH61PJ6paom/n7LlMmqWjuqxt/yT+PIiO dOgpZvyHd/fWWs08mfOb0W35WUlY1TkYtaxN3ee4FtWSh68peq1niQXvZbVGUS7TEu HMm1raUMUBXIA== Received: from jupiter.universe (dyndsl-091-248-085-026.ewe-ip-backbone.de [91.248.85.26]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id B3E6217E3664; Tue, 22 Oct 2024 17:45:09 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 67A4B4800F4; Tue, 22 Oct 2024 17:45:09 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson , Mark Brown Cc: Liam Girdwood , Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 2/7] pmdomain: rockchip: cleanup mutex handling in rockchip_pd_power Date: Tue, 22 Oct 2024 17:41:47 +0200 Message-ID: <20241022154508.63563-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241022154508.63563-1-sebastian.reichel@collabora.com> References: <20241022154508.63563-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the cleanup infrastructure to handle the mutex, which slightly improve code readability for this function. Reviewed-by: Heiko Stuebner Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel Tested-by: Heiko Stuebner --- drivers/pmdomain/rockchip/pm-domains.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index cb0f93800138..a161ee13c633 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -574,13 +574,12 @@ static int rockchip_pd_power(struct rockchip_pm_domai= n *pd, bool power_on) struct rockchip_pmu *pmu =3D pd->pmu; int ret; =20 - mutex_lock(&pmu->mutex); + guard(mutex)(&pmu->mutex); =20 if (rockchip_pmu_domain_is_on(pd) !=3D power_on) { ret =3D clk_bulk_enable(pd->num_clks, pd->clks); if (ret < 0) { dev_err(pmu->dev, "failed to enable clocks\n"); - mutex_unlock(&pmu->mutex); return ret; } =20 @@ -606,7 +605,6 @@ static int rockchip_pd_power(struct rockchip_pm_domain = *pd, bool power_on) clk_bulk_disable(pd->num_clks, pd->clks); } =20 - mutex_unlock(&pmu->mutex); return 0; } =20 --=20 2.45.2 From nobody Tue Nov 26 01:59:04 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9669A13957E; Tue, 22 Oct 2024 15:45:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611913; cv=none; b=O7IAHRdTOaEIU+31C6X2IQl12NCtQuJ6ae0BkmBTibmpSpx9eQ4GlXUDC0thfEw/OnnkXF3eZVLRWotPpCfIuB8sA6kU0tHYFf7c15gsK4h3+vIfqdhO+FpXHWgKwvp3Ur8maIa/rMDDIWIaz8MQ/yM5h0UhOZ3frhS6+bOmFLI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611913; c=relaxed/simple; bh=NJ7R6moR13i/qYgT1UcSIwbcfv9v3Unc4ptYYcOTvR8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R4cyxVV1DwSwYjq81hal1Xuo6g3ECs4rFVL+bBx7y9F6LbX/uIfzbK1tRip64Q4tL4qq1f46+GVjWkqTitwVwJDG3v88agxGs4YWGdnV8YoxixdD8f0Ij1dFNkxPpkJphinb2OV+QJMI7nUqOY1/sSEwUoJXN3I2+q/ts6ZOEs8= ARC-Authentication-Results: i=1; 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Tue, 22 Oct 2024 17:45:09 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 69AF84800F6; Tue, 22 Oct 2024 17:45:09 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson , Mark Brown Cc: Liam Girdwood , Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 3/7] pmdomain: rockchip: forward rockchip_do_pmu_set_power_domain errors Date: Tue, 22 Oct 2024 17:41:48 +0200 Message-ID: <20241022154508.63563-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241022154508.63563-1-sebastian.reichel@collabora.com> References: <20241022154508.63563-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently rockchip_do_pmu_set_power_domain prints a warning if there have been errors turning on the power domain, but it does not return any errors and rockchip_pd_power() tries to continue setting up the QOS registers. This usually results in accessing unpowered registers, which triggers an SError and a full system hang. This improves the error handling by forwarding the error to avoid kernel panics. Reviewed-by: Heiko Stuebner Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel Tested-by: Heiko Stuebner --- drivers/pmdomain/rockchip/pm-domains.c | 34 +++++++++++++++++--------- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index a161ee13c633..8f440f2883db 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -533,16 +533,17 @@ static int rockchip_pmu_domain_mem_reset(struct rockc= hip_pm_domain *pd) return ret; } =20 -static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, - bool on) +static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, + bool on) { struct rockchip_pmu *pmu =3D pd->pmu; struct generic_pm_domain *genpd =3D &pd->genpd; u32 pd_pwr_offset =3D pd->info->pwr_offset; bool is_on, is_mem_on =3D false; + int ret; =20 if (pd->info->pwr_mask =3D=3D 0) - return; + return 0; =20 if (on && pd->info->mem_status_mask) is_mem_on =3D rockchip_pmu_domain_is_mem_on(pd); @@ -557,16 +558,21 @@ static void rockchip_do_pmu_set_power_domain(struct r= ockchip_pm_domain *pd, =20 wmb(); =20 - if (is_mem_on && rockchip_pmu_domain_mem_reset(pd)) - return; + if (is_mem_on) { + ret =3D rockchip_pmu_domain_mem_reset(pd); + if (ret) + return ret; + } =20 - if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, - is_on =3D=3D on, 0, 10000)) { - dev_err(pmu->dev, - "failed to set domain '%s', val=3D%d\n", - genpd->name, is_on); - return; + ret =3D readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, + is_on =3D=3D on, 0, 10000); + if (ret) { + dev_err(pmu->dev, "failed to set domain '%s' %s, val=3D%d\n", + genpd->name, on ? "on" : "off", is_on); + return ret; } + + return 0; } =20 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) @@ -592,7 +598,11 @@ static int rockchip_pd_power(struct rockchip_pm_domain= *pd, bool power_on) rockchip_pmu_set_idle_request(pd, true); } =20 - rockchip_do_pmu_set_power_domain(pd, power_on); + ret =3D rockchip_do_pmu_set_power_domain(pd, power_on); + if (ret < 0) { + clk_bulk_disable(pd->num_clks, pd->clks); + return ret; + } =20 if (power_on) { /* if powering up, leave idle mode */ --=20 2.45.2 From nobody Tue Nov 26 01:59:04 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF4B819DF52; Tue, 22 Oct 2024 15:45:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611914; cv=none; b=YMricFRUYoBe2snFDGL9O7xwuAfB4ieTCpY+DuaQZ3veswfdj2oUh3PkwP19qhzZTuolRWJ+Fvs9+BNY932ys91EA84hYLNQcPNinXJqkYhjnBk2OT3uGMsXhT/57jlS0iCXqMVUUKUePwGi4a+0604+GmGNZ/SZb6v91YI60xA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611914; c=relaxed/simple; bh=WdAfMwo/02oulaifUnF7xk8G7gAfYMpEJETO/isky1k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Orn8mJvklu3pCgMjlDsspEg8J6EDsFNYzCUKRuHT+qL42bSydeDsawOXZ6g2Xd1vc4dQwpXAw38JQox8qrrXvZJgLZpVonx4LmvQu47+23zBBBGiDvxAM44G7CQYtCT7yomHM4NcRFbFvcQAZlrEAmYjQ+jBBH11W5BYE+GecyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=V0ko+3o+; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="V0ko+3o+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1729611909; bh=WdAfMwo/02oulaifUnF7xk8G7gAfYMpEJETO/isky1k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V0ko+3o+VrZizinMoMFxC+tLwwaGgfWnMO0+MB1SWLm2JgEWq1U2rVcmCWHL+hffR q9lDRJYm6xymckEd1T03tCHoAqdm3EAXle/2h6hB7eA5qLnyoIMTLcr4nTY8IZzJ0S il3jrsB/4GqfFWVjq3PnacouZwMx0TcaPC74f8w2vlyuT04BU0xWbbqs3AqQb4lnj3 whv/Ue177H9Y4aCvdU+gW6BckqAhB3UXhjXHdqylhBPDYl6Ar6+3SebyUeforY/K8P 8+c71l0+/g49OIfjv2YVQuGn5GQ8VoBEy4xI94vSOcu91l1I1xoaCp+8qmn50OZ8qE qwo0M+phXHZLg== Received: from jupiter.universe (dyndsl-091-248-085-026.ewe-ip-backbone.de [91.248.85.26]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id B7C4717E367D; Tue, 22 Oct 2024 17:45:09 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 6B89F4800F8; Tue, 22 Oct 2024 17:45:09 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson , Mark Brown Cc: Liam Girdwood , Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 4/7] pmdomain: rockchip: reduce indentation in rockchip_pd_power Date: Tue, 22 Oct 2024 17:41:49 +0200 Message-ID: <20241022154508.63563-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241022154508.63563-1-sebastian.reichel@collabora.com> References: <20241022154508.63563-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rework the logic, so that the function exits early when the power domain state is already correct to reduce code indentation. No functional change intended. Reviewed-by: Heiko Stuebner Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel Tested-by: Heiko Stuebner --- drivers/pmdomain/rockchip/pm-domains.c | 49 +++++++++++++------------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index 8f440f2883db..f4e555dac20a 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -582,39 +582,40 @@ static int rockchip_pd_power(struct rockchip_pm_domai= n *pd, bool power_on) =20 guard(mutex)(&pmu->mutex); =20 - if (rockchip_pmu_domain_is_on(pd) !=3D power_on) { - ret =3D clk_bulk_enable(pd->num_clks, pd->clks); - if (ret < 0) { - dev_err(pmu->dev, "failed to enable clocks\n"); - return ret; - } + if (rockchip_pmu_domain_is_on(pd) =3D=3D power_on) + return 0; =20 - rockchip_pmu_ungate_clk(pd, true); + ret =3D clk_bulk_enable(pd->num_clks, pd->clks); + if (ret < 0) { + dev_err(pmu->dev, "failed to enable clocks\n"); + return ret; + } =20 - if (!power_on) { - rockchip_pmu_save_qos(pd); + rockchip_pmu_ungate_clk(pd, true); =20 - /* if powering down, idle request to NIU first */ - rockchip_pmu_set_idle_request(pd, true); - } + if (!power_on) { + rockchip_pmu_save_qos(pd); =20 - ret =3D rockchip_do_pmu_set_power_domain(pd, power_on); - if (ret < 0) { - clk_bulk_disable(pd->num_clks, pd->clks); - return ret; - } + /* if powering down, idle request to NIU first */ + rockchip_pmu_set_idle_request(pd, true); + } =20 - if (power_on) { - /* if powering up, leave idle mode */ - rockchip_pmu_set_idle_request(pd, false); + ret =3D rockchip_do_pmu_set_power_domain(pd, power_on); + if (ret < 0) { + clk_bulk_disable(pd->num_clks, pd->clks); + return ret; + } =20 - rockchip_pmu_restore_qos(pd); - } + if (power_on) { + /* if powering up, leave idle mode */ + rockchip_pmu_set_idle_request(pd, false); =20 - rockchip_pmu_ungate_clk(pd, false); - clk_bulk_disable(pd->num_clks, pd->clks); + rockchip_pmu_restore_qos(pd); } =20 + rockchip_pmu_ungate_clk(pd, false); + clk_bulk_disable(pd->num_clks, pd->clks); + return 0; } =20 --=20 2.45.2 From nobody Tue Nov 26 01:59:04 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15DBF1B5338; Tue, 22 Oct 2024 15:45:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611916; cv=none; b=SC4Qf2Kkh6CIUx2YjamIGaznVXfw1Z7w3VvmLuEEtALMcmF74aAJ0Dbo8Y6rviTWqpC123s+lhxGCU9IAgAtN/Vq/I/xSlX3J6UAq1C8Jm5hjnwNpePYhhyTBtS+tO06IAUozl29WezTzPQayRIgWYU8AvgsrKKNoU2rMk9CnRw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611916; c=relaxed/simple; bh=HylE764hFn4QR8Thq5VNJ1Y99OJHF7eCaB0kqVRf8sY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Tue, 22 Oct 2024 17:45:09 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 6D6D74800FE; Tue, 22 Oct 2024 17:45:09 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson , Mark Brown Cc: Liam Girdwood , Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 5/7] dt-bindings: power: rockchip: add regulator support Date: Tue, 22 Oct 2024 17:41:50 +0200 Message-ID: <20241022154508.63563-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241022154508.63563-1-sebastian.reichel@collabora.com> References: <20241022154508.63563-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add optional support for a voltage supply required to enable a power domain. The binding follows the way it is handled by the Mediatek binding to keep things consistent. This will initially be used by the RK3588 GPU power domain, which fails to be enabled when the GPU regulator is not enabled. It is not limited to that platform, since older generations have similar requirements. They worked around this by marking the regulators as always-on instead of describing the dependency. Reviewed-by: Heiko Stuebner Acked-by: Rob Herring (Arm) Signed-off-by: Sebastian Reichel Tested-by: Heiko Stuebner --- .../devicetree/bindings/power/rockchip,power-controller.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/power/rockchip,power-control= ler.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controlle= r.yaml index 650dc0aae6f5..ebab98987e49 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -132,6 +132,9 @@ $defs: A number of phandles to clocks that need to be enabled while power domain switches state. =20 + domain-supply: + description: domain regulator supply. + pm_qos: $ref: /schemas/types.yaml#/definitions/phandle-array items: --=20 2.45.2 From nobody Tue Nov 26 01:59:04 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15E131B533C; Tue, 22 Oct 2024 15:45:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611917; cv=none; b=n4/wEoywb7NRqG+Obi1r3aDHoT7+1GyyqTt0Q18xvI56qzdchqXtF8F40+QITt4YhcTu9hc8TxuTYp4rV6skaWjtlxlHOgQvDExxodXeAiLvfEjOrU57yJrifZNbK+2iunn0aP98xGrn32uARESivCmZyn7sDi1o4XfHqRnnLoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729611917; c=relaxed/simple; bh=rmzXK8UxDAuXQJ3fmM9evGH4u3ylpHhCeM0Wfp38sXQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bz9fXBgbkeIHwatISum/RWLsr7I9gPxbk8woqlnBAK+B0u/Rm18paj5jVM7xWb2+VGcFvx7r+1VI5upYJjvJ/NjXrDOZPVW54H1ROHWRkAVCLPks6PsIfR8SncgZ0rzy7Yrph6KkHgicqDpSnXY8H0q5auh+FzfjkPFZvMpahvA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=i25iP9rr; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="i25iP9rr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1729611910; bh=rmzXK8UxDAuXQJ3fmM9evGH4u3ylpHhCeM0Wfp38sXQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i25iP9rr68kK8d2pLHuK0J1dXtr199vPzczLM/g84FO/X3Dfe8U15R9jwzqEf9nxS aWyVQBEfMEXplFKb2gFNpyU2e1McP4anzhiKLcR2TnvIZRmaNw+LeiF3exgieiApo2 HjLltBxsukM/Fz82hY9SF6gKdEfKWHBUJ7y1tnYfQtqe9DxXlKOFuWI6LBthOsnxgx QQyQ35u2qdgclXp1ay5L2Z4t5PlBrjvwVell5HknYr+QLvUWG1HLfci7FiE3gcPt7F WkAaaO9U0qwT93B1PnmgNSjx0/l+hMHYzeJR6011O/+clwFc9qN53kH6PbxOdgyuTR niH239S0o5igg== Received: from jupiter.universe (dyndsl-091-248-085-026.ewe-ip-backbone.de [91.248.85.26]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id EE76A17E3683; Tue, 22 Oct 2024 17:45:09 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 6F9774800FF; Tue, 22 Oct 2024 17:45:09 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson , Mark Brown Cc: Liam Girdwood , Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 6/7] pmdomain: rockchip: add regulator support Date: Tue, 22 Oct 2024 17:41:51 +0200 Message-ID: <20241022154508.63563-7-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241022154508.63563-1-sebastian.reichel@collabora.com> References: <20241022154508.63563-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some power domains require extra voltages to be applied. For example trying to enable the GPU power domain on RK3588 fails when the SoC does not have VDD GPU enabled. The same is expected to happen for the NPU, which also has a dedicated supply line. We get the regulator using devm_of_regulator_get(), so a missing dependency in the devicetree is handled gracefully by printing a warning and creating a dummy regulator. This is necessary, since existing DTs do not have the regulator described. They might still work if the regulator is marked as always-on. It is also working if the regulator is enabled at boot time and the GPU driver is probed before the kernel disables unused regulators. The regulator itself is not acquired at driver probe time, since that creates an unsolvable circular dependency. The power domain driver must be probed early, since SoC peripherals need it. Regulators on the other hand depend on SoC peripherals like SPI, I2C or GPIO. MediaTek does not run into this, since they have two power domain drivers. Signed-off-by: Sebastian Reichel Tested-by: Heiko Stuebner --- drivers/pmdomain/rockchip/pm-domains.c | 113 +++++++++++++++++-------- 1 file changed, 79 insertions(+), 34 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index f4e555dac20a..31c71b6fddf1 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,7 @@ struct rockchip_domain_info { int idle_mask; int ack_mask; bool active_wakeup; + bool need_regulator; int pwr_w_mask; int req_w_mask; int clk_ungate_mask; @@ -92,6 +94,8 @@ struct rockchip_pm_domain { u32 *qos_save_regs[MAX_QOS_REGS_NUM]; int num_clks; struct clk_bulk_data *clks; + struct device_node *node; + struct regulator *supply; }; =20 struct rockchip_pmu { @@ -129,7 +133,7 @@ struct rockchip_pmu { .active_wakeup =3D wakeup, \ } =20 -#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_s= tatus, r_offset, req, idle, ack, wakeup) \ +#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_s= tatus, r_offset, req, idle, ack, wakeup, regulator) \ { \ .name =3D _name, \ .pwr_offset =3D p_offset, \ @@ -145,6 +149,7 @@ struct rockchip_pmu { .idle_mask =3D (idle), \ .ack_mask =3D (ack), \ .active_wakeup =3D wakeup, \ + .need_regulator =3D regulator, \ } =20 #define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r= _status, r_offset, req, idle, ack, g_mask, wakeup) \ @@ -303,8 +308,8 @@ void rockchip_pmu_unblock(void) } EXPORT_SYMBOL_GPL(rockchip_pmu_unblock); =20 -#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_s= tatus, r_offset, req, idle, wakeup) \ - DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r= _offset, req, idle, idle, wakeup) +#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_s= tatus, r_offset, req, idle, wakeup, regulator) \ + DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r= _offset, req, idle, idle, wakeup, regulator) =20 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { @@ -619,18 +624,57 @@ static int rockchip_pd_power(struct rockchip_pm_domai= n *pd, bool power_on) return 0; } =20 +static int rockchip_pd_regulator_disable(struct rockchip_pm_domain *pd) +{ + return IS_ERR_OR_NULL(pd->supply) ? 0 : regulator_disable(pd->supply); +} + +static int rockchip_pd_regulator_enable(struct rockchip_pm_domain *pd) +{ + struct rockchip_pmu *pmu =3D pd->pmu; + + if (!pd->info->need_regulator) + return 0; + + if (IS_ERR_OR_NULL(pd->supply)) { + pd->supply =3D devm_of_regulator_get(pmu->dev, pd->node, "domain"); + + if (IS_ERR(pd->supply)) + return PTR_ERR(pd->supply); + } + + return regulator_enable(pd->supply); +} + static int rockchip_pd_power_on(struct generic_pm_domain *domain) { struct rockchip_pm_domain *pd =3D to_rockchip_pd(domain); + int ret; + + ret =3D rockchip_pd_regulator_enable(pd); + if (ret) { + dev_err(pd->pmu->dev, "Failed to enable supply: %d\n", ret); + return ret; + } =20 - return rockchip_pd_power(pd, true); + ret =3D rockchip_pd_power(pd, true); + if (ret) + rockchip_pd_regulator_disable(pd); + + return ret; } =20 static int rockchip_pd_power_off(struct generic_pm_domain *domain) { struct rockchip_pm_domain *pd =3D to_rockchip_pd(domain); + int ret; =20 - return rockchip_pd_power(pd, false); + ret =3D rockchip_pd_power(pd, false); + if (ret) + return ret; + + rockchip_pd_regulator_disable(pd); + return ret; } =20 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd, @@ -711,6 +755,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_p= mu *pmu, =20 pd->info =3D pd_info; pd->pmu =3D pmu; + pd->node =3D node; =20 pd->num_clks =3D of_clk_get_parent_count(node); if (pd->num_clks > 0) { @@ -1174,35 +1219,35 @@ static const struct rockchip_domain_info rk3576_pm_= domains[] =3D { }; =20 static const struct rockchip_domain_info rk3588_pm_domains[] =3D { - [RK3588_PD_GPU] =3D DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0,= 0, BIT(1), 0x0, BIT(0), BIT(0), false), - [RK3588_PD_NPU] =3D DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0,= 0, 0, 0x0, 0, 0, false), - [RK3588_PD_VCODEC] =3D DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x= 0, 0, 0, 0x0, 0, 0, false), - [RK3588_PD_NPUTOP] =3D DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x= 0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false), - [RK3588_PD_NPU1] =3D DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0,= BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false), - [RK3588_PD_NPU2] =3D DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0,= BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false), - [RK3588_PD_VENC0] =3D DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0= , BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false), - [RK3588_PD_VENC1] =3D DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0= , BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false), - [RK3588_PD_RKVDEC0] =3D DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0= x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false), - [RK3588_PD_RKVDEC1] =3D DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0= x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false), - [RK3588_PD_VDPU] =3D DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0,= BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false), - [RK3588_PD_RGA30] =3D DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0= , BIT(19), BIT(10), 0x0, 0, 0, false), - [RK3588_PD_AV1] =3D DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0,= BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false), - [RK3588_PD_VI] =3D DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, = BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false), - [RK3588_PD_FEC] =3D DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0,= BIT(22), BIT(13), 0x0, 0, 0, false), - [RK3588_PD_ISP1] =3D DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0,= BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false), - [RK3588_PD_RGA31] =3D DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0= , BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false), - [RK3588_PD_VOP] =3D DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0,= BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false), - [RK3588_PD_VO0] =3D DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0,= BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false), - [RK3588_PD_VO1] =3D DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0,= BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false), - [RK3588_PD_AUDIO] =3D DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0= , BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false), - [RK3588_PD_PHP] =3D DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0,= BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false), - [RK3588_PD_GMAC] =3D DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0,= BIT(30), BIT(21), 0x0, 0, 0, false), - [RK3588_PD_PCIE] =3D DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0,= BIT(31), BIT(22), 0x0, 0, 0, true), - [RK3588_PD_NVM] =3D DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4,= 0, 0, 0x4, BIT(2), BIT(18), false), - [RK3588_PD_NVM0] =3D DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4,= BIT(1), BIT(23), 0x0, 0, 0, false), - [RK3588_PD_SDIO] =3D DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4,= BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false), - [RK3588_PD_USB] =3D DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4,= BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true), - [RK3588_PD_SDMMC] =3D DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4= , BIT(5), BIT(26), 0x0, 0, 0, false), + [RK3588_PD_GPU] =3D DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0,= 0, BIT(1), 0x0, BIT(0), BIT(0), false, true), + [RK3588_PD_NPU] =3D DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0,= 0, 0, 0x0, 0, 0, false, true), + [RK3588_PD_VCODEC] =3D DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x= 0, 0, 0, 0x0, 0, 0, false, false), + [RK3588_PD_NPUTOP] =3D DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x= 0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false), + [RK3588_PD_NPU1] =3D DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0,= BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false), + [RK3588_PD_NPU2] =3D DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0,= BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false), + [RK3588_PD_VENC0] =3D DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0= , BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false), + [RK3588_PD_VENC1] =3D DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0= , BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false), + [RK3588_PD_RKVDEC0] =3D DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0= x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false), + [RK3588_PD_RKVDEC1] =3D DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0= x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false, false), + [RK3588_PD_VDPU] =3D DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0,= BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false, false), + [RK3588_PD_RGA30] =3D DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0= , BIT(19), BIT(10), 0x0, 0, 0, false, false), + [RK3588_PD_AV1] =3D DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0,= BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false, false), + [RK3588_PD_VI] =3D DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, = BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false, false), + [RK3588_PD_FEC] =3D DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0,= BIT(22), BIT(13), 0x0, 0, 0, false, false), + [RK3588_PD_ISP1] =3D DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0,= BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false, false), + [RK3588_PD_RGA31] =3D DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0= , BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false, false), + [RK3588_PD_VOP] =3D DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0,= BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false, false), + [RK3588_PD_VO0] =3D DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0,= BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false, false), + [RK3588_PD_VO1] =3D DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0,= BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false, false), + [RK3588_PD_AUDIO] =3D DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0= , BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false, false), + [RK3588_PD_PHP] =3D DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0,= BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false, false), + [RK3588_PD_GMAC] =3D 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linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 7/7] arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588 Date: Tue, 22 Oct 2024 17:41:52 +0200 Message-ID: <20241022154508.63563-8-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241022154508.63563-1-sebastian.reichel@collabora.com> References: <20241022154508.63563-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Enabling the GPU power domain requires that the GPU regulator is enabled. The regulator is enabled at boot time, but automatically gets disabled when there are no users. If the GPU driver is not probed at boot time or rebound while the system is running the system will try to enable the power domain before the regulator is enabled resulting in a failure hanging the whole system. Avoid this by adding an explicit dependency. Reported-by: Adri=C3=A1n Mart=C3=ADnez Larumbe Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel Tested-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++ 25 files changed, 97 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/ar= m64/boot/dts/rockchip/rk3588-armsom-sige7.dts index c667704ba985..00a1cd96781d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -286,6 +286,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 811b15064851..a6b2855cda94 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -861,7 +861,7 @@ power-domain@RK3588_PD_NPU2 { }; }; /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { + pd_gpu: power-domain@RK3588_PD_GPU { reg =3D ; clocks =3D <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi index fde8b228f2c7..cf9d75159ba6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi @@ -277,6 +277,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi = b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi index 03fd193be253..381242c8d6db 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -126,6 +126,10 @@ regulator-state-mem { }; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_user_en: led_user_en { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3588-evb1-v10.dts index 7dc3ee6e7eb4..142e685ae513 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -485,6 +485,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi b/arch/arm6= 4/boot/dts/rockchip/rk3588-fet3588-c.dtsi index 47e64d547ea9..799a71da7157 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi @@ -205,6 +205,10 @@ regulator-state-mem { }; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_rgb_b: led-rgb-b { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b= /arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi index e3a9598b99fc..1af0a30866f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -256,6 +256,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { led_sys_pin: led-sys-pin { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/bo= ot/dts/rockchip/rk3588-jaguar.dts index 31d2f8994f85..3cefaf830229 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -403,6 +403,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm6= 4/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index fc131789b4c3..30a5e4e9e844 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -519,6 +519,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { sys_led_pin: sys-led-pin { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/= boot/dts/rockchip/rk3588-ok3588-c.dts index c2a08bdf09e8..a9c1fed929fd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -312,6 +312,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { pcie2 { pcie2_0_rst: pcie2-0-rst { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch= /arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts index c3a6812cc93a..62863b6b1c88 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -389,6 +389,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm= 64/boot/dts/rockchip/rk3588-quartzpro64.dts index e4a20cda65ed..c8efe60e93ca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -348,6 +348,10 @@ rgmii_phy: ethernet-phy@1 { }; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm6= 4/boot/dts/rockchip/rk3588-rock-5-itx.dts index d0b922b8d67e..0eadf4fb4ba4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -530,6 +530,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { rtc_int: rtc-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts index 8f7a59918db7..717504383d46 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -465,6 +465,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hdmirx { hdmirx_hpd: hdmirx-5v-detection { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-tiger.dtsi index 615094bb8ba3..1b5c4a7fd5c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -317,6 +317,10 @@ &pcie3x4 { reset-gpios =3D <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm= 64/boot/dts/rockchip/rk3588-toybrick-x0.dts index d0021524e7f9..69aadc6c8b74 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts @@ -289,6 +289,10 @@ rgmii_phy: ethernet-phy@1 { }; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { rtl8211f { rtl8211f_rst: rtl8211f-rst { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index dbaa94ca69f4..83fc7ff55157 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -229,6 +229,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { fan { fan_int: fan-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm6= 4/boot/dts/rockchip/rk3588s-coolpi-4b.dts index 074c316a9a69..d938db0e2239 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -329,6 +329,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/= arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index 467f69594089..9b02cea96cdb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -675,6 +675,10 @@ &pcie2x1l1 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { audio-amplifier { headphone_amplifier_en: headphone-amplifier-en { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arc= h/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts index d8c50fdcca3b..1126fb442516 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -416,6 +416,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { bluetooth-pins { bt_reset: bt-reset { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/a= rm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index dbddfc3bb464..d29d404417ee 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -233,6 +233,10 @@ hym8563: rtc@51 { }; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { vdd_sd { vdd_sd_en: vdd-sd-en { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts b/arch/arm= 64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts index 4fa644ae510c..3dd8372b2578 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts @@ -326,6 +326,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { gpio-key { key1_pin: key1-pin { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts b/arch/arm6= 4/boot/dts/rockchip/rk3588s-odroid-m2.dts index 63d91236ba9f..5f32a339f5c9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts @@ -401,6 +401,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { lcd { lcd_pwren: lcd-pwren { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm= 64/boot/dts/rockchip/rk3588s-orangepi-5.dts index feea6b20a6bf..ef3a721d1fc7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -297,6 +297,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { gpio-func { leds_gpio: leds-gpio { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/= boot/dts/rockchip/rk3588s-rock-5a.dts index 294b99dd50da..a61864482f1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -317,6 +317,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { leds { io_led: io-led { --=20 2.45.2