From nobody Tue Nov 26 03:36:28 2024 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6F5612D1F1 for ; Tue, 22 Oct 2024 12:47:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729601225; cv=none; b=d9Djcf+FuvDDSfnH8G8BqkUYC9Qto6s4arY6geTtl9rRIqoaIH8DElFmet/w/OguMmXknnBU07pOTm9e07rr7iJ/6JtFGOHlp1JqSDaGRg7kMilwtkvjOD7sxsHJScp2Epaa7CSXGF2nwbjTRtvm7+DBGKhHKnYuuKCwMcxhkkE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729601225; c=relaxed/simple; bh=WDg3Yo+ZOX5lpTVXiVuPrqjfsgu1gYhePxMsWfY/j/k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jIL3Pn9D8oQO4S/Y5LMurBNrwu5QNQkGJwYxzq2rOSO7e5UsPNVLs/curP6zRplEvKHskT51Va/5XoFlEKT0Hz9EPhwfTozB36CCEaIkCThkyHkNvI9RWszGNpdRHi7OSlwKglAtWuo8UyyO5F5/yKaQcjUcay85vAvWZC++d9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.174]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4XXsM11nWXzfdM9; Tue, 22 Oct 2024 20:44:29 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id 271C514022E; Tue, 22 Oct 2024 20:46:59 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Tue, 22 Oct 2024 20:46:57 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 drm-dp 1/4] drm/hisilicon/hibmc: add dp aux in hibmc Date: Tue, 22 Oct 2024 20:41:45 +0800 Message-ID: <20241022124148.1952761-2-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20241022124148.1952761-1-shiyongbang@huawei.com> References: <20241022124148.1952761-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: baihan li Add dp aux read/write functions. They are basic functions and will be used later. Signed-off-by: baihan li --- ChangeLog: v1 -> v2: - using drm_dp_aux frame implement dp aux read and write functions, sugge= sted by Jani Nikula. - using drm dp header files' dp macros instead, suggested by Andy Yan. v1:https://lore.kernel.org/all/20240930100610.782363-1-shiyongbang@huawei= .com/ --- drivers/gpu/drm/hisilicon/hibmc/Makefile | 3 +- drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c | 162 +++++++++++++++++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.h | 31 ++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h | 74 +++++++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h | 76 +++++++++ 5 files changed, 345 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.h create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h diff --git a/drivers/gpu/drm/hisilicon/hibmc/Makefile b/drivers/gpu/drm/his= ilicon/hibmc/Makefile index d25c75e60d3d..8770ec6dfffd 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/Makefile +++ b/drivers/gpu/drm/hisilicon/hibmc/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -hibmc-drm-y :=3D hibmc_drm_drv.o hibmc_drm_de.o hibmc_drm_vdac.o hibmc_drm= _i2c.o +hibmc-drm-y :=3D hibmc_drm_drv.o hibmc_drm_de.o hibmc_drm_vdac.o hibmc_drm= _i2c.o \ + dp/dp_aux.o =20 obj-$(CONFIG_DRM_HISI_HIBMC) +=3D hibmc-drm.o diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c b/drivers/gpu/drm/= hisilicon/hibmc/dp/dp_aux.c new file mode 100644 index 000000000000..0078cafdf86d --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include +#include +#include +#include +#include "dp_comm.h" +#include "dp_reg.h" +#include "dp_aux.h" + +#define DP_MIN_PULSE_NUM 0x9 + +static void dp_aux_reset(const struct dp_dev *dp) +{ + dp_write_bits(dp->base + DP_DPTX_RST_CTRL, DP_CFG_AUX_RST_N, 0x0); + usleep_range(10, 15); + dp_write_bits(dp->base + DP_DPTX_RST_CTRL, DP_CFG_AUX_RST_N, 0x1); +} + +static void dp_aux_read_data(struct dp_dev *dp, u8 *buf, u8 size) +{ + u32 reg_num; + u32 value; + u32 num; + u8 i, j; + + reg_num =3D round_up(size, AUX_4_BYTE) / AUX_4_BYTE; + for (i =3D 0; i < reg_num; i++) { + /* number of bytes read from a single register */ + num =3D min(size - i * AUX_4_BYTE, AUX_4_BYTE); + value =3D readl(dp->base + DP_AUX_RD_DATA0 + i * AUX_4_BYTE); + /* convert the 32-bit value of the register to the buffer. */ + for (j =3D 0; j < num; j++) + buf[i * AUX_4_BYTE + j] =3D value >> (j * AUX_8_BIT); + } +} + +static void dp_aux_write_data(struct dp_dev *dp, u8 *buf, u8 size) +{ + u32 reg_num; + u32 value; + u8 i, j; + u32 num; + + reg_num =3D round_up(size, AUX_4_BYTE) / AUX_4_BYTE; + for (i =3D 0; i < reg_num; i++) { + /* number of bytes written to a single register */ + num =3D min_t(u8, size - i * AUX_4_BYTE, AUX_4_BYTE); + value =3D 0; + /* obtain the 32-bit value written to a single register. */ + for (j =3D 0; j < num; j++) + value |=3D buf[i * AUX_4_BYTE + j] << (j * AUX_8_BIT); + /* writing data to a single register */ + writel(value, dp->base + DP_AUX_WR_DATA0 + i * AUX_4_BYTE); + } +} + +static u32 dp_aux_build_cmd(const struct drm_dp_aux_msg *msg) +{ + u32 aux_cmd =3D msg->request; + + if (msg->size) + aux_cmd |=3D (msg->size - 1) << AUX_CMD_REQ_LEN_S; + else + aux_cmd |=3D 1 << AUX_CMD_I2C_ADDR_ONLY_S; + + aux_cmd |=3D msg->address << AUX_CMD_ADDR_S; + + return aux_cmd; +} + +/* ret >=3D 0 ,ret is size; ret < 0, ret is err code */ +static int dp_aux_parse_xfer(struct dp_dev *dp, struct drm_dp_aux_msg *msg) +{ + u32 buf_data_cnt; + u32 aux_status; + int ret =3D 0; + + aux_status =3D readl(dp->base + DP_AUX_STATUS); + msg->reply =3D FIELD_GET(DP_CFG_AUX_STATUS, aux_status); + + if (aux_status & DP_CFG_AUX_TIMEOUT) + return -ETIMEDOUT; + + /* only address */ + if (!msg->size) + return 0; + + if (msg->reply !=3D DP_AUX_NATIVE_REPLY_ACK) + return 0; + + buf_data_cnt =3D FIELD_GET(DP_CFG_AUX_READY_DATA_BYTE, aux_status); + + switch (msg->request) { + case DP_AUX_NATIVE_WRITE: + ret =3D msg->size; + break; + case DP_AUX_I2C_WRITE | DP_AUX_I2C_MOT: + if (buf_data_cnt =3D=3D AUX_I2C_WRITE_SUCCESS) + ret =3D msg->size; + else if (buf_data_cnt =3D=3D AUX_I2C_WRITE_PARTIAL_SUCCESS) + ret =3D FIELD_GET(DP_CFG_AUX, aux_status); + break; + case DP_AUX_NATIVE_READ: + case DP_AUX_I2C_READ | DP_AUX_I2C_MOT: + buf_data_cnt--; + /* only the successful part of data is read */ + if (buf_data_cnt !=3D msg->size) { + ret =3D -EBUSY; + } else { /* all data is successfully read */ + dp_aux_read_data(dp, msg->buffer, msg->size); + ret =3D msg->size; + } + break; + default: + return -EINVAL; + } + + return ret; +} + +/* ret >=3D 0 ,ret is size; ret < 0, ret is err code */ +static ssize_t dp_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *= msg) +{ + struct dp_dev *dp =3D container_of(aux, struct dp_dev, aux); + u32 aux_cmd; + int ret; + u32 val; /* val will be assigned at the beginning of readl_poll_timeout f= unction */ + + writel(0, dp->base + DP_AUX_WR_DATA0); + writel(0, dp->base + DP_AUX_WR_DATA1); + writel(0, dp->base + DP_AUX_WR_DATA2); + writel(0, dp->base + DP_AUX_WR_DATA3); + + dp_aux_write_data(dp, msg->buffer, msg->size); + + aux_cmd =3D dp_aux_build_cmd(msg); + writel(aux_cmd, dp->base + DP_AUX_CMD_ADDR); + + /* enable aux transfer */ + dp_write_bits(dp->base + DP_AUX_REQ, DP_CFG_AUX_REQ, 0x1); + ret =3D readl_poll_timeout(dp->base + DP_AUX_REQ, val, !(val & DP_CFG_AUX= _REQ), 50, 5000); + if (ret) { + dp_aux_reset(dp); + return ret; + } + + return dp_aux_parse_xfer(dp, msg); +} + +void dp_aux_init(struct dp_dev *dp) +{ + dp_write_bits(dp->base + DP_AUX_REQ, DP_CFG_AUX_SYNC_LEN_SEL, 0x0); + dp_write_bits(dp->base + DP_AUX_REQ, DP_CFG_AUX_TIMER_TIMEOUT, 0x1); + dp_write_bits(dp->base + DP_AUX_REQ, DP_CFG_AUX_MIN_PULSE_NUM, DP_MIN_PUL= SE_NUM); + + dp->aux.transfer =3D dp_aux_xfer; + dp->aux.is_remote =3D 0; + drm_dp_aux_init(&dp->aux); +} diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.h b/drivers/gpu/drm/= hisilicon/hibmc/dp/dp_aux.h new file mode 100644 index 000000000000..6f95a3750d60 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef DP_AUX_H +#define DP_AUX_H + +#include +#include "dp_comm.h" + +#define AUX_I2C_WRITE_SUCCESS 0x1 +#define AUX_I2C_WRITE_PARTIAL_SUCCESS 0x2 + +#define EQ_MAX_RETRY 5 + +#define DP_CFG_AUX_S 17 +#define DP_CFG_AUX_STATUS_S 4 + +#define AUX_4_BYTE 4 +#define AUX_4_BIT 4 +#define AUX_8_BIT 8 + +#define AUX_READY_DATA_BYTE_S 12 + +/* aux_cmd_addr register shift */ +#define AUX_CMD_REQ_LEN_S 4 +#define AUX_CMD_ADDR_S 8 +#define AUX_CMD_I2C_ADDR_ONLY_S 28 + +void dp_aux_init(struct dp_dev *dp); + +#endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_comm.h new file mode 100644 index 000000000000..26d97929dc06 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef DP_COMM_H +#define DP_COMM_H + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define REG_LENGTH 32 + +static inline u32 dp_read_bits(void __iomem *addr, u32 bit_mask) +{ + u32 reg_val; + + reg_val =3D readl(addr); + + return (reg_val & bit_mask) >> __ffs(bit_mask); +} + +static inline void dp_write_bits(void __iomem *addr, u32 bit_mask, u32 val) +{ + u32 reg_val; + + reg_val =3D readl(addr); + reg_val &=3D ~bit_mask; + reg_val |=3D (val << __ffs(bit_mask)) & bit_mask; + writel(reg_val, addr); +} + +enum dpcd_revision { + DPCD_REVISION_10 =3D 0x10, + DPCD_REVISION_11, + DPCD_REVISION_12, + DPCD_REVISION_13, + DPCD_REVISION_14, +}; + +struct link_status { + bool clock_recovered; + bool channel_equalized; + u8 cr_done_lanes; +}; + +struct link_cap { + enum dpcd_revision rx_dpcd_revision; + u8 link_rate; + u8 lanes; + bool is_tps3; + bool is_tps4; +}; + +struct hibmc_dp_link { + struct link_status status; + u8 *train_set; + struct link_cap cap; +}; + +struct dp_dev { + struct hibmc_dp_link link; + struct drm_dp_aux aux; + struct drm_device *dev; + void __iomem *base; + u8 dpcd[DP_RECEIVER_CAP_SIZE]; +}; + +#endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h b/drivers/gpu/drm/= hisilicon/hibmc/dp/dp_reg.h new file mode 100644 index 000000000000..3dcb847057a4 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef DP_REG_H +#define DP_REG_H + +#define DP_AUX_CMD_ADDR 0x50 +#define DP_AUX_WR_DATA0 0x54 +#define DP_AUX_WR_DATA1 0x58 +#define DP_AUX_WR_DATA2 0x5c +#define DP_AUX_WR_DATA3 0x60 +#define DP_AUX_RD_DATA0 0x64 +#define DP_AUX_REQ 0x74 +#define DP_AUX_STATUS 0x78 +#define DP_PHYIF_CTRL0 0xa0 +#define DP_VIDEO_CTRL 0x100 +#define DP_VIDEO_CONFIG0 0x104 +#define DP_VIDEO_CONFIG1 0x108 +#define DP_VIDEO_CONFIG2 0x10c +#define DP_VIDEO_CONFIG3 0x110 +#define DP_VIDEO_PACKET 0x114 +#define DP_VIDEO_MSA0 0x118 +#define DP_VIDEO_MSA1 0x11c +#define DP_VIDEO_MSA2 0x120 +#define DP_VIDEO_HORIZONTAL_SIZE 0X124 +#define DP_TIMING_GEN_CONFIG0 0x26c +#define DP_TIMING_GEN_CONFIG2 0x274 +#define DP_TIMING_GEN_CONFIG3 0x278 +#define DP_HDCP_CFG 0x600 +#define DP_INTR_ENABLE 0x720 +#define DP_INTR_ORIGINAL_STATUS 0x728 +#define DP_DPTX_RST_CTRL 0x700 +#define DP_DPTX_CLK_CTRL 0x704 +#define DP_DPTX_GCTL0 0x708 +#define DP_TIMING_MODEL_CTRL 0x884 +#define DP_TIMING_SYNC_CTRL 0xFF0 + +#define DP_CFG_AUX_SYNC_LEN_SEL BIT(1) +#define DP_CFG_AUX_TIMER_TIMEOUT BIT(2) +#define DP_CFG_STREAM_FRAME_MODE BIT(6) +#define DP_CFG_AUX_MIN_PULSE_NUM GENMASK(13, 9) +#define DP_CFG_LANE_DATA_EN GENMASK(11, 8) +#define DP_CFG_PHY_LANE_NUM GENMASK(2, 1) +#define DP_CFG_AUX_REQ BIT(0) +#define DP_CFG_AUX_RST_N BIT(4) +#define DP_CFG_AUX_TIMEOUT BIT(0) +#define DP_CFG_AUX_READY_DATA_BYTE GENMASK(16, 12) +#define DP_CFG_AUX GENMASK(24, 17) +#define DP_CFG_AUX_STATUS GENMASK(11, 4) +#define DP_CFG_SCRAMBLE_EN BIT(0) +#define DP_CFG_PAT_SEL GENMASK(7, 4) +#define DP_CFG_TIMING_GEN0_HACTIVE GENMASK(31, 16) +#define DP_CFG_TIMING_GEN0_HBLANK GENMASK(15, 0) +#define DP_CFG_TIMING_GEN0_VACTIVE GENMASK(31, 16) +#define DP_CFG_TIMING_GEN0_VBLANK GENMASK(15, 0) +#define DP_CFG_TIMING_GEN0_VFRONT_PORCH GENMASK(31, 16) +#define DP_CFG_STREAM_HACTIVE GENMASK(31, 16) +#define DP_CFG_STREAM_HBLANK GENMASK(15, 0) +#define DP_CFG_STREAM_HSYNC_WIDTH GENMASK(15, 0) +#define DP_CFG_STREAM_VACTIVE GENMASK(31, 16) +#define DP_CFG_STREAM_VBLANK GENMASK(15, 0) +#define DP_CFG_STREAM_VFRONT_PORCH GENMASK(31, 16) +#define DP_CFG_STREAM_VSYNC_WIDTH GENMASK(15, 0) +#define DP_CFG_STREAM_VSTART GENMASK(31, 16) +#define DP_CFG_STREAM_HSTART GENMASK(15, 0) +#define DP_CFG_STREAM_VSYNC_POLARITY BIT(8) +#define DP_CFG_STREAM_HSYNC_POLARITY BIT(7) +#define DP_CFG_STREAM_RGB_ENABLE BIT(1) +#define DP_CFG_STREAM_VIDEO_MAPPING GENMASK(5, 2) +#define DP_CFG_PIXEL_NUM_TIMING_MODE_SEL1 GENMASK(31, 16) +#define DP_CFG_STREAM_TU_SYMBOL_SIZE GENMASK(5, 0) +#define DP_CFG_STREAM_TU_SYMBOL_FRAC_SIZE GENMASK(9, 6) +#define DP_CFG_STREAM_HTOTAL_SIZE GENMASK(31, 16) +#define DP_CFG_STREAM_HBLANK_SIZE GENMASK(15, 0) + +#endif --=20 2.33.0 From nobody Tue Nov 26 03:36:28 2024 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDA6C19C579 for ; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4XXsJw2bl7z1HLKC; Tue, 22 Oct 2024 20:42:40 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id 4B65B140361; Tue, 22 Oct 2024 20:47:00 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Tue, 22 Oct 2024 20:46:58 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 drm-dp 2/4] drm/hisilicon/hibmc: add dp link moduel in hibmc Date: Tue, 22 Oct 2024 20:41:46 +0800 Message-ID: <20241022124148.1952761-3-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20241022124148.1952761-1-shiyongbang@huawei.com> References: <20241022124148.1952761-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: baihan li Add link training process functions in this moduel. Signed-off-by: baihan li --- ChangeLog: v1 -> v2: - using drm_dp_* functions implement dp link training process, suggested = by Jani Nikula. - fix build errors reported by kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202410031735.8iRZZR6T-lkp= @intel.com/ v1:https://lore.kernel.org/all/20240930100610.782363-1-shiyongbang@huawei= .com/ --- drivers/gpu/drm/hisilicon/hibmc/Makefile | 2 +- drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c | 344 +++++++++++++++++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.h | 25 ++ 3 files changed, 370 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.h diff --git a/drivers/gpu/drm/hisilicon/hibmc/Makefile b/drivers/gpu/drm/his= ilicon/hibmc/Makefile index 8770ec6dfffd..94d77da88bbf 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/Makefile +++ b/drivers/gpu/drm/hisilicon/hibmc/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only hibmc-drm-y :=3D hibmc_drm_drv.o hibmc_drm_de.o hibmc_drm_vdac.o hibmc_drm= _i2c.o \ - dp/dp_aux.o + dp/dp_aux.o dp/dp_link.o =20 obj-$(CONFIG_DRM_HISI_HIBMC) +=3D hibmc-drm.o diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_link.c new file mode 100644 index 000000000000..b02a536e0689 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include +#include +#include "dp_comm.h" +#include "dp_reg.h" +#include "dp_link.h" +#include "dp_aux.h" + +const u8 link_rate_map[] =3D {DP_LINK_BW_1_62, DP_LINK_BW_2_7, + DP_LINK_BW_5_4, DP_LINK_BW_8_1}; + +static int dp_link_training_configure(struct dp_dev *dp) +{ + u8 buf[2]; + int ret; + + /* DP 2 lane */ + dp_write_bits(dp->base + DP_PHYIF_CTRL0, DP_CFG_LANE_DATA_EN, + dp->link.cap.lanes =3D=3D DP_LANE_NUM_2 ? 0x3 : 0x1); + dp_write_bits(dp->base + DP_DPTX_GCTL0, DP_CFG_PHY_LANE_NUM, + dp->link.cap.lanes =3D=3D DP_LANE_NUM_2 ? 0x1 : 0); + + /* enhanced frame */ + dp_write_bits(dp->base + DP_VIDEO_CTRL, DP_CFG_STREAM_FRAME_MODE, 0x1); + + /* set rate and lane count */ + buf[0] =3D dp_get_link_rate(dp->link.cap.link_rate); + buf[1] =3D DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; + ret =3D drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); + if (ret !=3D sizeof(buf)) { + drm_err(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", r= et); + return ret; + } + + /* set 8b/10b and downspread */ + buf[0] =3D 0x10; + buf[1] =3D 0x1; + ret =3D drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf)); + if (ret !=3D sizeof(buf)) + drm_err(dp->dev, "dp aux write 8b/10b and downspread failed, ret: %d\n",= ret); + + ret =3D drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd); + if (ret) + drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret); + + return ret; +} + +static int dp_link_pattern2dpcd(struct dp_dev *dp, enum dp_pattern_e patte= rn) +{ + switch (pattern) { + case DP_PATTERN_NO: + return DP_TRAINING_PATTERN_DISABLE; + case DP_PATTERN_TPS1: + return DP_TRAINING_PATTERN_1; + case DP_PATTERN_TPS2: + return DP_TRAINING_PATTERN_2; + case DP_PATTERN_TPS3: + return DP_TRAINING_PATTERN_3; + case DP_PATTERN_TPS4: + return DP_TRAINING_PATTERN_4; + default: + drm_err(dp->dev, "dp link unknown pattern %d\n", pattern); + return -EINVAL; + } +} + +static int dp_link_set_pattern(struct dp_dev *dp, enum dp_pattern_e patter= n) +{ + int ret; + u8 buf; + + ret =3D dp_link_pattern2dpcd(dp, pattern); + if (ret < 0) + return ret; + + buf =3D (u8)ret; + if (pattern !=3D DP_TRAINING_PATTERN_DISABLE && pattern !=3D DP_TRAINING_= PATTERN_4) { + buf |=3D DP_LINK_SCRAMBLING_DISABLE; + dp_write_bits(dp->base + DP_PHYIF_CTRL0, DP_CFG_SCRAMBLE_EN, 0x1); + } else { + dp_write_bits(dp->base + DP_PHYIF_CTRL0, DP_CFG_SCRAMBLE_EN, 0); + } + + dp_write_bits(dp->base + DP_PHYIF_CTRL0, DP_CFG_PAT_SEL, pattern); + + ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET, &buf, sizeof= (buf)); + if (ret !=3D sizeof(buf)) + drm_err(dp->dev, "dp aux write training pattern set failed\n"); + + return 0; +} + +static int dp_link_training_cr_pre(struct dp_dev *dp) +{ + u8 *train_set =3D dp->link.train_set; + int ret; + u8 i; + + ret =3D dp_link_training_configure(dp); + if (ret) + return ret; + + ret =3D dp_link_set_pattern(dp, DP_PATTERN_TPS1); + if (ret) + return ret; + + for (i =3D 0; i < dp->link.cap.lanes; i++) + train_set[i] =3D DP_TRAIN_VOLTAGE_SWING_LEVEL_2; + + ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, dp-= >link.cap.lanes); + if (ret !=3D dp->link.cap.lanes) + drm_err(dp->dev, "dp aux write training lane set failed\n"); + + return 0; +} + +static bool dp_link_get_adjust_train(struct dp_dev *dp, u8 lane_status[DP_= LINK_STATUS_SIZE]) +{ + u8 pre_emph[DP_LANE_NUM_MAX] =3D {0}; + u8 voltage[DP_LANE_NUM_MAX] =3D {0}; + bool changed =3D false; + u8 train_set; + u8 lane; + + /* not support level 3 */ + for (lane =3D 0; lane < dp->link.cap.lanes; lane++) { + voltage[lane] =3D drm_dp_get_adjust_request_voltage(lane_status, lane); + pre_emph[lane] =3D drm_dp_get_adjust_request_pre_emphasis(lane_status, l= ane); + } + + for (lane =3D 0; lane < dp->link.cap.lanes; lane++) { + train_set =3D voltage[lane] | pre_emph[lane]; + if (dp->link.train_set[lane] !=3D train_set) { + changed =3D true; + dp->link.train_set[lane] =3D train_set; + } + } + + return changed; +} + +u8 dp_get_link_rate(u8 index) +{ + return link_rate_map[index]; +} + +static int dp_link_reduce_rate(struct dp_dev *dp) +{ + if (dp->link.cap.link_rate > 0) { + dp->link.cap.link_rate--; + return 0; + } + + drm_err(dp->dev, "dp link training reduce rate failed, already lowest rat= e\n"); + + return -EFAULT; +} + +static int dp_link_reduce_lane(struct dp_dev *dp) +{ + if (dp->link.cap.lanes =3D=3D DP_LANE_NUM_1) { + drm_err(dp->dev, "dp link training reduce lane failed, already reach min= imum\n"); + return -EFAULT; + } + + /* currently only 1 lane */ + dp->link.cap.lanes =3D DP_LANE_NUM_1; + + return 0; +} + +static int dp_link_training_cr(struct dp_dev *dp) +{ + u8 lane_status[DP_LINK_STATUS_SIZE] =3D {0}; + bool level_changed; + u32 voltage_tries; + u32 cr_tries; + u32 max_cr; + int ret; + + /* + * DP 1.4 spec define 10 for maxtries value, for pre DP 1.4 version set a= limit of 80 + * (4 voltage levels x 4 preemphasis levels x 5 identical voltage retries) + */ + max_cr =3D dp->link.cap.rx_dpcd_revision >=3D DPCD_REVISION_14 ? 10 : 80; + + voltage_tries =3D 1; + for (cr_tries =3D 0; cr_tries < max_cr; cr_tries++) { + drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); + + ret =3D drm_dp_dpcd_read_link_status(&dp->aux, lane_status); + if (ret !=3D DP_LINK_STATUS_SIZE) { + drm_err(dp->dev, "Get lane status failed\n"); + return ret; + } + + if (drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) { + drm_info(dp->dev, "dp link training cr done\n"); + dp->link.status.clock_recovered =3D true; + return 0; + } + + if (voltage_tries =3D=3D 5) { + drm_info(dp->dev, "same voltage tries 5 times\n"); + dp->link.status.clock_recovered =3D false; + return 0; + } + + level_changed =3D dp_link_get_adjust_train(dp, lane_status); + ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->link.trai= n_set, + dp->link.cap.lanes); + if (ret !=3D dp->link.cap.lanes) { + drm_err(dp->dev, "Update link training failed\n"); + return ret; + } + + voltage_tries =3D level_changed ? 1 : voltage_tries + 1; + } + + drm_err(dp->dev, "dp link training clock recovery %u timers failed\n", ma= x_cr); + dp->link.status.clock_recovered =3D false; + + return 0; +} + +static int dp_link_training_channel_eq(struct dp_dev *dp) +{ + u8 lane_status[DP_LINK_STATUS_SIZE] =3D {0}; + enum dp_pattern_e tps; + u8 eq_tries; + int ret; + + if (dp->link.cap.is_tps4) + tps =3D DP_PATTERN_TPS4; + else if (dp->link.cap.is_tps3) + tps =3D DP_PATTERN_TPS3; + else + tps =3D DP_PATTERN_TPS2; + + ret =3D dp_link_set_pattern(dp, tps); + if (ret) + return ret; + + for (eq_tries =3D 0; eq_tries < EQ_MAX_RETRY; eq_tries++) { + drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); + + ret =3D drm_dp_dpcd_read_link_status(&dp->aux, lane_status); + if (ret !=3D DP_LINK_STATUS_SIZE) { + drm_err(dp->dev, "get lane status failed\n"); + break; + } + + if (!drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) { + drm_info(dp->dev, "clock recovery check failed\n"); + drm_info(dp->dev, "cannot continue channel equalization\n"); + dp->link.status.clock_recovered =3D false; + break; + } + + if (drm_dp_channel_eq_ok(lane_status, dp->link.cap.lanes)) { + dp->link.status.channel_equalized =3D true; + drm_info(dp->dev, "dp link training eq done\n"); + break; + } + + dp_link_get_adjust_train(dp, lane_status); + ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, + dp->link.train_set, dp->link.cap.lanes); + if (ret !=3D dp->link.cap.lanes) { + drm_err(dp->dev, "Update link training failed\n"); + break; + } + } + + if (eq_tries =3D=3D EQ_MAX_RETRY) + drm_err(dp->dev, "channel equalization failed %u times\n", eq_tries); + + dp_link_set_pattern(dp, DP_PATTERN_NO); + + return ret < 0 ? ret : 0; +} + +static int dp_link_downgrade_training_cr(struct dp_dev *dp) +{ + if (dp_link_reduce_rate(dp)) + return dp_link_reduce_lane(dp); + + return 0; +} + +static int dp_link_downgrade_training_eq(struct dp_dev *dp) +{ + if ((dp->link.status.clock_recovered && !dp->link.status.channel_equalize= d)) { + if (!dp_link_reduce_lane(dp)) + return 0; + } + + return dp_link_reduce_rate(dp); +} + +int dp_link_training(struct dp_dev *dp) +{ + struct hibmc_dp_link *link =3D &dp->link; + int ret; + + while (true) { + ret =3D dp_link_training_cr_pre(dp); + if (ret) + goto err; + + ret =3D dp_link_training_cr(dp); + if (ret) + goto err; + + if (!link->status.clock_recovered) { + ret =3D dp_link_downgrade_training_cr(dp); + if (ret) + goto err; + continue; + } + + ret =3D dp_link_training_channel_eq(dp); + if (ret) + goto err; + + if (!link->status.channel_equalized) { + ret =3D dp_link_downgrade_training_eq(dp); + if (ret) + goto err; + continue; + } + + return 0; + } + +err: + dp_link_set_pattern(dp, DP_PATTERN_NO); + + return ret; +} diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.h b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_link.h new file mode 100644 index 000000000000..38877d8f473b --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef DP_LINK_H +#define DP_LINK_H + +#include "dp_comm.h" + +#define DP_LANE_NUM_MAX 2 +#define DP_LANE_STATUS_SIZE 1 +#define DP_LANE_NUM_1 0x1 +#define DP_LANE_NUM_2 0x2 + +enum dp_pattern_e { + DP_PATTERN_NO =3D 0, + DP_PATTERN_TPS1, + DP_PATTERN_TPS2, + DP_PATTERN_TPS3, + DP_PATTERN_TPS4, +}; + +int dp_link_training(struct dp_dev *dp); +u8 dp_get_link_rate(u8 index); + +#endif --=20 2.33.0 From nobody Tue Nov 26 03:36:28 2024 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0C8C17BB3F for ; Tue, 22 Oct 2024 12:47:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729601226; cv=none; b=VA3QiCBuuZvV7kzNW5hcvqWZy7sQTjDaBWekqXy4i/OaC9hm4GOLsUYVFAPYP1R22+5Kbc3yC1S/zolRSdutjNTT4b3LAWVOtkxcmCkADTfCBRw7od8KcPbDS4vI2QCvLfirFp/p18+jEW1EdcH1qPLtH4rfthVJlyXEEaOqm+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729601226; c=relaxed/simple; bh=PY81I468qpnyCJZgjgEqIzW2KNku2vANNeKKKmn7n1g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dmOaswFv0Nk1ytyEqN9jtQE7T+CQeAQTH00lFrw18thpBE0zq/CYoyySU6jWFkwow1qyjw1pOzhdbMF3bi2ep4GK5gOVdY0GxZ/Hzk4lfi7No6z9yuDUeLBovWbpCMeOaXyuXb72+qcBzi/QJBhVDi7wK80jhPYJEgDwGFYO5yk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4XXsNM3RHwz2Fb95; Tue, 22 Oct 2024 20:45:39 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id 76482180042; Tue, 22 Oct 2024 20:47:01 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Tue, 22 Oct 2024 20:47:00 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 drm-dp 3/4] drm/hisilicon/hibmc: add dp hw moduel in hibmc Date: Tue, 22 Oct 2024 20:41:47 +0800 Message-ID: <20241022124148.1952761-4-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20241022124148.1952761-1-shiyongbang@huawei.com> References: <20241022124148.1952761-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: baihan li Build a dp level that hibmc driver can enable dp by calling their functions. Signed-off-by: baihan li --- ChangeLog: v1 -> v2: - changed some defines and functions to former patch, suggested by Dmitry= Baryshkov. - sorting the headers including in dp_hw.h and hibmc_drm_drv.c files, sug= gested by Dmitry Baryshkov. - deleting struct dp_mode and dp_mode_cfg function, suggested by Dmitry B= aryshkov. - fix build errors reported by kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202410040328.VeVxM9yB-lkp= @intel.com/ v1:https://lore.kernel.org/all/20240930100610.782363-1-shiyongbang@huawei= .com/ --- drivers/gpu/drm/hisilicon/hibmc/Makefile | 2 +- .../gpu/drm/hisilicon/hibmc/dp/dp_config.h | 19 ++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 237 ++++++++++++++++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h | 31 +++ 4 files changed, 288 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h diff --git a/drivers/gpu/drm/hisilicon/hibmc/Makefile b/drivers/gpu/drm/his= ilicon/hibmc/Makefile index 94d77da88bbf..214228052ccf 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/Makefile +++ b/drivers/gpu/drm/hisilicon/hibmc/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only hibmc-drm-y :=3D hibmc_drm_drv.o hibmc_drm_de.o hibmc_drm_vdac.o hibmc_drm= _i2c.o \ - dp/dp_aux.o dp/dp_link.o + dp/dp_aux.o dp/dp_link.o dp/dp_hw.o =20 obj-$(CONFIG_DRM_HISI_HIBMC) +=3D hibmc-drm.o diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h b/drivers/gpu/d= rm/hisilicon/hibmc/dp/dp_config.h new file mode 100644 index 000000000000..4846deb794ae --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef DP_CONFIG_H +#define DP_CONFIG_H + +#define DP_BPP 24 +#define DP_SYMBOL_PER_FCLK 4 +#define DP_MSA1 0x20 +#define DP_MSA2 0x845c00 +#define DP_OFFSET 0x1e0000 +#define DP_HDCP 0x2 +#define DP_INT_RST 0xffff +#define DP_DPTX_RST 0x3ff +#define DP_CLK_EN 0x7 +#define DP_SYNC_EN_MASK 0x3 +#define DP_LINK_RATE_CAL 27 + +#endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c new file mode 100644 index 000000000000..5ed3c9138790 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include +#include "dp_config.h" +#include "dp_comm.h" +#include "dp_reg.h" +#include "dp_hw.h" +#include "dp_link.h" +#include "dp_aux.h" + +static int dp_link_init(struct dp_dev *dp) +{ + dp->link.cap.lanes =3D 2; + dp->link.train_set =3D devm_kzalloc(dp->dev->dev, + dp->link.cap.lanes * sizeof(u8), GFP_KERNEL); + if (!dp->link.train_set) + return -ENOMEM; + + dp->link.cap.link_rate =3D 1; + + return 0; +} + +static void dp_set_tu(struct dp_dev *dp, struct drm_display_mode *mode) +{ + u32 tu_symbol_frac_size; + u32 tu_symbol_size; + u64 rate_ks; + u8 lane_num; + u32 value; + u32 bpp; + + lane_num =3D dp->link.cap.lanes; + if (lane_num =3D=3D 0) { + drm_err(dp->dev, "set tu failed, lane num cannot be 0!\n"); + return; + } + + bpp =3D DP_BPP; + rate_ks =3D dp_get_link_rate(dp->link.cap.link_rate) * DP_LINK_RATE_CAL; + value =3D (mode->clock * bpp * 5) / (61 * lane_num * rate_ks); + + if (value % 10 =3D=3D 9) { /* 9 carry */ + tu_symbol_size =3D value / 10 + 1; + tu_symbol_frac_size =3D 0; + } else { + tu_symbol_size =3D value / 10; + tu_symbol_frac_size =3D value % 10 + 1; + } + + drm_info(dp->dev, "tu value: %u.%u value: %u\n", + tu_symbol_size, tu_symbol_frac_size, value); + + dp_write_bits(dp->base + DP_VIDEO_PACKET, + DP_CFG_STREAM_TU_SYMBOL_SIZE, tu_symbol_size); + dp_write_bits(dp->base + DP_VIDEO_PACKET, + DP_CFG_STREAM_TU_SYMBOL_FRAC_SIZE, tu_symbol_frac_size); +} + +static void dp_set_sst(struct dp_dev *dp, struct drm_display_mode *mode) +{ + u32 hblank_size; + u32 htotal_size; + u32 htotal_int; + u32 hblank_int; + u32 fclk; /* flink_clock */ + + fclk =3D dp_get_link_rate(dp->link.cap.link_rate) * DP_LINK_RATE_CAL; + + /* ssc: 9947 / 10000 =3D 0.9947 */ + htotal_int =3D mode->htotal * 9947 / 10000; + htotal_size =3D (u32)((u64)htotal_int * fclk / (DP_SYMBOL_PER_FCLK * (mod= e->clock / 1000))); + + /* ssc: max effect bandwidth 53 / 10000 =3D 0.53% */ + hblank_int =3D (mode->htotal - mode->hdisplay) - mode->hdisplay * 53 / 10= 000; + hblank_size =3D (u64)hblank_int * fclk * 9947 / + (mode->clock * 10 * DP_SYMBOL_PER_FCLK); + + drm_info(dp->dev, "h_active %u v_active %u htotal_size %u hblank_size %u", + mode->hdisplay, mode->vdisplay, htotal_size, hblank_size); + drm_info(dp->dev, "flink_clock %u pixel_clock %d", fclk, (mode->clock / 1= 000)); + + dp_write_bits(dp->base + DP_VIDEO_HORIZONTAL_SIZE, DP_CFG_STREAM_HTOTAL_S= IZE, htotal_size); + dp_write_bits(dp->base + DP_VIDEO_HORIZONTAL_SIZE, DP_CFG_STREAM_HBLANK_S= IZE, hblank_size); +} + +static void dp_link_cfg(struct dp_dev *dp, struct drm_display_mode *mode) +{ + u32 timing_delay; + u32 vblank; + u32 hstart; + u32 vstart; + + vblank =3D mode->vtotal - mode->vdisplay; + timing_delay =3D mode->htotal - mode->hsync_start; + hstart =3D mode->htotal - mode->hsync_start; + vstart =3D mode->vtotal - mode->vsync_start; + + dp_write_bits(dp->base + DP_TIMING_GEN_CONFIG0, + DP_CFG_TIMING_GEN0_HBLANK, (mode->htotal - mode->hdisplay)); + dp_write_bits(dp->base + DP_TIMING_GEN_CONFIG0, + DP_CFG_TIMING_GEN0_HACTIVE, mode->hdisplay); + + dp_write_bits(dp->base + DP_TIMING_GEN_CONFIG2, + DP_CFG_TIMING_GEN0_VBLANK, vblank); + dp_write_bits(dp->base + DP_TIMING_GEN_CONFIG2, + DP_CFG_TIMING_GEN0_VACTIVE, mode->vdisplay); + dp_write_bits(dp->base + DP_TIMING_GEN_CONFIG3, + DP_CFG_TIMING_GEN0_VFRONT_PORCH, (mode->vsync_start - mode->vdispl= ay)); + + dp_write_bits(dp->base + DP_VIDEO_CONFIG0, + DP_CFG_STREAM_HACTIVE, mode->hdisplay); + dp_write_bits(dp->base + DP_VIDEO_CONFIG0, + DP_CFG_STREAM_HBLANK, (mode->htotal - mode->hdisplay)); + dp_write_bits(dp->base + DP_VIDEO_CONFIG2, + DP_CFG_STREAM_HSYNC_WIDTH, (mode->hsync_end - mode->hsync_start)); + + dp_write_bits(dp->base + DP_VIDEO_CONFIG1, + DP_CFG_STREAM_VACTIVE, mode->vdisplay); + dp_write_bits(dp->base + DP_VIDEO_CONFIG1, + DP_CFG_STREAM_VBLANK, vblank); + dp_write_bits(dp->base + DP_VIDEO_CONFIG3, + DP_CFG_STREAM_VFRONT_PORCH, (mode->vsync_start - mode->vdisplay)); + dp_write_bits(dp->base + DP_VIDEO_CONFIG3, + DP_CFG_STREAM_VSYNC_WIDTH, (mode->vsync_end - mode->vsync_start)); + + dp_write_bits(dp->base + DP_VIDEO_MSA0, + DP_CFG_STREAM_VSTART, vstart); + dp_write_bits(dp->base + DP_VIDEO_MSA0, + DP_CFG_STREAM_HSTART, hstart); + + dp_write_bits(dp->base + DP_VIDEO_CTRL, + DP_CFG_STREAM_VSYNC_POLARITY, + mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 : 0); + dp_write_bits(dp->base + DP_VIDEO_CTRL, + DP_CFG_STREAM_HSYNC_POLARITY, + mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 : 0); + + /* MSA mic 0 and 1 */ + writel(DP_MSA1, dp->base + DP_VIDEO_MSA1); + writel(DP_MSA2, dp->base + DP_VIDEO_MSA2); + + dp_set_tu(dp, mode); + + dp_write_bits(dp->base + DP_VIDEO_CTRL, DP_CFG_STREAM_RGB_ENABLE, 0x1); + dp_write_bits(dp->base + DP_VIDEO_CTRL, DP_CFG_STREAM_VIDEO_MAPPING, 0); + + /* divide 2: up even */ + if (timing_delay - timing_delay / 2 * 2) + timing_delay++; + + dp_write_bits(dp->base + DP_TIMING_MODEL_CTRL, + DP_CFG_PIXEL_NUM_TIMING_MODE_SEL1, timing_delay); + + dp_set_sst(dp, mode); +} + +int dp_hw_init(struct hibmc_dp *dp) +{ + struct drm_device *drm_dev =3D dp->drm_dev; + struct dp_dev *dp_dev; + int ret; + + dp_dev =3D devm_kzalloc(drm_dev->dev, sizeof(struct dp_dev), GFP_KERNEL); + if (!dp_dev) + return -ENOMEM; + + dp->dp_dev =3D dp_dev; + + dp_dev->dev =3D drm_dev; + dp_dev->base =3D dp->mmio + DP_OFFSET; + + dp_aux_init(dp_dev); + + ret =3D dp_link_init(dp_dev); + if (ret) { + drm_err(drm_dev, "dp link init failed\n"); + return ret; + } + + /* hdcp data */ + writel(DP_HDCP, dp_dev->base + DP_HDCP_CFG); + /* int init */ + writel(0, dp_dev->base + DP_INTR_ENABLE); + writel(DP_INT_RST, dp_dev->base + DP_INTR_ORIGINAL_STATUS); + /* rst */ + writel(DP_DPTX_RST, dp_dev->base + DP_DPTX_RST_CTRL); + /* clock enable */ + writel(DP_CLK_EN, dp_dev->base + DP_DPTX_CLK_CTRL); + + return 0; +} + +void dp_hw_uninit(struct hibmc_dp *dp) +{ + // keep this uninit interface in the future use +} + +void dp_display_en(struct hibmc_dp *dp, bool enable) +{ + struct dp_dev *dp_dev =3D dp->dp_dev; + + if (enable) { + dp_write_bits(dp_dev->base + DP_VIDEO_CTRL, BIT(0), 0x1); + writel(DP_SYNC_EN_MASK, dp_dev->base + DP_TIMING_SYNC_CTRL); + dp_write_bits(dp_dev->base + DP_DPTX_GCTL0, BIT(10), 0x1); + writel(DP_SYNC_EN_MASK, dp_dev->base + DP_TIMING_SYNC_CTRL); + } else { + dp_write_bits(dp_dev->base + DP_DPTX_GCTL0, BIT(10), 0); + writel(DP_SYNC_EN_MASK, dp_dev->base + DP_TIMING_SYNC_CTRL); + dp_write_bits(dp_dev->base + DP_VIDEO_CTRL, BIT(0), 0); + writel(DP_SYNC_EN_MASK, dp_dev->base + DP_TIMING_SYNC_CTRL); + } + + msleep(50); +} + +int dp_mode_set(struct hibmc_dp *dp, struct drm_display_mode *mode) +{ + struct dp_dev *dp_dev =3D dp->dp_dev; + int ret; + + if (!dp_dev->link.status.channel_equalized) { + ret =3D dp_link_training(dp_dev); + if (ret) { + drm_err(dp->drm_dev, "dp link training failed, ret: %d\n", ret); + return ret; + } + } + + dp_display_en(dp, false); + dp_link_cfg(dp_dev, mode); + + return 0; +} diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.h new file mode 100644 index 000000000000..f5394327dc99 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef DP_KAPI_H +#define DP_KAPI_H + +#include +#include + +#include +#include +#include +#include +#include