From nobody Tue Nov 26 04:45:19 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ECA619C57F for ; Tue, 22 Oct 2024 10:53:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729594439; cv=none; b=FwfigMFyihIoseKlDpzoKvl1aysJsxPnQlAQP4wQro8eswRUz5o+NoKmOIOzWTHtAmbvPW2tJG3VOl9lqU77um98tykfxTPnVPj0T5DjHxuQhdVbke7mrvsfVUiWmAZtvhroRpbBDfLJk29ZfA4zMQTy4uK0LcrObK627l9YuYw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729594439; c=relaxed/simple; bh=Kz66ZBvdDfnbLzNXF5AzvRxd5T6+xWlmdNEg3YMnw0g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=atyHMSrO1rtlTyf8zBrzO6LF+mijogSXf2uSlZQtVJGLyMMZ5DtpwohLp6Ev8/P6qaoZxShkhjKHCW09GGgGHyt3uCRkIQONbK49sVgnlNVpA9FQtWdxV6IlXOJe2hi4NAdRdV9wg3m22FLlxjWk2GhuPmI/LVTHj8G0wMTIxec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=f+mTZsl3; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="f+mTZsl3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729594438; x=1761130438; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Kz66ZBvdDfnbLzNXF5AzvRxd5T6+xWlmdNEg3YMnw0g=; b=f+mTZsl3X5cP/MouGDK0HSmPCvds+34IvzBVwZrisCpL9tgS3U8NPymT 2NIjEbmiBfH3FyUlyUGcw7OS6SShFdoc9QpKatDUB+NqYJASM7Nke6+0I jrx5v5sIiUVEtXs5pPUIMCBQa6kVi/A1+G50NSbqQ1gVhwGY9XoydV8J9 /1S/PIhaKIQc2rPU+LMWKnvENOndABGTZ6BcUDsr7tYFQLZoOKFowflyJ ut0DGt/a+7uR/SYuE/I8YD/e//fyc/yzwZ34VgdZRTGtd9BXFoBLwjHoC ujgXjvI1JhibBMZmHvWukw3DV9L7lEBivPaYcQFWZcMZKeLb6ruaEALpI w==; X-CSE-ConnectionGUID: 09qBWLBZS2y5xRvcH35mSw== X-CSE-MsgGUID: F5v95mfIR/Oqn8ENO/OktQ== X-IronPort-AV: E=McAfee;i="6700,10204,11232"; a="39705097" X-IronPort-AV: E=Sophos;i="6.11,223,1725346800"; d="scan'208";a="39705097" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 03:53:51 -0700 X-CSE-ConnectionGUID: FaLlAvxpTDqRghBFYvas2w== X-CSE-MsgGUID: +jwW4OFnSHSIwBLP+OAVog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,223,1725346800"; d="scan'208";a="79847687" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 03:53:46 -0700 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH 08/10] drm/i915/nvm: add support for access mode Date: Tue, 22 Oct 2024 13:41:17 +0300 Message-ID: <20241022104119.3149051-9-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241022104119.3149051-1-alexander.usyskin@intel.com> References: <20241022104119.3149051-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check NVM access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/intel_nvm.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_nvm.c b/drivers/gpu/drm/i915/intel_= nvm.c index 003c89cbcb88..98c11e027b76 100644 --- a/drivers/gpu/drm/i915/intel_nvm.c +++ b/drivers/gpu/drm/i915/intel_nvm.c @@ -10,6 +10,7 @@ #include "intel_nvm.h" =20 #define GEN12_GUNIT_NVM_SIZE 0x80 +#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3) =20 static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] =3D { [0] =3D { .name =3D "DESCRIPTOR", }, @@ -22,6 +23,29 @@ static void i915_nvm_release_dev(struct device *dev) { } =20 +static bool i915_nvm_writeable_override(struct drm_i915_private *i915) +{ + struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); + resource_size_t base; + bool writeable_override; + + if (IS_DG1(i915)) { + base =3D DG1_GSC_HECI2_BASE; + } else if (IS_DG2(i915)) { + base =3D DG2_GSC_HECI2_BASE; + } else { + dev_err(&pdev->dev, "Unknown platform\n"); + return true; + } + + writeable_override =3D + !(intel_uncore_read(&i915->uncore, HECI_FWSTS(base, 2)) & + HECI_FW_STATUS_2_NVM_ACCESS_MODE); + if (writeable_override) + dev_info(&pdev->dev, "NVM access overridden by jumper\n"); + return writeable_override; +} + void intel_nvm_init(struct drm_i915_private *i915) { struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); @@ -43,7 +67,7 @@ void intel_nvm_init(struct drm_i915_private *i915) =20 nvm =3D i915->nvm; =20 - nvm->writeable_override =3D true; + nvm->writeable_override =3D i915_nvm_writeable_override(i915); nvm->bar.parent =3D &pdev->resource[0]; nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; nvm->bar.end =3D nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; --=20 2.43.0