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Tue, 22 Oct 2024 06:02:20 +0000 From: Himanshu Bhavani To: linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Himanshu Bhavani , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] dt-bindings: pinctrl: convert pinctrl-mcp23s08.txt to yaml format Date: Tue, 22 Oct 2024 11:31:27 +0530 Message-ID: <20241022060157.36372-1-himanshu.bhavani@siliconsignals.io> X-Mailer: git-send-email 2.43.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: PN3PR01CA0012.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:95::21) To PN0P287MB2019.INDP287.PROD.OUTLOOK.COM (2603:1096:c01:1b8::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PN0P287MB2019:EE_|PN2P287MB1711:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b105667-106b-40d9-f94b-08dcf25f173b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|52116014|376014|1800799024|38350700014; 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charset="utf-8" Convert the text bindings of pinctrl-mcp23s08 to YAML so it could be used to validate the DTS. Signed-off-by: Himanshu Bhavani --- .../bindings/pinctrl/pinctrl-mcp23s08.txt | 148 ----------------- .../bindings/pinctrl/pinctrl-mcp23s08.yaml | 153 ++++++++++++++++++ 2 files changed, 153 insertions(+), 148 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23= s08.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23= s08.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt= b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt deleted file mode 100644 index 2fa5edac7a35..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +++ /dev/null @@ -1,148 +0,0 @@ -Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for -8-/16-bit I/O expander with serial interface (I2C/SPI) - -Required properties: -- compatible : Should be - - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version - - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version - - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or - - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip - - - "microchip,mcp23s08" for 8 GPIO SPI version - - "microchip,mcp23s17" for 16 GPIO SPI version - - "microchip,mcp23s18" for 16 GPIO SPI version - - "microchip,mcp23008" for 8 GPIO I2C version or - - "microchip,mcp23017" for 16 GPIO I2C version of the chip - - "microchip,mcp23018" for 16 GPIO I2C version - NOTE: Do not use the old mcp prefix any more. It is deprecated and wil= l be - removed. -- #gpio-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags as described in - 'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defi= ned by - 'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW). -- gpio-controller : Marks the device node as a GPIO controller. -- reg : For an address on its bus. I2C uses this a the I2C address of the = chip. - SPI uses this to specify the chipselect line which the chip is - connected to. The driver and the SPI variant of the chip support - multiple chips on the same chipselect. Have a look at - microchip,spi-present-mask below. - -Required device specific properties (only for SPI chips): -- mcp,spi-present-mask (DEPRECATED) -- microchip,spi-present-mask : This is a present flag, that makes only sen= se for SPI - chips - as the name suggests. Multiple SPI chips can share the same - SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a - chip connected with the corresponding spi address set. For example= if - you have a chip with address 3 connected, you have to set bit3 to = 1, - which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is= not - possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set = at - least one bit to 1 for SPI chips. - NOTE: Do not use the old mcp prefix any more. It is deprecated and wil= l be - removed. -- spi-max-frequency =3D The maximum frequency this chip is able to handle - -Optional properties: -- #interrupt-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags. -- interrupt-controller: Marks the device node as a interrupt controller. -- drive-open-drain: Sets the ODR flag in the IOCON register. This configur= es - the IRQ output as open drain active low. -- reset-gpios: Corresponds to the active-low RESET# pin for the chip - -Optional device specific properties: -- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices - with two interrupt outputs (these are the devices ending with 17 a= nd - those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and - IO 8-15 are bank 2. These chips have two different interrupt outpu= ts: - One for bank 1 and another for bank 2. If irq-mirror is set, both - interrupts are generated regardless of the bank that an input chan= ge - occurred on. If it is not set, the interrupt are only generated fo= r the - bank they belong to. - On devices with only one interrupt output this property is useless. -- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. T= his - configures the IRQ output polarity as active high. - -Example I2C (with interrupt): -gpiom1: gpio@20 { - compatible =3D "microchip,mcp23017"; - gpio-controller; - #gpio-cells =3D <2>; - reg =3D <0x20>; - - interrupt-parent =3D <&gpio1>; - interrupts =3D <17 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells=3D<2>; - microchip,irq-mirror; -}; - -Example SPI: -gpiom1: gpio@0 { - compatible =3D "microchip,mcp23s17"; - gpio-controller; - #gpio-cells =3D <2>; - microchip,spi-present-mask =3D <0x01>; - reg =3D <0>; - spi-max-frequency =3D <1000000>; -}; - -Pull-up configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -If pins are used as output, they can also be configured with pull-ups. Thi= s is -done with pinctrl. - -Please refer file -for details of the common pinctrl bindings used by client devices, -including the meaning of the phrase "pin configuration node". - -Optional Pinmux properties: --------------------------- -Following properties are required if default setting of pins are required -at boot. -- pinctrl-names: A pinctrl state named per . -- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per - . - -The pin configurations are defined as child of the pinctrl states node. Ea= ch -sub-node have following properties: - -Required properties: ------------------- -- pins: List of pins. Valid values of pins properties are: - gpio0 ... gpio7 for the devices with 8 GPIO pins and - gpio0 ... gpio15 for the devices with 16 GPIO pins. - -Optional properties: -------------------- -The following optional property is defined in the pinmux DT binding docume= nt -. Absence of this property will leave the configurat= ion -in its default state. - bias-pull-up - -Example with pinctrl to pull-up output pins: -gpio21: gpio@21 { - compatible =3D "microchip,mcp23017"; - gpio-controller; - #gpio-cells =3D <0x2>; - reg =3D <0x21>; - interrupt-parent =3D <&socgpio>; - interrupts =3D <0x17 0x8>; - interrupt-names =3D "mcp23017@21 irq"; - interrupt-controller; - #interrupt-cells =3D <0x2>; - microchip,irq-mirror; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&i2cgpio0irq>, <&gpio21pullups>; - reset-gpios =3D <&gpio6 15 GPIO_ACTIVE_LOW>; - - gpio21pullups: pinmux { - pins =3D "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15"; - bias-pull-up; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.yam= l b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.yaml new file mode 100644 index 000000000000..3904b8adba44 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright 2024 Silicon Signals Pvt. Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mcp23s08.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip I/O expander with serial interface (I2C/SPI) + +maintainers: + - Himanshu Bhavani + +description: | + Microchip MCP23008, MCP23017, MCP23S08, MCP23S17, MCP23S18 GPIO expander + chips.These chips provide 8 or 16 GPIO pins with either I2C or SPI inter= face. + +properties: + compatible: + enum: + - microchip,mcp23s08 + - microchip,mcp23s17 + - microchip,mcp23s18 + - microchip,mcp23008 + - microchip,mcp23017 + - microchip,mcp23018 + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + + reset-gpios: + description: GPIO specifier for active-low reset pin. + maxItems: 1 + + spi-max-frequency: + description: Maximum frequency for SPI devices. + + microchip,spi-present-mask: + description: | + SPI present mask. Specifies which chips are present on the shared SPI + chipselect. Each bit in the mask represents one SPI address. + $ref: /schemas/types.yaml#/definitions/uint8 + + microchip,irq-mirror: + type: boolean + description: | + Sets the mirror flag in the IOCON register. Devices with two interru= pt + outputs (these are the devices ending with 17 and those that have 16= IOs) + have two IO banks IO 0-7 form bank 1 and IO 8-15 are bank 2. These c= hips + have two different interrupt outputs One for bank 1 and another for + bank 2. If irq-mirror is set, both interrupts are generated regardle= ss of + the bank that an input change occurred on. If it is not set,the inte= rrupt + are only generated for the bank they belong to. + + microchip,irq-active-high: + type: boolean + description: | + Sets the INTPOL flag in the IOCON register.This configures the IRQ o= utput + polarity as active high. + + drive-open-drain: + type: boolean + description: | + Sets the ODR flag in the IOCON register. This configures the IRQ out= put as + open drain active low. + + pinmux: + type: object + properties: + pins: =20 + description: | + The list of GPIO pins controlled by this node. Each pin name cor= responds + to a physical pin on the GPIO expander. + items: + pattern: "^gpio([0-9]|[1][0-5])$" + maxItems: 16 + + bias-pull-up: + type: boolean + description: Configures pull-up resistors for the GPIO pins. + + required: + - pins + - bias-pull-up + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + #include + #include + =20 + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + =20 + mcp23017: gpio@20 { + compatible =3D "microchip,mcp23017"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&gpio1>; + interrupts =3D <17 IRQ_TYPE_LEVEL_LOW>; // Check this line + interrupt-controller; + #interrupt-cells =3D <2>; + + microchip,irq-mirror; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c_gpio0>, <&gpio21pullups>; + reset-gpios =3D <&gpio6 15 GPIO_ACTIVE_LOW>; + =20 + gpio21pullups: pinmux { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + bias-pull-up; + }; + }; + }; + + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + =20 + mcp23s17: gpio@0 { + compatible =3D "microchip,mcp23s17"; + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <2>; + spi-max-frequency =3D <1000000>; + microchip,spi-present-mask =3D /bits/ 8 <0x01>; + }; + }; --=20 2.43.0