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charset="utf-8" Add edma1, sai4, sai5 device nodes bus of in per_bridge3. Add edma2, sai6, sai7, spdif device nodes in bus of per_bridge5. Signed-off-by: Shengjiu Wang --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 212 +++++++++++++++++++++ 1 file changed, 212 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8ulp.dtsi index e32d5afcf4a9..9930bc1cd5ff 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -212,6 +212,70 @@ per_bridge3: bus@29000000 { #size-cells =3D <1>; ranges; =20 + edma1: dma-controller@29010000 { + compatible =3D "fsl,imx8ulp-edma"; + reg =3D <0x29010000 0x210000>; + #dma-cells =3D <3>; + dma-channels =3D <32>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&pcc3 IMX8ULP_CLK_DMA1_MP>, + <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, + <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, + <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, + <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, + <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, + <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, + <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, + <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, + <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, + <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, + <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, + <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, + <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, + <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, + <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, + <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; + clock-names =3D "dma", "ch00","ch01", "ch02", "ch03", + "ch04", "ch05", "ch06", "ch07", + "ch08", "ch09", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24", "ch25", "ch26", "ch27", + "ch28", "ch29", "ch30", "ch31"; + }; + mu: mailbox@29220000 { compatible =3D "fsl,imx8ulp-mu"; reg =3D <0x29220000 0x10000>; @@ -442,6 +506,36 @@ lpuart7: serial@29870000 { status =3D "disabled"; }; =20 + sai4: sai@29880000 { + compatible =3D "fsl,imx8ulp-sai"; + reg =3D <0x29880000 0x10000>; + interrupts =3D ; + clocks =3D <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names =3D "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas =3D <&edma1 67 0 1>, <&edma1 68 0 0>; + dma-names =3D "rx", "tx"; + #sound-dai-cells =3D <0>; + fsl,dataline =3D <0 0x03 0x03>; + status =3D "disabled"; + }; + + sai5: sai@29890000 { + compatible =3D "fsl,imx8ulp-sai"; + reg =3D <0x29890000 0x10000>; + interrupts =3D ; + clocks =3D <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names =3D "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas =3D <&edma1 69 0 1>, <&edma1 70 0 0>; + dma-names =3D "rx", "tx"; + #sound-dai-cells =3D <0>; + fsl,dataline =3D <0 0x0f 0x0f>; + status =3D "disabled"; + }; + iomuxc1: pinctrl@298c0000 { compatible =3D "fsl,imx8ulp-iomuxc1"; reg =3D <0x298c0000 0x10000>; @@ -614,6 +708,70 @@ per_bridge5: bus@2d800000 { #size-cells =3D <1>; ranges; =20 + edma2: dma-controller@2d800000 { + compatible =3D "fsl,imx8ulp-edma"; + reg =3D <0x2d800000 0x210000>; + #dma-cells =3D <3>; + dma-channels =3D <32>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&pcc5 IMX8ULP_CLK_DMA2_MP>, + <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, + <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, + <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, + <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, + <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, + <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, + <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, + <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, + <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, + <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, + <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, + <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, + <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, + <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, + <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, + <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; + clock-names =3D "dma", "ch00","ch01", "ch02", "ch03", + "ch04", "ch05", "ch06", "ch07", + "ch08", "ch09", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24", "ch25", "ch26", "ch27", + "ch28", "ch29", "ch30", "ch31"; + }; + cgc2: clock-controller@2da60000 { compatible =3D "fsl,imx8ulp-cgc2"; reg =3D <0x2da60000 0x10000>; @@ -626,6 +784,60 @@ pcc5: clock-controller@2da70000 { #clock-cells =3D <1>; #reset-cells =3D <1>; }; + + sai6: sai@2da90000 { + compatible =3D "fsl,imx8ulp-sai"; + reg =3D <0x2da90000 0x10000>; + interrupts =3D ; + clocks =3D <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names =3D "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas =3D <&edma2 71 0 1>, <&edma2 72 0 0>; + dma-names =3D "rx", "tx"; + #sound-dai-cells =3D <0>; + fsl,dataline =3D <0 0x0f 0x0f>; + status =3D "disabled"; + }; + + sai7: sai@2daa0000 { + compatible =3D "fsl,imx8ulp-sai"; + reg =3D <0x2daa0000 0x10000>; + interrupts =3D ; + clocks =3D <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names =3D "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas =3D <&edma2 73 0 1>, <&edma2 74 0 0>; + dma-names =3D "rx", "tx"; + #sound-dai-cells =3D <0>; + fsl,dataline =3D <0 0x0f 0x0f>; + status =3D "disabled"; + }; + + spdif: spdif@2dab0000 { + compatible =3D "fsl,imx8ulp-spdif"; + reg =3D <0x2dab0000 0x10000>; + interrupts =3D ; + clocks =3D <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */ + <&sosc>, /* 0, extal */ + <&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */ + <&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */ + <&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */ + clock-names =3D "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas =3D <&edma2 75 0 5>, <&edma2 76 0 4>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; }; =20 gpiod: gpio@2e200000 { --=20 2.34.1