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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-8-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=18156; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=B7MwKrZflyj1l35LNUyKrkOLBnsjNym0juDzFX/eRLs=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kbFFYGx6lJhhYmoJLhtyi16SqBNpwNFVrwp qT1BDUUmlaJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJGwAKCRDBN2bmhouD 1wcTD/9LtJxdiLSYrqtX9086FTdSdSu2eiJDM4XTI+r7o3Ym5SQlylvxA2wLeBbELygSFZ3aFyc lQEdxYux+t4S9zDkotS88RgfqAy6Z0iT4FIpNZsmK9JOxg1xqGD0DRc1MRZJxiyH3fGk3yyAeRb 7PL8SwBa/0JoSkQsVtJXjychBUycLetOpWxB3Iv0CKxXYP5sPJjainZ+84ZaM7wQQsk4sGCZ8/h DinMEszrARl4LoGYTGeumzKtf49mf9uXMwsaOcyPzkrQVAl3wb6kNJEY7us/tss+49rXKp9fIeL ajCw+J/dw6rMoIIiEaicBpQnS/kCkOVfIYSNGYNEtUdLdIeoC5PgvHsbTdfrUGGB3XPmVD8VTJV /9lutnsWL4XqwUE9AfaT72IfQEY8kpX8ZR1UWacPNXXZM2VYZI5+f8O28DQM9VC39a7PwdVKjGW wzVY9a1xJmDisBL1+ssLtDoGFvT4U7te8ECDjcrSVoOOIiaPiBnvElYFhn6umHCzwlPL4BhAA6I 8224O78lq5YePz/YIwn9b/V+7vS90llj/n7DFXlXRKc+eJJrBlRCqD4aS791QtwGPwP8P3buJxE BEFd49uVSToVZlCBMmMSop++vMFnEZbCeTZuLejwQ5j2a75ReFr/IDSiSeJZU5imggziyoxJ81z E9jlCphkAJKZLwg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 190 +++++++++++++++++--------------= ---- arch/arm64/boot/dts/qcom/sm7225.dtsi | 16 +-- 2 files changed, 103 insertions(+), 103 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 17d03045ff33e89e38c7bb65e0386df4c7223d25..2ca5a59ba4fb8a88b189aa906a3= 4995ec33ec4c7 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -45,7 +45,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x0>; @@ -53,21 +53,21 @@ CPU0: cpu@0 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -75,7 +75,7 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x100>; @@ -83,24 +83,24 @@ CPU1: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x200>; @@ -108,24 +108,24 @@ CPU2: cpu@200 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x300>; @@ -133,24 +133,24 @@ CPU3: cpu@300 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x400>; @@ -158,24 +158,24 @@ CPU4: cpu@400 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x500>; @@ -183,24 +183,24 @@ CPU5: cpu@500 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x600>; @@ -208,24 +208,24 @@ CPU6: cpu@600 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <703>; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x700>; @@ -233,61 +233,61 @@ CPU7: cpu@700 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <703>; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; =20 domain-idle-states { - CLUSTER_SLEEP_PC: cluster-sleep-0 { + cluster_sleep_pc: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <2752>; @@ -295,7 +295,7 @@ CLUSTER_SLEEP_PC: cluster-sleep-0 { min-residency-us =3D <6118>; }; =20 - CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + cluster_sleep_cx_ret: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41001244>; entry-latency-us =3D <3638>; @@ -303,7 +303,7 @@ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { min-residency-us =3D <8467>; }; =20 - CLUSTER_AOSS_SLEEP: cluster-sleep-2 { + cluster_aoss_sleep: cluster-sleep-2 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100b244>; entry-latency-us =3D <3263>; @@ -315,7 +315,7 @@ CLUSTER_AOSS_SLEEP: cluster-sleep-2 { cpu_idle_states: idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -325,7 +325,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + little_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -335,7 +335,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -345,7 +345,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + big_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -504,59 +504,59 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_PC - &CLUSTER_SLEEP_CX_RET - &CLUSTER_AOSS_SLEEP>; + domain-idle-states =3D <&cluster_sleep_pc + &cluster_sleep_cx_ret + &cluster_aoss_sleep>; }; }; =20 @@ -2777,7 +2777,7 @@ apps_rsc: rsc@18200000 { qcom,drv-id =3D <2>; qcom,tcs-config =3D , , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 rpmhcc: clock-controller { compatible =3D "qcom,sm6350-rpmh-clk"; @@ -2954,7 +2954,7 @@ cpu0-crit { cooling-maps { map0 { trip =3D <&cpu0_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2979,7 +2979,7 @@ cpu1-crit { cooling-maps { map0 { trip =3D <&cpu1_alert0>; - cooling-device =3D <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3004,7 +3004,7 @@ cpu2-crit { cooling-maps { map0 { trip =3D <&cpu2_alert0>; - cooling-device =3D <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3029,7 +3029,7 @@ cpu3-crit { cooling-maps { map0 { trip =3D <&cpu3_alert0>; - cooling-device =3D <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3054,7 +3054,7 @@ cpu4-crit { cooling-maps { map0 { trip =3D <&cpu4_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3079,7 +3079,7 @@ cpu5-crit { cooling-maps { map0 { trip =3D <&cpu5_alert0>; - cooling-device =3D <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3104,7 +3104,7 @@ cpu6-left-crit { cooling-maps { map0 { trip =3D <&cpu6_left_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3129,7 +3129,7 @@ cpu6-right-crit { cooling-maps { map0 { trip =3D <&cpu6_right_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3154,7 +3154,7 @@ cpu7-left-crit { cooling-maps { map0 { trip =3D <&cpu7_left_alert0>; - cooling-device =3D <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3179,7 +3179,7 @@ cpu7-right-crit { cooling-maps { map0 { trip =3D <&cpu7_right_alert0>; - cooling-device =3D <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225.dtsi b/arch/arm64/boot/dts/qco= m/sm7225.dtsi index b7b4044e9bb0cb25e01b782acffd1e0069ed6a6b..a8ffdfb254fe61245a0b073b41e= 6db172e6b5415 100644 --- a/arch/arm64/boot/dts/qcom/sm7225.dtsi +++ b/arch/arm64/boot/dts/qcom/sm7225.dtsi @@ -6,14 +6,14 @@ #include "sm6350.dtsi" =20 /* SM7225 uses Kryo 570 instead of Kryo 560 */ -&CPU0 { compatible =3D "qcom,kryo570"; }; -&CPU1 { compatible =3D "qcom,kryo570"; }; -&CPU2 { compatible =3D "qcom,kryo570"; }; -&CPU3 { compatible =3D "qcom,kryo570"; }; -&CPU4 { compatible =3D "qcom,kryo570"; }; -&CPU5 { compatible =3D "qcom,kryo570"; }; -&CPU6 { compatible =3D "qcom,kryo570"; }; -&CPU7 { compatible =3D "qcom,kryo570"; }; +&cpu0 { compatible =3D "qcom,kryo570"; }; +&cpu1 { compatible =3D "qcom,kryo570"; }; +&cpu2 { compatible =3D "qcom,kryo570"; }; +&cpu3 { compatible =3D "qcom,kryo570"; }; +&cpu4 { compatible =3D "qcom,kryo570"; }; +&cpu5 { compatible =3D "qcom,kryo570"; }; +&cpu6 { compatible =3D "qcom,kryo570"; }; +&cpu7 { compatible =3D "qcom,kryo570"; }; =20 &cpu0_opp_table { opp-1804800000 { --=20 2.43.0