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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-2-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=45120; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=ALIXUFaj3TITSq6RcHZynbmUg4yb4KvnV43vbFxTm9A=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kVwLmRY0393LQqlIX4QXurYJa+Stza5Jn8N 86u/i4VpmOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJFQAKCRDBN2bmhouD 1y78EACSk3lx/KoFIGRX4fk7kFyIFs14rYawEjjtdTP2XnKbLcmaMPmgDnKiFTkBCFVlgZFCTR9 yG/AQMytIDpi/m2F2XijkJ2Sg+hjyllXtdmsEDzam1Rv79D+MdEPNLuIB6qrAvjAVpaWRrK3/sI 7P+OMBh9PVzg3ZEDAH6hRM+8mdy7nW4YN+mc7SgldoLu2aa0dP8Idd5cXp8fo2qqYL3VFiAtY8Q rhhPpP7QU/RSqPsG/mcN+3N/R/nchSHRbm2FHJvPUaxE3gvUMfrdP4IG5EcsWxbIeYfg6hvxY/n O/dQ5b23m7jp0h1RBvOYR0iKmElmIARD9ZA3nPUu5kj757RoQD9HDV5tK7Wt3Iw04jDVgkPBMBS sdcPWYJo+9KtJCbvFwAylgiisS+edGk/8rf+Q59/a5O2nnzjcMyfdH8bcCZdU3CVqLq3Av+2OJR N6XB88CfSYbhGJCs40W487gG6qqq9j4bTaMx6cnob87Gl+jPa3Z9/bcGyJcZ++Gcc8lyjB2WayE JeDYXF+teqpQNImNV6fA4WXkk1Z3u65RxWRrszSr07W4XSNZdIPFPjHhrnSeEeCLbVZnQVE+pZw SGg9kPImp0BxmoAL1OUNFG4X90GSAP4UVLZyF3QgGO4WUm+vYRI070v36yJ+ii8xLqdoZJX1zwn eJvivMfkHORpl4g== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 100 ++++++++++----------- arch/arm64/boot/dts/qcom/msm8939.dtsi | 110 ++++++++++++--------= ---- arch/arm64/boot/dts/qcom/msm8953.dtsi | 68 +++++++-------- arch/arm64/boot/dts/qcom/msm8976.dtsi | 32 +++---- arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts | 12 +-- arch/arm64/boot/dts/qcom/msm8992.dtsi | 4 +- arch/arm64/boot/dts/qcom/msm8994.dtsi | 52 +++++------ arch/arm64/boot/dts/qcom/msm8996.dtsi | 54 ++++++------ arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi | 32 +++---- arch/arm64/boot/dts/qcom/msm8998.dtsi | 92 ++++++++++---------- arch/arm64/boot/dts/qcom/sdm632.dtsi | 26 +++--- 12 files changed, 292 insertions(+), 292 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi b/arch/arm/boot/d= ts/qcom/qcom-msm8916-smp.dtsi index 1ba403b83cb1d4e92b218ab6b9a44ed4f9d4308a..94b7694eeeffaffe88a6e28d625= 187f36a1d69f5 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi @@ -25,7 +25,7 @@ psci { }; }; =20 -&CPU_SLEEP_0 { +&cpu_sleep_0 { compatible =3D "qcom,idle-state-spc", "arm,idle-state"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qc= om/msm8916.dtsi index 0ee44706b70ba3844a5bdd63298f318fb9e1d7c5..5e558bcc9d87893486352e5e211= f131d4a1f67e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -133,67 +133,67 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; enable-method =3D "psci"; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; #cooling-cells =3D <2>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,acc =3D <&cpu0_acc>; qcom,saw =3D <&cpu0_saw>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; enable-method =3D "psci"; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; #cooling-cells =3D <2>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,acc =3D <&cpu1_acc>; qcom,saw =3D <&cpu1_saw>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; enable-method =3D "psci"; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; #cooling-cells =3D <2>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,acc =3D <&cpu2_acc>; qcom,saw =3D <&cpu2_saw>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; enable-method =3D "psci"; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; #cooling-cells =3D <2>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,acc =3D <&cpu3_acc>; qcom,saw =3D <&cpu3_saw>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -202,7 +202,7 @@ L2_0: l2-cache { idle-states { entry-method =3D "psci"; =20 - CPU_SLEEP_0: cpu-sleep-0 { + cpu_sleep_0: cpu-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "standalone-power-collapse"; arm,psci-suspend-param =3D <0x40000002>; @@ -215,7 +215,7 @@ CPU_SLEEP_0: cpu-sleep-0 { =20 domain-idle-states { =20 - CLUSTER_RET: cluster-retention { + cluster_ret: cluster-retention { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000012>; entry-latency-us =3D <500>; @@ -223,7 +223,7 @@ CLUSTER_RET: cluster-retention { min-residency-us =3D <2000>; }; =20 - CLUSTER_PWRDN: cluster-gdhs { + cluster_pwrdn: cluster-gdhs { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000032>; entry-latency-us =3D <2000>; @@ -273,33 +273,33 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + domain-idle-states =3D <&cluster_ret>, <&cluster_pwrdn>; }; }; =20 @@ -823,7 +823,7 @@ debug0: debug@850000 { reg =3D <0x00850000 0x1000>; clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; status =3D "disabled"; }; =20 @@ -832,7 +832,7 @@ debug1: debug@852000 { reg =3D <0x00852000 0x1000>; clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; status =3D "disabled"; }; =20 @@ -841,7 +841,7 @@ debug2: debug@854000 { reg =3D <0x00854000 0x1000>; clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; status =3D "disabled"; }; =20 @@ -850,7 +850,7 @@ debug3: debug@856000 { reg =3D <0x00856000 0x1000>; clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; status =3D "disabled"; }; =20 @@ -864,7 +864,7 @@ cti12: cti@858000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; arm,cs-dev-assoc =3D <&etm0>; =20 status =3D "disabled"; @@ -879,7 +879,7 @@ cti13: cti@859000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; arm,cs-dev-assoc =3D <&etm1>; =20 status =3D "disabled"; @@ -894,7 +894,7 @@ cti14: cti@85a000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; arm,cs-dev-assoc =3D <&etm2>; =20 status =3D "disabled"; @@ -909,7 +909,7 @@ cti15: cti@85b000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; arm,cs-dev-assoc =3D <&etm3>; =20 status =3D "disabled"; @@ -923,7 +923,7 @@ etm0: etm@85c000 { clock-names =3D "apb_pclk", "atclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 status =3D "disabled"; =20 @@ -944,7 +944,7 @@ etm1: etm@85d000 { clock-names =3D "apb_pclk", "atclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 status =3D "disabled"; =20 @@ -965,7 +965,7 @@ etm2: etm@85e000 { clock-names =3D "apb_pclk", "atclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 status =3D "disabled"; =20 @@ -986,7 +986,7 @@ etm3: etm@85f000 { clock-names =3D "apb_pclk", "atclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 status =3D "disabled"; =20 @@ -2644,10 +2644,10 @@ cpu0_1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_1_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2673,10 +2673,10 @@ cpu2_3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_3_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qc= om/msm8939.dtsi index 28634789a8a9704be6f0841d2189dd93c413c9ab..bbd116a6d492e9129b7ba363b66= 6bdc5667a069c 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -42,122 +42,122 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@100 { + cpu0: cpu@100 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x100>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs1_mbox>; #cooling-cells =3D <2>; - L2_1: l2-cache { + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@101 { + cpu1: cpu@101 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x101>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs1_mbox>; #cooling-cells =3D <2>; }; =20 - CPU2: cpu@102 { + cpu2: cpu@102 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x102>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,acc =3D <&acc2>; qcom,saw =3D <&saw2>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs1_mbox>; #cooling-cells =3D <2>; }; =20 - CPU3: cpu@103 { + cpu3: cpu@103 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x103>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,acc =3D <&acc3>; qcom,saw =3D <&saw3>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs1_mbox>; #cooling-cells =3D <2>; }; =20 - CPU4: cpu@0 { + cpu4: cpu@0 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x0>; qcom,acc =3D <&acc4>; qcom,saw =3D <&saw4>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs0_mbox>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@1 { + cpu5: cpu@1 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x1>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,acc =3D <&acc5>; qcom,saw =3D <&saw5>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs0_mbox>; #cooling-cells =3D <2>; }; =20 - CPU6: cpu@2 { + cpu6: cpu@2 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,acc =3D <&acc6>; qcom,saw =3D <&saw6>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs0_mbox>; #cooling-cells =3D <2>; }; =20 - CPU7: cpu@3 { + cpu7: cpu@3 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x3>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,acc =3D <&acc7>; qcom,saw =3D <&saw7>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs0_mbox>; #cooling-cells =3D <2>; }; =20 idle-states { - CPU_SLEEP_0: cpu-sleep-0 { + cpu_sleep_0: cpu-sleep-0 { compatible =3D "arm,idle-state"; entry-latency-us =3D <130>; exit-latency-us =3D <150>; @@ -182,19 +182,19 @@ cpu-map { /* LITTLE (efficiency) cluster */ cluster0 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; =20 @@ -202,19 +202,19 @@ core3 { /* Boot CPU is cluster 1 core 0 */ cluster1 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; }; @@ -2318,10 +2318,10 @@ cpu0_crit: trip1 { cooling-maps { map0 { trip =3D <&cpu0_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2348,10 +2348,10 @@ cpu1_crit: trip1 { cooling-maps { map0 { trip =3D <&cpu1_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2378,10 +2378,10 @@ cpu2_crit: trip1 { cooling-maps { map0 { trip =3D <&cpu2_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2408,10 +2408,10 @@ cpu3_crit: trip1 { cooling-maps { map0 { trip =3D <&cpu3_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2438,10 +2438,10 @@ cpu4567_crit: trip1 { cooling-maps { map0 { trip =3D <&cpu4567_alert>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qc= om/msm8953.dtsi index d20fd3d7c46e4f93a4436c39d5286f69ed7a99c7..af4c341e2533ef2cca593e0dc97= 003334d3fd6b7 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -38,125 +38,125 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x100>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x101>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x102>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x103>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; =20 - L2_0: l2-cache-0 { + l2_0: l2-cache-0 { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; =20 - L2_1: l2-cache-1 { + l2_1: l2-cache-1 { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -1985,7 +1985,7 @@ cpu0_crit: crit { cooling-maps { map0 { trip =3D <&cpu0_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2009,7 +2009,7 @@ cpu1_crit: crit { cooling-maps { map0 { trip =3D <&cpu1_alert>; - cooling-device =3D <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2033,7 +2033,7 @@ cpu2_crit: crit { cooling-maps { map0 { trip =3D <&cpu2_alert>; - cooling-device =3D <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2057,7 +2057,7 @@ cpu3_crit: crit { cooling-maps { map0 { trip =3D <&cpu3_alert>; - cooling-device =3D <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2079,7 +2079,7 @@ cpu4_crit: crit { cooling-maps { map0 { trip =3D <&cpu4_alert>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2101,7 +2101,7 @@ cpu5_crit: crit { cooling-maps { map0 { trip =3D <&cpu5_alert>; - cooling-device =3D <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2123,7 +2123,7 @@ cpu6_crit: crit { cooling-maps { map0 { trip =3D <&cpu6_alert>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2145,7 +2145,7 @@ cpu7_crit: crit { cooling-maps { map0 { trip =3D <&cpu7_alert>; - cooling-device =3D <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qc= om/msm8976.dtsi index ed6ba4730cadc782fb1e0ee62e0478f7e9626b12..d036f31dfdca162debe18ed6ed9= a7767a34aced6 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -31,7 +31,7 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; @@ -42,7 +42,7 @@ CPU0: cpu@0 { #cooling-cells =3D <2>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; @@ -53,7 +53,7 @@ CPU1: cpu@1 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; @@ -64,7 +64,7 @@ CPU2: cpu@2 { #cooling-cells =3D <2>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; @@ -75,7 +75,7 @@ CPU3: cpu@3 { #cooling-cells =3D <2>; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a72"; reg =3D <0x100>; @@ -86,7 +86,7 @@ CPU4: cpu@100 { #cooling-cells =3D <2>; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "arm,cortex-a72"; reg =3D <0x101>; @@ -97,7 +97,7 @@ CPU5: cpu@101 { #cooling-cells =3D <2>; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "arm,cortex-a72"; reg =3D <0x102>; @@ -108,7 +108,7 @@ CPU6: cpu@102 { #cooling-cells =3D <2>; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "arm,cortex-a72"; reg =3D <0x103>; @@ -122,37 +122,37 @@ CPU7: cpu@103 { cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts b/arch/arm64/boot= /dts/qcom/msm8992-lg-h815.dts index 38b305816d2f762c98aca13951fa35c32f035d8b..4520d5d51a2998580d9bf8ed27c= c662939ad82c2 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts @@ -91,27 +91,27 @@ key-vol-up { }; }; =20 -&CPU0 { +&cpu0 { enable-method =3D "spin-table"; }; =20 -&CPU1 { +&cpu1 { enable-method =3D "spin-table"; }; =20 -&CPU2 { +&cpu2 { enable-method =3D "spin-table"; }; =20 -&CPU3 { +&cpu3 { enable-method =3D "spin-table"; }; =20 -&CPU4 { +&cpu4 { enable-method =3D "spin-table"; }; =20 -&CPU5 { +&cpu5 { enable-method =3D "spin-table"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qc= om/msm8992.dtsi index 02fc3795dbfd73a5c2905f630a88e42b520e7a2e..b2dc46c25fa24321f91b13b1950= 968418d927d6c 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -6,8 +6,8 @@ #include "msm8994.dtsi" =20 /* 8992 only features 2 A57 cores. */ -/delete-node/ &CPU6; -/delete-node/ &CPU7; +/delete-node/ &cpu6; +/delete-node/ &cpu7; /delete-node/ &cpu6_map; /delete-node/ &cpu7_map; =20 diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qc= om/msm8994.dtsi index fc2a7f13f690ee1c640c78b13bfe419321a61a3a..1acb0f159511996db07bc7543cf= 4f194a4ebd0fa 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -43,114 +43,114 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x2>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x3>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; - L2_1: l2-cache { + next-level-cache =3D <&l2_1>; + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x101>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x102>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x103>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 cpu6_map: core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 cpu7_map: core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qc= om/msm8996.dtsi index e5966724f37c691ce871df9313e41c56ca84c419..b379623c1b8a0844c9de5255c46= 47fe3490bd2aa 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -43,90 +43,90 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x0>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; capacity-dmips-mhz =3D <1024>; clocks =3D <&kryocc 0>; interconnects =3D <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 =3D <&cluster0_opp>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x1>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; capacity-dmips-mhz =3D <1024>; clocks =3D <&kryocc 0>; interconnects =3D <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 =3D <&cluster0_opp>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU2: cpu@100 { + cpu2: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x100>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; capacity-dmips-mhz =3D <1024>; clocks =3D <&kryocc 1>; interconnects =3D <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 =3D <&cluster1_opp>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_1>; - L2_1: l2-cache { + next-level-cache =3D <&l2_1>; + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU3: cpu@101 { + cpu3: cpu@101 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x101>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; capacity-dmips-mhz =3D <1024>; clocks =3D <&kryocc 1>; interconnects =3D <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 =3D <&cluster1_opp>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core1 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; }; @@ -134,7 +134,7 @@ core1 { idle-states { entry-method =3D "psci"; =20 - CPU_SLEEP_0: cpu-sleep-0 { + cpu_sleep_0: cpu-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "standalone-power-collapse"; arm,psci-suspend-param =3D <0x00000004>; @@ -2829,7 +2829,7 @@ debug@3810000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 etm@3840000 { @@ -2839,7 +2839,7 @@ etm@3840000 { clocks =3D <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 out-ports { port { @@ -2858,7 +2858,7 @@ debug@3910000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 etm@3940000 { @@ -2868,7 +2868,7 @@ etm@3940000 { clocks =3D <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 out-ports { port { @@ -2923,7 +2923,7 @@ debug@3a10000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 etm@3a40000 { @@ -2933,7 +2933,7 @@ etm@3a40000 { clocks =3D <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 out-ports { port { @@ -2952,7 +2952,7 @@ debug@3b10000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 etm@3b40000 { @@ -2962,7 +2962,7 @@ etm@3b40000 { clocks =3D <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 out-ports { port { diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/b= oot/dts/qcom/msm8998-clamshell.dtsi index 3b7172aa40374cb953fc27cc36546a897b748258..4748a093af2fc520e5e5273dcc4= 9d7721ffe5b3a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi @@ -61,36 +61,36 @@ cts-pins { * not advertised as enabled in ACPI, and enabling it in DT can cause boot * hangs. */ -&CPU0 { - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_1>; +&cpu0 { + cpu-idle-states =3D <&little_cpu_sleep_1>; }; =20 -&CPU1 { - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_1>; +&cpu1 { + cpu-idle-states =3D <&little_cpu_sleep_1>; }; =20 -&CPU2 { - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_1>; +&cpu2 { + cpu-idle-states =3D <&little_cpu_sleep_1>; }; =20 -&CPU3 { - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_1>; +&cpu3 { + cpu-idle-states =3D <&little_cpu_sleep_1>; }; =20 -&CPU4 { - cpu-idle-states =3D <&BIG_CPU_SLEEP_1>; +&cpu4 { + cpu-idle-states =3D <&big_cpu_sleep_1>; }; =20 -&CPU5 { - cpu-idle-states =3D <&BIG_CPU_SLEEP_1>; +&cpu5 { + cpu-idle-states =3D <&big_cpu_sleep_1>; }; =20 -&CPU6 { - cpu-idle-states =3D <&BIG_CPU_SLEEP_1>; +&cpu6 { + cpu-idle-states =3D <&big_cpu_sleep_1>; }; =20 -&CPU7 { - cpu-idle-states =3D <&BIG_CPU_SLEEP_1>; +&cpu7 { + cpu-idle-states =3D <&big_cpu_sleep_1>; }; =20 /* diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qc= om/msm8998.dtsi index 4952da36ba5935b1ed135cf2bbab1dc9b669868e..c2caad85c668df2ebe900bc560e= 39480ae03e353 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -136,130 +136,130 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x0>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + cpu-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x1>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache =3D <&L2_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + next-level-cache =3D <&l2_0>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x2>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache =3D <&L2_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + next-level-cache =3D <&l2_0>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x3>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache =3D <&L2_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + next-level-cache =3D <&l2_0>; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x100>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1536>; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache =3D <&L2_1>; - L2_1: l2-cache { + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + next-level-cache =3D <&l2_1>; + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x101>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1536>; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache =3D <&L2_1>; + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x102>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1536>; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache =3D <&L2_1>; + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x103>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1536>; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache =3D <&L2_1>; + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + next-level-cache =3D <&l2_1>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -267,7 +267,7 @@ core3 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-retention"; /* CPU Retention (C2D), L2 Active */ @@ -277,7 +277,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { min-residency-us =3D <504>; }; =20 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + little_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-power-collapse"; /* CPU + L2 Power Collapse (C3, D4) */ @@ -288,7 +288,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-retention"; /* CPU Retention (C2D), L2 Active */ @@ -298,7 +298,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { min-residency-us =3D <1302>; }; =20 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + big_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-power-collapse"; /* CPU + L2 Power Collapse (C3, D4) */ @@ -1874,7 +1874,7 @@ etm1: etm@7840000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 out-ports { port { @@ -1894,7 +1894,7 @@ etm2: etm@7940000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 out-ports { port { @@ -1914,7 +1914,7 @@ etm3: etm@7a40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 out-ports { port { @@ -1934,7 +1934,7 @@ etm4: etm@7b40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 out-ports { port { @@ -2068,7 +2068,7 @@ etm5: etm@7c40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 out-ports { port { @@ -2087,7 +2087,7 @@ etm6: etm@7d40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 out-ports { port { @@ -2106,7 +2106,7 @@ etm7: etm@7e40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 out-ports { port { @@ -2125,7 +2125,7 @@ etm8: etm@7f40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 out-ports { port { diff --git a/arch/arm64/boot/dts/qcom/sdm632.dtsi b/arch/arm64/boot/dts/qco= m/sdm632.dtsi index 95b025ea260bdbc48e15496dda34cdd5a7f0a448..40d86d91b67fa02d100c108baf6= 06222c1c6c4df 100644 --- a/arch/arm64/boot/dts/qcom/sdm632.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm632.dtsi @@ -14,10 +14,10 @@ cpu0-thermal { =20 cooling-maps { map0 { - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -42,40 +42,40 @@ cpu7-thermal { =20 /* * SDM632 uses Kryo 250 instead of Cortex A53 - * CPU0-3 are efficiency cores, CPU4-7 are performance cores + * cpu0-3 are efficiency cores, cpu4-7 are performance cores */ -&CPU0 { +&cpu0 { compatible =3D "qcom,kryo250"; }; =20 -&CPU1 { +&cpu1 { compatible =3D "qcom,kryo250"; }; =20 -&CPU2 { +&cpu2 { compatible =3D "qcom,kryo250"; }; =20 -&CPU3 { +&cpu3 { compatible =3D "qcom,kryo250"; }; =20 -&CPU4 { +&cpu4 { compatible =3D "qcom,kryo250"; capacity-dmips-mhz =3D <1980>; }; =20 -&CPU5 { +&cpu5 { compatible =3D "qcom,kryo250"; capacity-dmips-mhz =3D <1980>; }; =20 -&CPU6 { +&cpu6 { compatible =3D "qcom,kryo250"; capacity-dmips-mhz =3D <1980>; }; =20 -&CPU7 { +&cpu7 { compatible =3D "qcom,kryo250"; capacity-dmips-mhz =3D <1980>; }; --=20 2.43.0