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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-18-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=16448; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=CV3H0zvj4P3Kw7YcRn5Q8CqsEW5i2UEX4m8ePcJEUs8=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kjPx43d+4urlc4Qy0BZxi+c/9DQd0ENaumW v3RYMwHoeGJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJIwAKCRDBN2bmhouD 10ZZD/9uENiZJ6zI38qo2evNNoLzJfFWOrnnfz89h3XyvNxfTFcxBBUUVDC42Md5cKu3WwZuYKP Jrq1QdB48bD4mQylWbPGZpu+SeSzbpC6oFjQgEiYOcruS9JxkbMBl9IaXmg0S298omeot6J1ol4 rezfcvjnY3Pjb2KIMaN0dX23dB4SHRnJGeubHRK+JdybANNvwG9wn9Quh/BZLguOSRb62wRPKMS f3mlS4lpn8+oibi8AOQt76cjnW8NjGUlSK4ZyMJKOv2d8ND9uY/RkQ3KJfo4psiLQOhuE5u3XmV R9bzTTqLqE2maZ/Iheq9ZJSYnWlVVcqduIfqnsS3LSjS5ubCwE3rSQbzDcycqWEBCe5ndn5aRGt c4Ram7hhk7Hx3r9+2Z6Lbw8uZqRA8KxQTpquLrlp2Z61WOdhdPs8fNWfeRqBXVHXPq3tC1Ecnf2 qLECwBEb+cPZ7I8LA3VftHcq7Ns8xdVjlXLuL1Z4HaKYsBB4s6/AnbeKggpx7p+aVEUtt/lNlLb /Be6p/CS3RbNnPMhtnToYcnc8GpOrygSvtVQbhgPlzWA3vpnXoW1i6tbsCDzjXxJO9uwvfxfusW wEwqVLNu//vG9+0Wq/ZuEdyG+r+7nxYB12p1kj+geiKV1drkg7pr0ef4Wne+HF75XQJ6VQs0X4Y N73+VQVFXz9Xq2A== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- 1. New patch --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 36 ++++++++++++++++------------= ---- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 20 +++++++++--------- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 ++++----- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 6 +++--- arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi | 4 ++-- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 34 +++++++++++++++-------------= -- arch/arm/boot/dts/qcom/qcom-msm8660.dtsi | 6 +++--- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 6 +++--- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 36 ++++++++++++++++------------= ---- 9 files changed, 79 insertions(+), 79 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/q= com/qcom-apq8064.dtsi index 1bc935d900854ea40e7520ac5762f307c73232f2..5f1a6b4b764492486df1a261097= 9f56c0a37b64a 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -36,58 +36,58 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <2>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc2>; qcom,saw =3D <&saw2>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <3>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc3>; qcom,saw =3D <&saw3>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; =20 idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible =3D "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us =3D <400>; @@ -1625,7 +1625,7 @@ etm@1a1c000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 out-ports { port { @@ -1643,7 +1643,7 @@ etm@1a1d000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 out-ports { port { @@ -1661,7 +1661,7 @@ etm@1a1e000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 out-ports { port { @@ -1679,7 +1679,7 @@ etm@1a1f000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 out-ports { port { diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/q= com/qcom-apq8084.dtsi index 40dbbf8655f09ff3c6259c69bdd08b2fe3c39594..cee0694ef127b5e2450e274659c= 403e0be81f401 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -32,10 +32,10 @@ cpu@0 { compatible =3D "qcom,krait"; reg =3D <0>; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 cpu@1 { @@ -43,10 +43,10 @@ cpu@1 { compatible =3D "qcom,krait"; reg =3D <1>; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 cpu@2 { @@ -54,10 +54,10 @@ cpu@2 { compatible =3D "qcom,krait"; reg =3D <2>; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc2>; qcom,saw =3D <&saw2>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 cpu@3 { @@ -65,13 +65,13 @@ cpu@3 { compatible =3D "qcom,krait"; reg =3D <3>; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc3>; qcom,saw =3D <&saw3>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -79,7 +79,7 @@ L2: l2-cache { }; =20 idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible =3D "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us =3D <150>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/q= com/qcom-ipq4019.dtsi index 56415ab34083f38f0f5c6aefa873947409c8cc6a..06b20c196faf3fe35983d7ee2ab= ebd2066f83b02 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -47,7 +47,7 @@ cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; reg =3D <0x0>; @@ -61,7 +61,7 @@ cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; reg =3D <0x1>; @@ -75,7 +75,7 @@ cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc2>; qcom,saw =3D <&saw2>; reg =3D <0x2>; @@ -89,7 +89,7 @@ cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc3>; qcom,saw =3D <&saw3>; reg =3D <0x3>; @@ -99,7 +99,7 @@ cpu@3 { operating-points-v2 =3D <&cpu0_opp_table>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/q= com/qcom-ipq8064.dtsi index 0f02f59c282a25698bade3ef3cac3082bd056b3c..96e97350153506922b7560131e3= 3664d51e891b5 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -27,7 +27,7 @@ cpu0: cpu@0 { enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; }; @@ -37,12 +37,12 @@ cpu1: cpu@1 { enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/q= com/qcom-mdm9615.dtsi index 573feb3218c33c449f95f4922c24400cea9ac0cc..7de8d6c550167ac37e09dc5d92b= 7a3b2e21753cb 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -30,7 +30,7 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a5"; reg =3D <0>; device_type =3D "cpu"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; }; }; =20 @@ -61,7 +61,7 @@ soc: soc { ranges; compatible =3D "simple-bus"; =20 - L2: cache-controller@2040000 { + l2: cache-controller@2040000 { compatible =3D "arm,pl310-cache"; reg =3D <0x02040000 0x1000>; arm,data-latency =3D <2 2 0>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8226.dtsi index 3a685ff7e8ccf505e2801607a70099f4b3c16137..64c8ac94f352e46dc4a18f902d2= c30114ecd91d2 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -39,12 +39,12 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,msm8226-smp"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; qcom,acc =3D <&acc0>; @@ -52,12 +52,12 @@ CPU0: cpu@0 { #cooling-cells =3D <2>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,msm8226-smp"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; qcom,acc =3D <&acc1>; @@ -65,12 +65,12 @@ CPU1: cpu@1 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,msm8226-smp"; device_type =3D "cpu"; reg =3D <2>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; qcom,acc =3D <&acc2>; @@ -78,12 +78,12 @@ CPU2: cpu@2 { #cooling-cells =3D <2>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,msm8226-smp"; device_type =3D "cpu"; reg =3D <3>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; qcom,acc =3D <&acc3>; @@ -91,7 +91,7 @@ CPU3: cpu@3 { #cooling-cells =3D <2>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -1264,10 +1264,10 @@ cpu0-thermal { cooling-maps { map0 { trip =3D <&cpu_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; =20 @@ -1295,10 +1295,10 @@ cpu1-thermal { cooling-maps { map0 { trip =3D <&cpu_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; =20 diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8660.dtsi index a66c474cd1aa0d4303dbb1fdaa97072c1f45a7b2..3f69b98d0041eb16093668d6b83= a2da0c3496638 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -22,7 +22,7 @@ cpu@0 { enable-method =3D "qcom,gcc-msm8660"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; }; =20 cpu@1 { @@ -30,10 +30,10 @@ cpu@1 { enable-method =3D "qcom,gcc-msm8660"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8960.dtsi index ebc43c5c6e5f756995a5d48bdee102b0b3c47106..865fe7cc39511d7cb9ec5c4b121= 00404f77e2989 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -25,7 +25,7 @@ cpu@0 { enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; }; @@ -35,12 +35,12 @@ cpu@1 { enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8974.dtsi index 742d2104b4fe5db54fcbf8c55c6fb2e0fb12a410..e3f9c56a778cf8c64735ede1e85= 286bde12c1c87 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -35,51 +35,51 @@ cpus { #size-cells =3D <0>; interrupts =3D ; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v2"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v2"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v2"; device_type =3D "cpu"; reg =3D <2>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc2>; qcom,saw =3D <&saw2>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v2"; device_type =3D "cpu"; reg =3D <3>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc3>; qcom,saw =3D <&saw3>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -87,7 +87,7 @@ L2: l2-cache { }; =20 idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible =3D "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us =3D <150>; @@ -960,7 +960,7 @@ etm@fc33c000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 out-ports { port { @@ -978,7 +978,7 @@ etm@fc33d000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 out-ports { port { @@ -996,7 +996,7 @@ etm@fc33e000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 out-ports { port { @@ -1014,7 +1014,7 @@ etm@fc33f000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 out-ports { port { --=20 2.43.0