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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-14-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11241; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=N4xxcEjJPumCJxJbggY58CEN96mc+S3LZciqIJaEmuo=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kgF6WUUJbA7sWf1v2z09SkM4FlcvOLofJVJ XJofyaqsDCJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJIAAKCRDBN2bmhouD 13xLD/wMlzqPsl0S8aB1HmDpXxU0U/S71F8QPYXG9wHF6NYYLnm+GDD/+d/3NqlQF2XtimsiW/R Pc2gF2IEs+AvRx8JE7/YlVc/PnF3w4WOMB/A8WhtmucGSxTI5nNDO95w5Ibd6f0nklkk9aBW2LD JXzhy2EMKOqgl/405WL8q9Eobti2lxInCfViSTtcpf+HesH9O2sN7SribvND1DVnBy97LUfd9Wq ImCETvRG9uDbGjtEsYGLqcRb01LqKtVsaOoh7h1VlEO+cw/qP6tSz30AI8zm1swC1RJxF6QDVBR mEbhGVfhVQFtfFkGR2oO0GqHEJIL8nPs5sfiqminu6i/8F0m3VIsozYOsqb42be8Ya3ZxSREzZN k1sl0sMjJXjC89am7zIhbD2HrowjUnRr2qOxrsCCjDJjOSHqARO2ZLtpWxpq6Wot/pNu/+IIrpK 4bWOQaAPDr/kXd9Yz8bZ0avrdgQ27eyOe4MqatckpQC3ZAGCbRAyIQNvHcE00UHcSimgJNiXKpV vl/0QPaY2rOpBXPCnPxSuEovlTNqFLlxTj9N2+8kCSvcbrk6O2cljloc4MjtBhhA0znL8oeSasn ccOrUUtbspmPbpUk8jCyyWNBZYn4ubtUYCcorjww8P5ZLlJCuT2GXK+SqWCwKnvU932AqckSAhn kTcTCjQAZfIQthw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 156 +++++++++++++++++--------------= ---- 1 file changed, 78 insertions(+), 78 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 3d8a807a81c9c15eeeaadf624a8e7f085b68ae9e..0c2b2a12663363b7d35eec89051= 697d69aba287d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -68,18 +68,18 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a520"; reg =3D <0 0>; =20 clocks =3D <&cpufreq_hw 0>; =20 - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; =20 @@ -87,13 +87,13 @@ CPU0: cpu@0 { =20 #cooling-cells =3D <2>; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; =20 - L3_0: l3-cache { + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -101,18 +101,18 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a520"; reg =3D <0 0x100>; =20 clocks =3D <&cpufreq_hw 0>; =20 - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; =20 @@ -121,18 +121,18 @@ CPU1: cpu@100 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x200>; =20 clocks =3D <&cpufreq_hw 3>; =20 - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -140,26 +140,26 @@ CPU2: cpu@200 { =20 #cooling-cells =3D <2>; =20 - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x300>; =20 clocks =3D <&cpufreq_hw 3>; =20 - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -168,18 +168,18 @@ CPU3: cpu@300 { #cooling-cells =3D <2>; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x400>; =20 clocks =3D <&cpufreq_hw 3>; =20 - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -187,26 +187,26 @@ CPU4: cpu@400 { =20 #cooling-cells =3D <2>; =20 - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x500>; =20 clocks =3D <&cpufreq_hw 1>; =20 - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -214,26 +214,26 @@ CPU5: cpu@500 { =20 #cooling-cells =3D <2>; =20 - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x600>; =20 clocks =3D <&cpufreq_hw 1>; =20 - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -241,26 +241,26 @@ CPU6: cpu@600 { =20 #cooling-cells =3D <2>; =20 - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "arm,cortex-x4"; reg =3D <0 0x700>; =20 clocks =3D <&cpufreq_hw 2>; =20 - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <588>; =20 @@ -268,46 +268,46 @@ CPU7: cpu@700 { =20 #cooling-cells =3D <2>; =20 - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -315,7 +315,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { + silver_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -325,7 +325,7 @@ SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { + gold_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -335,7 +335,7 @@ GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { + gold_plus_cpu_sleep_0: cpu-sleep-2-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-plus-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -347,7 +347,7 @@ GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <750>; @@ -355,7 +355,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { min-residency-us =3D <9144>; }; =20 - CLUSTER_SLEEP_1: cluster-sleep-1 { + cluster_sleep_1: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c344>; entry-latency-us =3D <2800>; @@ -411,58 +411,58 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&SILVER_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&SILVER_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&SILVER_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_PLUS_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_plus_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>, - <&CLUSTER_SLEEP_1>; + domain-idle-states =3D <&cluster_sleep_0>, + <&cluster_sleep_1>; }; }; =20 @@ -5081,7 +5081,7 @@ apps_rsc: rsc@17a00000 { , ; =20 - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 qcom,tcs-offset =3D <0xd00>; qcom,drv-id =3D <2>; --=20 2.43.0