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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-13-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11525; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=fdf5q7Kdg5agvSReu+CjfGcEHicH6nlf1t2RIbqvN1I=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kfZCwdQUtnoJZTzVx95Q4Oy8Z9Vh8f7Fvue DrohB/TiTCJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJHwAKCRDBN2bmhouD 14xYD/oDqHPB1D03/2Vuzud1vu1jfBDzrFRB4sWdmF+M/5t+WpTe9bxX60TaaU7PVeUe29pjRDU Ckxu08/Fm93ogTTMPl4poD9SH0so6cjQoReaqRO0bH30+Ukae2v4d/0Sp2l2pBmPB1geGUnyBAc fX/e59mK0AKHKxnTpopToAqsmXlVulxkkzp46hWtJokmLzyasH9DMaDGJz2vXrJoskUSmVVvDDk bYJfBxc9NNlU/NHW3yX9PQFKUyzwLEA0aMtcXdv6WGC6ZcsypzTnO8Ipl+v+Fhn5Xn1+kVO0eNK H2FgDlOOdaMazb6hs06MDEZ8zD/t1YA+og/gI8yUii0P6CFwkFqZACsuZQaigN50sR38YNN35Zy ScJI+JNebAJ30KcE0Hjr9a6fyp2QOXAwLQEA1tFiiaf1jqD1dv783z2tJglY1WPy74KElG2cl5O GhTMzct1D9ZxBGfJgvXFzO4IMR0KfetCwqctSpcn6GspjEdas25VzVRwof+vj1lxytRzX/IUFs8 d/OCNLxnu96Px4jAnXfrfgHPmmnXRoBzIOif5Kk4nRIxt6bZBf0n/zdYz2kCbPa7TPEC3C3gUD1 GZKBUvrfk4pJwUZQV7A9/CRf19o/e+oUSyDHD5EsdnUZ1Tq2bHskYIWxAW2iTfJBFylTkvEH0Wp 3ndR8CTUXMHrJ/A== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 162 +++++++++++++++++--------------= ---- 1 file changed, 81 insertions(+), 81 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 93c8aa32e411b4aecb3140110073f422b407bf80..9d2ee372b225783c0fd2acc0fe2= 3329fa42abb12 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -64,25 +64,25 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a510"; reg =3D <0 0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -90,185 +90,185 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a510"; reg =3D <0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_100>; - power-domains =3D <&CPU_PD1>; + next-level-cache =3D <&l2_100>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a510"; reg =3D <0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; - power-domains =3D <&CPU_PD2>; + next-level-cache =3D <&l2_200>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a715"; reg =3D <0 0x300>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_300>; - power-domains =3D <&CPU_PD3>; + next-level-cache =3D <&l2_300>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a715"; reg =3D <0 0x400>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; - power-domains =3D <&CPU_PD4>; + next-level-cache =3D <&l2_400>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a710"; reg =3D <0 0x500>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; - power-domains =3D <&CPU_PD5>; + next-level-cache =3D <&l2_500>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-a710"; reg =3D <0 0x600>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; - power-domains =3D <&CPU_PD6>; + next-level-cache =3D <&l2_600>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "arm,cortex-x3"; reg =3D <0 0x700>; clocks =3D <&cpufreq_hw 2>; enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; - power-domains =3D <&CPU_PD7>; + next-level-cache =3D <&l2_700>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 2>; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <588>; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -276,7 +276,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -286,7 +286,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -296,7 +296,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { + prime_cpu_sleep_0: cpu-sleep-2-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "goldplus-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -308,7 +308,7 @@ PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <750>; @@ -316,7 +316,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { min-residency-us =3D <9144>; }; =20 - CLUSTER_SLEEP_1: cluster-sleep-1 { + cluster_sleep_1: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c344>; entry-latency-us =3D <2800>; @@ -376,57 +376,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&PRIME_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&prime_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; + domain-idle-states =3D <&cluster_sleep_0>, <&cluster_sleep_1>; }; }; =20 @@ -4366,7 +4366,7 @@ apps_rsc: rsc@17a00000 { qcom,drv-id =3D <2>; qcom,tcs-config =3D , , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; --=20 2.43.0