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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11894; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=5KnjYWNoQonMUKH4Crw2+ZOH1md/NQUEce78VXKNOZY=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kUhKasX3yA7UIFSLy2ucDPLGsYAU0S0U1TE FPdhBDLTOCJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJFAAKCRDBN2bmhouD 17I0EACXJ420vCKaof13mmlrKJy/B+nd6Z/sPyfS/lDzUIyqiMTCH2Jcb+LMwiqNDDQEltsQ+9c r3MFjbrkcVYUmtUoPC65lUqFfimSFmgVgZyRIl6wT3tLwEWmVyTdsdKmq2oicMS8FR5TpAvwyvW G1ZXUPt+Uy5ESxwnGcON9nmYj04Zk+qDKmKacLxK1/En91sXxUv9wcDKDBJgS8v0ej7F5rZYlJK XjM6quxdSIADCoeokhv3f2FiCisp4Cyge5H0j8yzwRHaK3aKhz3mvANmPkWFHEBXafgRlRg0PXb KPJrj7OAARvdMMG+IAPjTRh0moXNBn4nuVO39omoUp4Laqt+vCqP4m7cZZIyaDr4+wWMmY1c04T 2ECKEFDFIYxY/nBYVoYfA1tXDJ9sUksxbWxOwV9tf+x5wpggrApJHrYsLtsqDvOPlGaouEbO3tK WgH55W+Jw8h65/dWlbb0XuElyCU6lZIOLPD2rSFRZNOXuJWyZrvVgEw7jvOQMbyanzpG5lNe7Ea 0JNuEUdWyQqsRYkdFOMLlP+JbPec/FgD7SBwN+79t0/7Fdgj6pHFfxbO3cfd5jdIKPLNLKieDFE PSUUrL+ylINLXKhKOSudyS0/UZl9pmk0d4qOxbaDkcYUwKBaZQS8VqCymzWahtt0lDyOWuRH6Et yog65bHjhyNCrRQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++---- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 ++++++------- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++++--------- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 ++++++------- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++++++--------------= ---- 5 files changed, 61 insertions(+), 61 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 7e6e2c1219793145fdbc6d97cac5c1a646dd77b3..8914f2ef0bc47fda243b19174f7= 7ce73fc10757d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -31,27 +31,27 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x80000>; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index 71328b22353114f21404450fcf54e2767fa50cd9..d3c3e215a15cfc3998f8e306568= 28a46b6991898 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -31,47 +31,47 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qc= om/ipq6018.dtsi index 8edd535a188f2ddc8af2f564f514c8be4a8d7a43..dbf6716bcb59a04939c2b994d85= cf58c12365962 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -34,12 +34,12 @@ cpus: cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -47,12 +47,12 @@ CPU0: cpu@0 { #cooling-cells =3D <2>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x1>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -60,12 +60,12 @@ CPU1: cpu@1 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -73,12 +73,12 @@ CPU2: cpu@2 { #cooling-cells =3D <2>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x3>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -86,7 +86,7 @@ CPU3: cpu@3 { #cooling-cells =3D <2>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -1015,10 +1015,10 @@ cpu_alert: cpu-passive { cooling-maps { map0 { trip =3D <&cpu_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qc= om/ipq8074.dtsi index 284a4553070faa94960d12e6b08fadf8cd2c6b06..78e1992b749573ea899e4d639ee= df437cab19d59 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -32,39 +32,39 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; enable-method =3D "psci"; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x1>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x3>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 14c7b3a78442c85c3b5dab24498aa1740facc22b..d1fd35ebc4a28bafee77e7be441= 709f99f482558 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -34,12 +34,12 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a73"; reg =3D <0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -47,12 +47,12 @@ CPU0: cpu@0 { #cooling-cells =3D <2>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a73"; reg =3D <0x1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -60,12 +60,12 @@ CPU1: cpu@1 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a73"; reg =3D <0x2>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -73,12 +73,12 @@ CPU2: cpu@2 { #cooling-cells =3D <2>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a73"; reg =3D <0x3>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -86,7 +86,7 @@ CPU3: cpu@3 { #cooling-cells =3D <2>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -863,10 +863,10 @@ cpu0_alert: cpu-passive { cooling-maps { map0 { trip =3D <&cpu0_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -891,10 +891,10 @@ cpu1_alert: cpu-passive { cooling-maps { map0 { trip =3D <&cpu1_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -919,10 +919,10 @@ cpu2_alert: cpu-passive { cooling-maps { map0 { trip =3D <&cpu2_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -947,10 +947,10 @@ cpu3_alert: cpu-passive { cooling-maps { map0 { trip =3D <&cpu3_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; --=20 2.43.0