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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11894; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=5KnjYWNoQonMUKH4Crw2+ZOH1md/NQUEce78VXKNOZY=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kUhKasX3yA7UIFSLy2ucDPLGsYAU0S0U1TE FPdhBDLTOCJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJFAAKCRDBN2bmhouD 17I0EACXJ420vCKaof13mmlrKJy/B+nd6Z/sPyfS/lDzUIyqiMTCH2Jcb+LMwiqNDDQEltsQ+9c r3MFjbrkcVYUmtUoPC65lUqFfimSFmgVgZyRIl6wT3tLwEWmVyTdsdKmq2oicMS8FR5TpAvwyvW G1ZXUPt+Uy5ESxwnGcON9nmYj04Zk+qDKmKacLxK1/En91sXxUv9wcDKDBJgS8v0ej7F5rZYlJK XjM6quxdSIADCoeokhv3f2FiCisp4Cyge5H0j8yzwRHaK3aKhz3mvANmPkWFHEBXafgRlRg0PXb KPJrj7OAARvdMMG+IAPjTRh0moXNBn4nuVO39omoUp4Laqt+vCqP4m7cZZIyaDr4+wWMmY1c04T 2ECKEFDFIYxY/nBYVoYfA1tXDJ9sUksxbWxOwV9tf+x5wpggrApJHrYsLtsqDvOPlGaouEbO3tK WgH55W+Jw8h65/dWlbb0XuElyCU6lZIOLPD2rSFRZNOXuJWyZrvVgEw7jvOQMbyanzpG5lNe7Ea 0JNuEUdWyQqsRYkdFOMLlP+JbPec/FgD7SBwN+79t0/7Fdgj6pHFfxbO3cfd5jdIKPLNLKieDFE PSUUrL+ylINLXKhKOSudyS0/UZl9pmk0d4qOxbaDkcYUwKBaZQS8VqCymzWahtt0lDyOWuRH6Et yog65bHjhyNCrRQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++---- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 ++++++------- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++++--------- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 ++++++------- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++++++--------------= ---- 5 files changed, 61 insertions(+), 61 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 7e6e2c1219793145fdbc6d97cac5c1a646dd77b3..8914f2ef0bc47fda243b19174f7= 7ce73fc10757d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -31,27 +31,27 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x80000>; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index 71328b22353114f21404450fcf54e2767fa50cd9..d3c3e215a15cfc3998f8e306568= 28a46b6991898 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -31,47 +31,47 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qc= om/ipq6018.dtsi index 8edd535a188f2ddc8af2f564f514c8be4a8d7a43..dbf6716bcb59a04939c2b994d85= cf58c12365962 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -34,12 +34,12 @@ cpus: cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -47,12 +47,12 @@ CPU0: cpu@0 { #cooling-cells =3D <2>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x1>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -60,12 +60,12 @@ CPU1: cpu@1 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -73,12 +73,12 @@ CPU2: cpu@2 { #cooling-cells =3D <2>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x3>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -86,7 +86,7 @@ CPU3: cpu@3 { #cooling-cells =3D <2>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -1015,10 +1015,10 @@ cpu_alert: cpu-passive { cooling-maps { map0 { trip =3D <&cpu_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qc= om/ipq8074.dtsi index 284a4553070faa94960d12e6b08fadf8cd2c6b06..78e1992b749573ea899e4d639ee= df437cab19d59 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -32,39 +32,39 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; enable-method =3D "psci"; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x1>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; enable-method =3D "psci"; reg =3D <0x3>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 14c7b3a78442c85c3b5dab24498aa1740facc22b..d1fd35ebc4a28bafee77e7be441= 709f99f482558 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -34,12 +34,12 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a73"; reg =3D <0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -47,12 +47,12 @@ CPU0: cpu@0 { #cooling-cells =3D <2>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a73"; reg =3D <0x1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -60,12 +60,12 @@ CPU1: cpu@1 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a73"; reg =3D <0x2>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -73,12 +73,12 @@ CPU2: cpu@2 { #cooling-cells =3D <2>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a73"; reg =3D <0x3>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; @@ -86,7 +86,7 @@ CPU3: cpu@3 { #cooling-cells =3D <2>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -863,10 +863,10 @@ cpu0_alert: cpu-passive { cooling-maps { map0 { trip =3D <&cpu0_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -891,10 +891,10 @@ cpu1_alert: cpu-passive { cooling-maps { map0 { trip =3D <&cpu1_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -919,10 +919,10 @@ cpu2_alert: cpu-passive { cooling-maps { map0 { trip =3D <&cpu2_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -947,10 +947,10 @@ cpu3_alert: cpu-passive { cooling-maps { map0 { trip =3D <&cpu3_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-2-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=45120; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=ALIXUFaj3TITSq6RcHZynbmUg4yb4KvnV43vbFxTm9A=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kVwLmRY0393LQqlIX4QXurYJa+Stza5Jn8N 86u/i4VpmOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJFQAKCRDBN2bmhouD 1y78EACSk3lx/KoFIGRX4fk7kFyIFs14rYawEjjtdTP2XnKbLcmaMPmgDnKiFTkBCFVlgZFCTR9 yG/AQMytIDpi/m2F2XijkJ2Sg+hjyllXtdmsEDzam1Rv79D+MdEPNLuIB6qrAvjAVpaWRrK3/sI 7P+OMBh9PVzg3ZEDAH6hRM+8mdy7nW4YN+mc7SgldoLu2aa0dP8Idd5cXp8fo2qqYL3VFiAtY8Q rhhPpP7QU/RSqPsG/mcN+3N/R/nchSHRbm2FHJvPUaxE3gvUMfrdP4IG5EcsWxbIeYfg6hvxY/n O/dQ5b23m7jp0h1RBvOYR0iKmElmIARD9ZA3nPUu5kj757RoQD9HDV5tK7Wt3Iw04jDVgkPBMBS sdcPWYJo+9KtJCbvFwAylgiisS+edGk/8rf+Q59/a5O2nnzjcMyfdH8bcCZdU3CVqLq3Av+2OJR N6XB88CfSYbhGJCs40W487gG6qqq9j4bTaMx6cnob87Gl+jPa3Z9/bcGyJcZ++Gcc8lyjB2WayE JeDYXF+teqpQNImNV6fA4WXkk1Z3u65RxWRrszSr07W4XSNZdIPFPjHhrnSeEeCLbVZnQVE+pZw SGg9kPImp0BxmoAL1OUNFG4X90GSAP4UVLZyF3QgGO4WUm+vYRI070v36yJ+ii8xLqdoZJX1zwn eJvivMfkHORpl4g== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 100 ++++++++++----------- arch/arm64/boot/dts/qcom/msm8939.dtsi | 110 ++++++++++++--------= ---- arch/arm64/boot/dts/qcom/msm8953.dtsi | 68 +++++++-------- arch/arm64/boot/dts/qcom/msm8976.dtsi | 32 +++---- arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts | 12 +-- arch/arm64/boot/dts/qcom/msm8992.dtsi | 4 +- arch/arm64/boot/dts/qcom/msm8994.dtsi | 52 +++++------ arch/arm64/boot/dts/qcom/msm8996.dtsi | 54 ++++++------ arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi | 32 +++---- arch/arm64/boot/dts/qcom/msm8998.dtsi | 92 ++++++++++---------- arch/arm64/boot/dts/qcom/sdm632.dtsi | 26 +++--- 12 files changed, 292 insertions(+), 292 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi b/arch/arm/boot/d= ts/qcom/qcom-msm8916-smp.dtsi index 1ba403b83cb1d4e92b218ab6b9a44ed4f9d4308a..94b7694eeeffaffe88a6e28d625= 187f36a1d69f5 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi @@ -25,7 +25,7 @@ psci { }; }; =20 -&CPU_SLEEP_0 { +&cpu_sleep_0 { compatible =3D "qcom,idle-state-spc", "arm,idle-state"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qc= om/msm8916.dtsi index 0ee44706b70ba3844a5bdd63298f318fb9e1d7c5..5e558bcc9d87893486352e5e211= f131d4a1f67e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -133,67 +133,67 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; enable-method =3D "psci"; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; #cooling-cells =3D <2>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,acc =3D <&cpu0_acc>; qcom,saw =3D <&cpu0_saw>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; enable-method =3D "psci"; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; #cooling-cells =3D <2>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,acc =3D <&cpu1_acc>; qcom,saw =3D <&cpu1_saw>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; enable-method =3D "psci"; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; #cooling-cells =3D <2>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,acc =3D <&cpu2_acc>; qcom,saw =3D <&cpu2_saw>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; enable-method =3D "psci"; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; #cooling-cells =3D <2>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,acc =3D <&cpu3_acc>; qcom,saw =3D <&cpu3_saw>; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -202,7 +202,7 @@ L2_0: l2-cache { idle-states { entry-method =3D "psci"; =20 - CPU_SLEEP_0: cpu-sleep-0 { + cpu_sleep_0: cpu-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "standalone-power-collapse"; arm,psci-suspend-param =3D <0x40000002>; @@ -215,7 +215,7 @@ CPU_SLEEP_0: cpu-sleep-0 { =20 domain-idle-states { =20 - CLUSTER_RET: cluster-retention { + cluster_ret: cluster-retention { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000012>; entry-latency-us =3D <500>; @@ -223,7 +223,7 @@ CLUSTER_RET: cluster-retention { min-residency-us =3D <2000>; }; =20 - CLUSTER_PWRDN: cluster-gdhs { + cluster_pwrdn: cluster-gdhs { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000032>; entry-latency-us =3D <2000>; @@ -273,33 +273,33 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + domain-idle-states =3D <&cluster_ret>, <&cluster_pwrdn>; }; }; =20 @@ -823,7 +823,7 @@ debug0: debug@850000 { reg =3D <0x00850000 0x1000>; clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; status =3D "disabled"; }; =20 @@ -832,7 +832,7 @@ debug1: debug@852000 { reg =3D <0x00852000 0x1000>; clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; status =3D "disabled"; }; =20 @@ -841,7 +841,7 @@ debug2: debug@854000 { reg =3D <0x00854000 0x1000>; clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; status =3D "disabled"; }; =20 @@ -850,7 +850,7 @@ debug3: debug@856000 { reg =3D <0x00856000 0x1000>; clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; status =3D "disabled"; }; =20 @@ -864,7 +864,7 @@ cti12: cti@858000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; arm,cs-dev-assoc =3D <&etm0>; =20 status =3D "disabled"; @@ -879,7 +879,7 @@ cti13: cti@859000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; arm,cs-dev-assoc =3D <&etm1>; =20 status =3D "disabled"; @@ -894,7 +894,7 @@ cti14: cti@85a000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; arm,cs-dev-assoc =3D <&etm2>; =20 status =3D "disabled"; @@ -909,7 +909,7 @@ cti15: cti@85b000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; arm,cs-dev-assoc =3D <&etm3>; =20 status =3D "disabled"; @@ -923,7 +923,7 @@ etm0: etm@85c000 { clock-names =3D "apb_pclk", "atclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 status =3D "disabled"; =20 @@ -944,7 +944,7 @@ etm1: etm@85d000 { clock-names =3D "apb_pclk", "atclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 status =3D "disabled"; =20 @@ -965,7 +965,7 @@ etm2: etm@85e000 { clock-names =3D "apb_pclk", "atclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 status =3D "disabled"; =20 @@ -986,7 +986,7 @@ etm3: etm@85f000 { clock-names =3D "apb_pclk", "atclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 status =3D "disabled"; =20 @@ -2644,10 +2644,10 @@ cpu0_1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_1_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2673,10 +2673,10 @@ cpu2_3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_3_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qc= om/msm8939.dtsi index 28634789a8a9704be6f0841d2189dd93c413c9ab..bbd116a6d492e9129b7ba363b66= 6bdc5667a069c 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -42,122 +42,122 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@100 { + cpu0: cpu@100 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x100>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs1_mbox>; #cooling-cells =3D <2>; - L2_1: l2-cache { + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@101 { + cpu1: cpu@101 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x101>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs1_mbox>; #cooling-cells =3D <2>; }; =20 - CPU2: cpu@102 { + cpu2: cpu@102 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x102>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,acc =3D <&acc2>; qcom,saw =3D <&saw2>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs1_mbox>; #cooling-cells =3D <2>; }; =20 - CPU3: cpu@103 { + cpu3: cpu@103 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x103>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,acc =3D <&acc3>; qcom,saw =3D <&saw3>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs1_mbox>; #cooling-cells =3D <2>; }; =20 - CPU4: cpu@0 { + cpu4: cpu@0 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x0>; qcom,acc =3D <&acc4>; qcom,saw =3D <&saw4>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs0_mbox>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@1 { + cpu5: cpu@1 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x1>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,acc =3D <&acc5>; qcom,saw =3D <&saw5>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs0_mbox>; #cooling-cells =3D <2>; }; =20 - CPU6: cpu@2 { + cpu6: cpu@2 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,acc =3D <&acc6>; qcom,saw =3D <&saw6>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs0_mbox>; #cooling-cells =3D <2>; }; =20 - CPU7: cpu@3 { + cpu7: cpu@3 { compatible =3D "arm,cortex-a53"; device_type =3D "cpu"; enable-method =3D "spin-table"; reg =3D <0x3>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,acc =3D <&acc7>; qcom,saw =3D <&saw7>; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; clocks =3D <&apcs0_mbox>; #cooling-cells =3D <2>; }; =20 idle-states { - CPU_SLEEP_0: cpu-sleep-0 { + cpu_sleep_0: cpu-sleep-0 { compatible =3D "arm,idle-state"; entry-latency-us =3D <130>; exit-latency-us =3D <150>; @@ -182,19 +182,19 @@ cpu-map { /* LITTLE (efficiency) cluster */ cluster0 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; =20 @@ -202,19 +202,19 @@ core3 { /* Boot CPU is cluster 1 core 0 */ cluster1 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; }; @@ -2318,10 +2318,10 @@ cpu0_crit: trip1 { cooling-maps { map0 { trip =3D <&cpu0_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2348,10 +2348,10 @@ cpu1_crit: trip1 { cooling-maps { map0 { trip =3D <&cpu1_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2378,10 +2378,10 @@ cpu2_crit: trip1 { cooling-maps { map0 { trip =3D <&cpu2_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2408,10 +2408,10 @@ cpu3_crit: trip1 { cooling-maps { map0 { trip =3D <&cpu3_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2438,10 +2438,10 @@ cpu4567_crit: trip1 { cooling-maps { map0 { trip =3D <&cpu4567_alert>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qc= om/msm8953.dtsi index d20fd3d7c46e4f93a4436c39d5286f69ed7a99c7..af4c341e2533ef2cca593e0dc97= 003334d3fd6b7 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -38,125 +38,125 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x100>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x101>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x102>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x103>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; =20 - L2_0: l2-cache-0 { + l2_0: l2-cache-0 { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; =20 - L2_1: l2-cache-1 { + l2_1: l2-cache-1 { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -1985,7 +1985,7 @@ cpu0_crit: crit { cooling-maps { map0 { trip =3D <&cpu0_alert>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2009,7 +2009,7 @@ cpu1_crit: crit { cooling-maps { map0 { trip =3D <&cpu1_alert>; - cooling-device =3D <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2033,7 +2033,7 @@ cpu2_crit: crit { cooling-maps { map0 { trip =3D <&cpu2_alert>; - cooling-device =3D <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2057,7 +2057,7 @@ cpu3_crit: crit { cooling-maps { map0 { trip =3D <&cpu3_alert>; - cooling-device =3D <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2079,7 +2079,7 @@ cpu4_crit: crit { cooling-maps { map0 { trip =3D <&cpu4_alert>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2101,7 +2101,7 @@ cpu5_crit: crit { cooling-maps { map0 { trip =3D <&cpu5_alert>; - cooling-device =3D <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2123,7 +2123,7 @@ cpu6_crit: crit { cooling-maps { map0 { trip =3D <&cpu6_alert>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2145,7 +2145,7 @@ cpu7_crit: crit { cooling-maps { map0 { trip =3D <&cpu7_alert>; - cooling-device =3D <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qc= om/msm8976.dtsi index ed6ba4730cadc782fb1e0ee62e0478f7e9626b12..d036f31dfdca162debe18ed6ed9= a7767a34aced6 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -31,7 +31,7 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; @@ -42,7 +42,7 @@ CPU0: cpu@0 { #cooling-cells =3D <2>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; @@ -53,7 +53,7 @@ CPU1: cpu@1 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; @@ -64,7 +64,7 @@ CPU2: cpu@2 { #cooling-cells =3D <2>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; @@ -75,7 +75,7 @@ CPU3: cpu@3 { #cooling-cells =3D <2>; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a72"; reg =3D <0x100>; @@ -86,7 +86,7 @@ CPU4: cpu@100 { #cooling-cells =3D <2>; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "arm,cortex-a72"; reg =3D <0x101>; @@ -97,7 +97,7 @@ CPU5: cpu@101 { #cooling-cells =3D <2>; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "arm,cortex-a72"; reg =3D <0x102>; @@ -108,7 +108,7 @@ CPU6: cpu@102 { #cooling-cells =3D <2>; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "arm,cortex-a72"; reg =3D <0x103>; @@ -122,37 +122,37 @@ CPU7: cpu@103 { cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts b/arch/arm64/boot= /dts/qcom/msm8992-lg-h815.dts index 38b305816d2f762c98aca13951fa35c32f035d8b..4520d5d51a2998580d9bf8ed27c= c662939ad82c2 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts @@ -91,27 +91,27 @@ key-vol-up { }; }; =20 -&CPU0 { +&cpu0 { enable-method =3D "spin-table"; }; =20 -&CPU1 { +&cpu1 { enable-method =3D "spin-table"; }; =20 -&CPU2 { +&cpu2 { enable-method =3D "spin-table"; }; =20 -&CPU3 { +&cpu3 { enable-method =3D "spin-table"; }; =20 -&CPU4 { +&cpu4 { enable-method =3D "spin-table"; }; =20 -&CPU5 { +&cpu5 { enable-method =3D "spin-table"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qc= om/msm8992.dtsi index 02fc3795dbfd73a5c2905f630a88e42b520e7a2e..b2dc46c25fa24321f91b13b1950= 968418d927d6c 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -6,8 +6,8 @@ #include "msm8994.dtsi" =20 /* 8992 only features 2 A57 cores. */ -/delete-node/ &CPU6; -/delete-node/ &CPU7; +/delete-node/ &cpu6; +/delete-node/ &cpu7; /delete-node/ &cpu6_map; /delete-node/ &cpu7_map; =20 diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qc= om/msm8994.dtsi index fc2a7f13f690ee1c640c78b13bfe419321a61a3a..1acb0f159511996db07bc7543cf= 4f194a4ebd0fa 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -43,114 +43,114 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x2>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x3>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; - L2_1: l2-cache { + next-level-cache =3D <&l2_1>; + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x101>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x102>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x103>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 cpu6_map: core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 cpu7_map: core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qc= om/msm8996.dtsi index e5966724f37c691ce871df9313e41c56ca84c419..b379623c1b8a0844c9de5255c46= 47fe3490bd2aa 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -43,90 +43,90 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x0>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; capacity-dmips-mhz =3D <1024>; clocks =3D <&kryocc 0>; interconnects =3D <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 =3D <&cluster0_opp>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x1>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; capacity-dmips-mhz =3D <1024>; clocks =3D <&kryocc 0>; interconnects =3D <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 =3D <&cluster0_opp>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU2: cpu@100 { + cpu2: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x100>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; capacity-dmips-mhz =3D <1024>; clocks =3D <&kryocc 1>; interconnects =3D <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 =3D <&cluster1_opp>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_1>; - L2_1: l2-cache { + next-level-cache =3D <&l2_1>; + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU3: cpu@101 { + cpu3: cpu@101 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x101>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; + cpu-idle-states =3D <&cpu_sleep_0>; capacity-dmips-mhz =3D <1024>; clocks =3D <&kryocc 1>; interconnects =3D <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 =3D <&cluster1_opp>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core1 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; }; @@ -134,7 +134,7 @@ core1 { idle-states { entry-method =3D "psci"; =20 - CPU_SLEEP_0: cpu-sleep-0 { + cpu_sleep_0: cpu-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "standalone-power-collapse"; arm,psci-suspend-param =3D <0x00000004>; @@ -2829,7 +2829,7 @@ debug@3810000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 etm@3840000 { @@ -2839,7 +2839,7 @@ etm@3840000 { clocks =3D <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 out-ports { port { @@ -2858,7 +2858,7 @@ debug@3910000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 etm@3940000 { @@ -2868,7 +2868,7 @@ etm@3940000 { clocks =3D <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 out-ports { port { @@ -2923,7 +2923,7 @@ debug@3a10000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 etm@3a40000 { @@ -2933,7 +2933,7 @@ etm@3a40000 { clocks =3D <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 out-ports { port { @@ -2952,7 +2952,7 @@ debug@3b10000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 etm@3b40000 { @@ -2962,7 +2962,7 @@ etm@3b40000 { clocks =3D <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 out-ports { port { diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/b= oot/dts/qcom/msm8998-clamshell.dtsi index 3b7172aa40374cb953fc27cc36546a897b748258..4748a093af2fc520e5e5273dcc4= 9d7721ffe5b3a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi @@ -61,36 +61,36 @@ cts-pins { * not advertised as enabled in ACPI, and enabling it in DT can cause boot * hangs. */ -&CPU0 { - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_1>; +&cpu0 { + cpu-idle-states =3D <&little_cpu_sleep_1>; }; =20 -&CPU1 { - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_1>; +&cpu1 { + cpu-idle-states =3D <&little_cpu_sleep_1>; }; =20 -&CPU2 { - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_1>; +&cpu2 { + cpu-idle-states =3D <&little_cpu_sleep_1>; }; =20 -&CPU3 { - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_1>; +&cpu3 { + cpu-idle-states =3D <&little_cpu_sleep_1>; }; =20 -&CPU4 { - cpu-idle-states =3D <&BIG_CPU_SLEEP_1>; +&cpu4 { + cpu-idle-states =3D <&big_cpu_sleep_1>; }; =20 -&CPU5 { - cpu-idle-states =3D <&BIG_CPU_SLEEP_1>; +&cpu5 { + cpu-idle-states =3D <&big_cpu_sleep_1>; }; =20 -&CPU6 { - cpu-idle-states =3D <&BIG_CPU_SLEEP_1>; +&cpu6 { + cpu-idle-states =3D <&big_cpu_sleep_1>; }; =20 -&CPU7 { - cpu-idle-states =3D <&BIG_CPU_SLEEP_1>; +&cpu7 { + cpu-idle-states =3D <&big_cpu_sleep_1>; }; =20 /* diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qc= om/msm8998.dtsi index 4952da36ba5935b1ed135cf2bbab1dc9b669868e..c2caad85c668df2ebe900bc560e= 39480ae03e353 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -136,130 +136,130 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x0>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + cpu-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x1>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache =3D <&L2_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + next-level-cache =3D <&l2_0>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x2>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache =3D <&L2_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + next-level-cache =3D <&l2_0>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x3>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache =3D <&L2_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + next-level-cache =3D <&l2_0>; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x100>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1536>; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache =3D <&L2_1>; - L2_1: l2-cache { + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + next-level-cache =3D <&l2_1>; + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x101>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1536>; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache =3D <&L2_1>; + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x102>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1536>; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache =3D <&L2_1>; + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "qcom,kryo280"; reg =3D <0x0 0x103>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1536>; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache =3D <&L2_1>; + cpu-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + next-level-cache =3D <&l2_1>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -267,7 +267,7 @@ core3 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-retention"; /* CPU Retention (C2D), L2 Active */ @@ -277,7 +277,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { min-residency-us =3D <504>; }; =20 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + little_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-power-collapse"; /* CPU + L2 Power Collapse (C3, D4) */ @@ -288,7 +288,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-retention"; /* CPU Retention (C2D), L2 Active */ @@ -298,7 +298,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { min-residency-us =3D <1302>; }; =20 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + big_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-power-collapse"; /* CPU + L2 Power Collapse (C3, D4) */ @@ -1874,7 +1874,7 @@ etm1: etm@7840000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 out-ports { port { @@ -1894,7 +1894,7 @@ etm2: etm@7940000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 out-ports { port { @@ -1914,7 +1914,7 @@ etm3: etm@7a40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 out-ports { port { @@ -1934,7 +1934,7 @@ etm4: etm@7b40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 out-ports { port { @@ -2068,7 +2068,7 @@ etm5: etm@7c40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 out-ports { port { @@ -2087,7 +2087,7 @@ etm6: etm@7d40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 out-ports { port { @@ -2106,7 +2106,7 @@ etm7: etm@7e40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 out-ports { port { @@ -2125,7 +2125,7 @@ etm8: etm@7f40000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 out-ports { port { diff --git a/arch/arm64/boot/dts/qcom/sdm632.dtsi b/arch/arm64/boot/dts/qco= m/sdm632.dtsi index 95b025ea260bdbc48e15496dda34cdd5a7f0a448..40d86d91b67fa02d100c108baf6= 06222c1c6c4df 100644 --- a/arch/arm64/boot/dts/qcom/sdm632.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm632.dtsi @@ -14,10 +14,10 @@ cpu0-thermal { =20 cooling-maps { map0 { - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -42,40 +42,40 @@ cpu7-thermal { =20 /* * SDM632 uses Kryo 250 instead of Cortex A53 - * CPU0-3 are efficiency cores, CPU4-7 are performance cores + * cpu0-3 are efficiency cores, cpu4-7 are performance cores */ -&CPU0 { +&cpu0 { compatible =3D "qcom,kryo250"; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase, but the labels are not used, so just drop them. Signed-off-by: Krzysztof Kozlowski --- Changes in v2: 1. New patch --- arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64= /boot/dts/qcom/msm8992-xiaomi-libra.dts index 133f9c2540bcab3eae9c5e6047f942ac5a5794ea..d0290a20b888ddcf5885f6c19fd= 5a687431be764 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -175,7 +175,7 @@ &blsp2_uart2 { }; =20 &pm8994_spmi_regulators { - VDD_APC0: s8 { + s8 { regulator-min-microvolt =3D <680000>; regulator-max-microvolt =3D <1180000>; regulator-always-on; @@ -183,7 +183,7 @@ VDD_APC0: s8 { }; =20 /* APC1 is 3-phase, but quoting downstream, s11 is "the gang leader" */ - VDD_APC1: s11 { + s11 { regulator-min-microvolt =3D <700000>; regulator-max-microvolt =3D <1225000>; regulator-always-on; --=20 2.43.0 From nobody Tue Nov 26 02:43:14 2024 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EA0B1B86EF for ; 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Tue, 22 Oct 2024 08:47:59 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5cb66c725fesm3439959a12.87.2024.10.22.08.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 08:47:58 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 22 Oct 2024 17:47:29 +0200 Subject: [PATCH v3 04/18] arm64: dts: qcom: sc7180: change labels to lower-case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-4-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi | 84 ++--- .../arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 8 +- .../boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 8 +- .../boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi | 8 +- arch/arm64/boot/dts/qcom/sc7180.dtsi | 362 ++++++++++-------= ---- arch/arm64/boot/dts/qcom/sm7125.dtsi | 16 +- 6 files changed, 243 insertions(+), 243 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi b/arch/arm64= /boot/dts/qcom/sc7180-firmware-tfa.dtsi index ee35a454dbf6f3272bec55636342e0605e8131a8..59162b3afcb841bae456e3c1dc2= 8371359a6e1f8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi @@ -6,82 +6,82 @@ * by Qualcomm firmware. */ =20 -&CPU0 { +&cpu0 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 + &little_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU1 { +&cpu1 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 + &little_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU2 { +&cpu2 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 + &little_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU3 { +&cpu3 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 + &little_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU4 { +&cpu4 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 + &little_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU5 { +&cpu5 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 + &little_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU6 { +&cpu6 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&big_cpu_sleep_0 + &big_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU7 { +&cpu7 { /delete-property/ power-domains; /delete-property/ power-domain-names; =20 - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&big_cpu_sleep_0 + &big_cpu_sleep_1 + &cluster_sleep_0>; }; =20 /delete-node/ &domain_idle_states; =20 &idle_states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "cluster-power-down"; arm,psci-suspend-param =3D <0x40003444>; @@ -92,15 +92,15 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { }; }; =20 -/delete-node/ &CPU_PD0; -/delete-node/ &CPU_PD1; -/delete-node/ &CPU_PD2; -/delete-node/ &CPU_PD3; -/delete-node/ &CPU_PD4; -/delete-node/ &CPU_PD5; -/delete-node/ &CPU_PD6; -/delete-node/ &CPU_PD7; -/delete-node/ &CLUSTER_PD; +/delete-node/ &cpu_pd0; +/delete-node/ &cpu_pd1; +/delete-node/ &cpu_pd2; +/delete-node/ &cpu_pd3; +/delete-node/ &cpu_pd4; +/delete-node/ &cpu_pd5; +/delete-node/ &cpu_pd6; +/delete-node/ &cpu_pd7; +/delete-node/ &cluster_pd; =20 &apps_rsc { /delete-property/ power-domains; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm= 64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 3c124bbe2f4c94989157aaa7de2a0dc78356f3e3..25b17b0425f24e9f4e8c94db300= 183cf3585b385 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -53,14 +53,14 @@ skin-temp-crit { cooling-maps { map0 { trip =3D <&skin_temp_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; =20 map1 { trip =3D <&skin_temp_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/a= rm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index b2df22faafe8890da1fc9f234e3c17474a453f28..f57976906d63040ee5aab7ea487= 02118f44824d2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -71,14 +71,14 @@ skin-temp-crit { cooling-maps { map0 { trip =3D <&skin_temp_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; =20 map1 { trip =3D <&skin_temp_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arc= h/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index af89d80426abbdcc702301ca84481202d0f2c60b..d4925be3b1fcf5219866f9754b5= bff3e45d84c08 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -78,14 +78,14 @@ skin-temp-crit { cooling-maps { map0 { trip =3D <&skin_temp_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; =20 map1 { trip =3D <&skin_temp_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index 899c7a3d7a4ce2448565fc0f59b0f5e93ccb4b89..76fe314d2ad50d002ee6adf4659= fa685ddae89de 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -77,28 +77,28 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -106,206 +106,206 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x300>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x400>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x500>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x600>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <480>; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo468"; reg =3D <0x0 0x700>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <480>; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -313,7 +313,7 @@ core7 { idle_states: idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-power-down"; arm,psci-suspend-param =3D <0x40000003>; @@ -323,7 +323,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + little_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-down"; arm,psci-suspend-param =3D <0x40000004>; @@ -333,7 +333,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-power-down"; arm,psci-suspend-param =3D <0x40000003>; @@ -343,7 +343,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + big_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-down"; arm,psci-suspend-param =3D <0x40000004>; @@ -355,7 +355,7 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 { }; =20 domain_idle_states: domain-idle-states { - CLUSTER_SLEEP_PC: cluster-sleep-0 { + cluster_sleep_pc: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <2752>; @@ -363,7 +363,7 @@ CLUSTER_SLEEP_PC: cluster-sleep-0 { min-residency-us =3D <6118>; }; =20 - CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + cluster_sleep_cx_ret: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41001244>; entry-latency-us =3D <3638>; @@ -371,7 +371,7 @@ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { min-residency-us =3D <8467>; }; =20 - CLUSTER_AOSS_SLEEP: cluster-sleep-2 { + cluster_aoss_sleep: cluster-sleep-2 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100b244>; entry-latency-us =3D <3263>; @@ -580,59 +580,59 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: cpu0 { + cpu_pd0: cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD1: cpu1 { + cpu_pd1: cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD2: cpu2 { + cpu_pd2: cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD3: cpu3 { + cpu_pd3: cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD4: cpu4 { + cpu_pd4: cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD5: cpu5 { + cpu_pd5: cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD6: cpu6 { + cpu_pd6: cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CPU_PD7: cpu7 { + cpu_pd7: cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CLUSTER_PD: cpu-cluster0 { + cluster_pd: cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_PC - &CLUSTER_SLEEP_CX_RET - &CLUSTER_AOSS_SLEEP>; + domain-idle-states =3D <&cluster_sleep_pc + &cluster_sleep_cx_ret + &cluster_aoss_sleep>; }; }; =20 @@ -2543,7 +2543,7 @@ etm@7040000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07040000 0 0x1000>; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2563,7 +2563,7 @@ etm@7140000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07140000 0 0x1000>; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2583,7 +2583,7 @@ etm@7240000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07240000 0 0x1000>; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2603,7 +2603,7 @@ etm@7340000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07340000 0 0x1000>; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2623,7 +2623,7 @@ etm@7440000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07440000 0 0x1000>; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2643,7 +2643,7 @@ etm@7540000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07540000 0 0x1000>; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2663,7 +2663,7 @@ etm@7640000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07640000 0 0x1000>; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2683,7 +2683,7 @@ etm@7740000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07740000 0 0x1000>; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3732,7 +3732,7 @@ apps_rsc: rsc@18200000 { , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 rpmhcc: clock-controller { compatible =3D "qcom,sc7180-rpmh-clk"; @@ -4061,21 +4061,21 @@ cpu0_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu0_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4109,21 +4109,21 @@ cpu1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu1_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu1_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4157,21 +4157,21 @@ cpu2_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu2_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4205,21 +4205,21 @@ cpu3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu3_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu3_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4253,21 +4253,21 @@ cpu4_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4301,21 +4301,21 @@ cpu5_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4349,13 +4349,13 @@ cpu6_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4389,13 +4389,13 @@ cpu7_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4429,13 +4429,13 @@ cpu8_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu8_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu8_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4469,13 +4469,13 @@ cpu9_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu9_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu9_alert1>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7125.dtsi b/arch/arm64/boot/dts/qco= m/sm7125.dtsi index 12dd72859a433ba375da4c2be1ca8406ccab179c..a53145a610a3c8ca4e69fb73e21= 47066a4f24315 100644 --- a/arch/arm64/boot/dts/qcom/sm7125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm7125.dtsi @@ -6,11 +6,11 @@ #include "sc7180.dtsi" =20 /* SM7125 uses Kryo 465 instead of Kryo 468 */ -&CPU0 { compatible =3D "qcom,kryo465"; }; -&CPU1 { compatible =3D "qcom,kryo465"; }; -&CPU2 { compatible =3D "qcom,kryo465"; }; -&CPU3 { compatible =3D "qcom,kryo465"; }; -&CPU4 { compatible =3D "qcom,kryo465"; }; -&CPU5 { compatible =3D "qcom,kryo465"; }; -&CPU6 { compatible =3D "qcom,kryo465"; }; -&CPU7 { compatible =3D "qcom,kryo465"; }; +&cpu0 { compatible =3D "qcom,kryo465"; }; +&cpu1 { compatible =3D "qcom,kryo465"; }; +&cpu2 { compatible =3D "qcom,kryo465"; }; +&cpu3 { compatible =3D "qcom,kryo465"; }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-5-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Steev Klimaszewski , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15073; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=AvFi3zJ8nbHyF+xnWeWAYOlSyVkYWvxWgfDU9xJPJtA=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kYiOT4OMZREAyy6Lslg3y1kO9XYwxpMOa2F 77ZIS+nSgeJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJGAAKCRDBN2bmhouD 1woBD/4iGhYzbWhCXBH8AoYAwLFo5kUX5tGA8l7JaSiWfWQWAVCxBBVlsfIJS4oDD4kOrHHCv2U Zj7ugVlhEzy1kivCvEvtJhU9SUMvSacr7PI8b8cSZ89fqHXc7jrNGrANsubl7pzVNwLfA/ScAcT 2kYnERuRE5Y0V3bz1frJL7gVqsYDbUp2QFw7pxQyouI905j/7whs5dVvZhkR9ERTMe4J61C00JZ xBBS93ubQ+96maV5a7sBlszcGckkyMfQgWcH0Av89i8CgqW81U6ma+cYS6L/ER1lcsHZwEKbhwN 8CiaJ3uBuCC8ci5QGcBdpG49K5HnmPjKdJB9h7OOmnuvsCVNxMrNiO9sdydG+DGMVvJbbIuG4Oa udZw/LdzqKPo++fOTf/QtRGieoxa76qBYqyICPIwEvwRQh6NO8NOa0GAjMKNWcYxqfbq6LqakDI q+6sGiHYxfv+qpdraKUqxnHL/xkEwH7GdjuvqDoPsy/FHeq8/7ZmnBohRpWfunIG/j6vX1S/9cH St2MyxlUwxTS6zWBaCqBuWMNIq72u55DoNaPgZucJSrFmuV1iL23YqBALUHWgwKYOOpmxvJJUOB WtZQ5rTxI9M68BcBXUONU1VJhwPu5fU849FAw0nLQqHe8D5IwB0HSWor4h4hUzTI9JppUrEBMuv d8g/ZZkTfkx/e3g== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Tested-by: Steev Klimaszewski Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. Update sc8280xp-microsoft-arcata.dts --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 16 +-- .../boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 16 +-- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 158 ++++++++++-------= ---- 3 files changed, 95 insertions(+), 95 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 6a28cab971891d327bf7fa5558a382799c178e6e..83208b10f994b282ed50c3ba8a8= 2298b6fc50deb 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -346,18 +346,18 @@ skin-temp-crit { cooling-maps { map0 { trip =3D <&skin_temp_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; =20 map1 { trip =3D <&skin_temp_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/= arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index a31742471f512e3e3992012d71206eb4f442a400..ae5daeac8fe284bbec86622c10e= 6831d60a25297 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -228,18 +228,18 @@ skin-temp-crit { cooling-maps { map0 { trip =3D <&skin_temp_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; =20 map1 { trip =3D <&skin_temp_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 495e2acc666a3cdcfaa3c5d87f9836e8759a18eb..2b98a8f0f899c2d7e3badec0a12= 2e8b3d4b897a2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -44,7 +44,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78c"; reg =3D <0x0 0x0>; @@ -52,19 +52,19 @@ CPU0: cpu@0 { enable-method =3D "psci"; capacity-dmips-mhz =3D <981>; dynamic-power-coefficient =3D <549>; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -72,7 +72,7 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78c"; reg =3D <0x0 0x100>; @@ -80,22 +80,22 @@ CPU1: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <981>; dynamic-power-coefficient =3D <549>; - next-level-cache =3D <&L2_100>; - power-domains =3D <&CPU_PD1>; + next-level-cache =3D <&l2_100>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78c"; reg =3D <0x0 0x200>; @@ -103,22 +103,22 @@ CPU2: cpu@200 { enable-method =3D "psci"; capacity-dmips-mhz =3D <981>; dynamic-power-coefficient =3D <549>; - next-level-cache =3D <&L2_200>; - power-domains =3D <&CPU_PD2>; + next-level-cache =3D <&l2_200>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78c"; reg =3D <0x0 0x300>; @@ -126,22 +126,22 @@ CPU3: cpu@300 { enable-method =3D "psci"; capacity-dmips-mhz =3D <981>; dynamic-power-coefficient =3D <549>; - next-level-cache =3D <&L2_300>; - power-domains =3D <&CPU_PD3>; + next-level-cache =3D <&l2_300>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-x1c"; reg =3D <0x0 0x400>; @@ -149,22 +149,22 @@ CPU4: cpu@400 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <590>; - next-level-cache =3D <&L2_400>; - power-domains =3D <&CPU_PD4>; + next-level-cache =3D <&l2_400>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-x1c"; reg =3D <0x0 0x500>; @@ -172,22 +172,22 @@ CPU5: cpu@500 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <590>; - next-level-cache =3D <&L2_500>; - power-domains =3D <&CPU_PD5>; + next-level-cache =3D <&l2_500>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-x1c"; reg =3D <0x0 0x600>; @@ -195,22 +195,22 @@ CPU6: cpu@600 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <590>; - next-level-cache =3D <&L2_600>; - power-domains =3D <&CPU_PD6>; + next-level-cache =3D <&l2_600>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "arm,cortex-x1c"; reg =3D <0x0 0x700>; @@ -218,53 +218,53 @@ CPU7: cpu@700 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <590>; - next-level-cache =3D <&L2_700>; - power-domains =3D <&CPU_PD7>; + next-level-cache =3D <&l2_700>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_= SHARED>; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -272,7 +272,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -282,7 +282,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -294,7 +294,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c344>; entry-latency-us =3D <3263>; @@ -593,57 +593,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>; + domain-idle-states =3D <&cluster_sleep_0>; }; }; =20 @@ -5160,7 +5160,7 @@ apps_rsc: rsc@18200000 { qcom,tcs-config =3D , , , ; label =3D "apps_rsc"; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; --=20 2.43.0 From nobody Tue Nov 26 02:43:14 2024 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 107341BC068 for ; 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Tue, 22 Oct 2024 08:48:04 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5cb66c725fesm3439959a12.87.2024.10.22.08.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 08:48:02 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 22 Oct 2024 17:47:31 +0200 Subject: [PATCH v3 06/18] arm64: dts: qcom: sc: change labels to lower-case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-6-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 6 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 374 ++++++++++-------= ---- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 164 ++++----- 3 files changed, 272 insertions(+), 272 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm6= 4/boot/dts/qcom/sc7280-chrome-common.dtsi index eb5e32035d937c412847626d2f2b1814ba258a8d..8b4239f13748fe591b68a163f37= 993f9e84c2de0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -29,7 +29,7 @@ / { cpus { domain_idle_states: domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x40003444>; entry-latency-us =3D <2752>; @@ -52,8 +52,8 @@ venus_mem: memory@8b200000 { }; }; =20 -&CLUSTER_PD { - domain-idle-states =3D <&CLUSTER_SLEEP_0>; +&cluster_pd { + domain-idle-states =3D <&cluster_sleep_0>; }; =20 &gpu { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 7c75340b3a46e609285e60c9246325b40e1383dc..77da825159b0ec2a9ac899697eb= 4f63d933d12b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -193,15 +193,15 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; operating-points-v2 =3D <&cpu0_opp_table>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; @@ -209,12 +209,12 @@ CPU0: cpu@0 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -222,15 +222,15 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; operating-points-v2 =3D <&cpu0_opp_table>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; @@ -238,23 +238,23 @@ CPU1: cpu@100 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; operating-points-v2 =3D <&cpu0_opp_table>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; @@ -262,23 +262,23 @@ CPU2: cpu@200 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x300>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; operating-points-v2 =3D <&cpu0_opp_table>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; @@ -286,23 +286,23 @@ CPU3: cpu@300 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x400>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; operating-points-v2 =3D <&cpu4_opp_table>; capacity-dmips-mhz =3D <1946>; dynamic-power-coefficient =3D <520>; @@ -310,23 +310,23 @@ CPU4: cpu@400 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x500>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; operating-points-v2 =3D <&cpu4_opp_table>; capacity-dmips-mhz =3D <1946>; dynamic-power-coefficient =3D <520>; @@ -334,23 +334,23 @@ CPU5: cpu@500 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x600>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; operating-points-v2 =3D <&cpu4_opp_table>; capacity-dmips-mhz =3D <1946>; dynamic-power-coefficient =3D <520>; @@ -358,23 +358,23 @@ CPU6: cpu@600 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x700>; clocks =3D <&cpufreq_hw 2>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; operating-points-v2 =3D <&cpu7_opp_table>; capacity-dmips-mhz =3D <1985>; dynamic-power-coefficient =3D <552>; @@ -382,46 +382,46 @@ CPU7: cpu@700 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 2>; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -429,7 +429,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-power-down"; arm,psci-suspend-param =3D <0x40000003>; @@ -439,7 +439,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + little_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-down"; arm,psci-suspend-param =3D <0x40000004>; @@ -449,7 +449,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-power-down"; arm,psci-suspend-param =3D <0x40000003>; @@ -459,7 +459,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + big_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-down"; arm,psci-suspend-param =3D <0x40000004>; @@ -471,7 +471,7 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 { }; =20 domain_idle_states: domain-idle-states { - CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { + cluster_sleep_apss_off: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <2752>; @@ -479,7 +479,7 @@ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { min-residency-us =3D <6118>; }; =20 - CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + cluster_sleep_cx_ret: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41001344>; entry-latency-us =3D <3263>; @@ -487,7 +487,7 @@ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { min-residency-us =3D <8467>; }; =20 - CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 { + cluster_sleep_llcc_off: cluster-sleep-2 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100b344>; entry-latency-us =3D <3638>; @@ -859,57 +859,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &= CLUSTER_SLEEP_LLCC_OFF>; + domain-idle-states =3D <&cluster_sleep_apss_off &cluster_sleep_cx_ret &= cluster_sleep_llcc_off>; }; }; =20 @@ -3285,7 +3285,7 @@ etm@7040000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07040000 0 0x1000>; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3305,7 +3305,7 @@ etm@7140000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07140000 0 0x1000>; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3325,7 +3325,7 @@ etm@7240000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07240000 0 0x1000>; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3345,7 +3345,7 @@ etm@7340000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07340000 0 0x1000>; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3365,7 +3365,7 @@ etm@7440000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07440000 0 0x1000>; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3385,7 +3385,7 @@ etm@7540000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07540000 0 0x1000>; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3405,7 +3405,7 @@ etm@7640000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07640000 0 0x1000>; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3425,7 +3425,7 @@ etm@7740000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07740000 0 0x1000>; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -6064,7 +6064,7 @@ apps_rsc: rsc@18200000 { , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; @@ -6184,17 +6184,17 @@ cpu0_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu0_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6227,17 +6227,17 @@ cpu1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu1_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu1_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6270,17 +6270,17 @@ cpu2_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu2_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6313,17 +6313,17 @@ cpu3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu3_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu3_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6356,17 +6356,17 @@ cpu4_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6399,17 +6399,17 @@ cpu5_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6442,17 +6442,17 @@ cpu6_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6485,17 +6485,17 @@ cpu7_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6528,17 +6528,17 @@ cpu8_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu8_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu8_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6571,17 +6571,17 @@ cpu9_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu9_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu9_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6614,17 +6614,17 @@ cpu10_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu10_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu10_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6657,17 +6657,17 @@ cpu11_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu11_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu11_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qc= om/sc8180x.dtsi index e80e0d3b77329836ec3c97e707c5659b9ad83325..717ec4ad63f3035b839d85fb1dd= 375fac9b0a2b7 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -42,28 +42,28 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x0>; enable-method =3D "psci"; capacity-dmips-mhz =3D <602>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -71,207 +71,207 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x100>; enable-method =3D "psci"; capacity-dmips-mhz =3D <602>; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; =20 - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; =20 }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x200>; enable-method =3D "psci"; capacity-dmips-mhz =3D <602>; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; =20 - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x300>; enable-method =3D "psci"; capacity-dmips-mhz =3D <602>; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; =20 - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-unified; cache-level =3D <2>; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x400>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; =20 - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-unified; cache-level =3D <2>; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x500>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; =20 - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-unified; cache-level =3D <2>; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x600>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; =20 - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-unified; cache-level =3D <2>; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x700>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; =20 - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-unified; cache-level =3D <2>; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -279,7 +279,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; arm,psci-suspend-param =3D <0x40000004>; entry-latency-us =3D <355>; @@ -288,7 +288,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; arm,psci-suspend-param =3D <0x40000004>; entry-latency-us =3D <2411>; @@ -299,7 +299,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { + cluster_sleep_apss_off: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <3300>; @@ -307,7 +307,7 @@ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { min-residency-us =3D <6000>; }; =20 - CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { + cluster_sleep_aoss_sleep: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100a344>; entry-latency-us =3D <3263>; @@ -541,57 +541,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLE= EP>; + domain-idle-states =3D <&cluster_sleep_apss_off &cluster_sleep_aoss_sle= ep>; }; }; =20 @@ -3790,7 +3790,7 @@ apps_rsc: rsc@18200000 { , ; label =3D "apps_rsc"; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; @@ -3868,7 +3868,7 @@ lmh@18350800 { compatible =3D "qcom,sc8180x-lmh"; reg =3D <0 0x18350800 0 0x400>; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm4250.dtsi | 16 ++-- arch/arm64/boot/dts/qcom/sm6115.dtsi | 152 +++++++++++++++++--------------= ---- 2 files changed, 84 insertions(+), 84 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qco= m/sm4250.dtsi index c5add8f44fc0f28bc775e392f1d5418eeb25b480..a0ed61925e12d63f8b9d2fb5d31= cc7480c85a66f 100644 --- a/arch/arm64/boot/dts/qcom/sm4250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi @@ -5,34 +5,34 @@ =20 #include "sm6115.dtsi" =20 -&CPU0 { +&cpu0 { compatible =3D "qcom,kryo240"; }; =20 -&CPU1 { +&cpu1 { compatible =3D "qcom,kryo240"; }; =20 -&CPU2 { +&cpu2 { compatible =3D "qcom,kryo240"; }; =20 -&CPU3 { +&cpu3 { compatible =3D "qcom,kryo240"; }; =20 -&CPU4 { +&cpu4 { compatible =3D "qcom,kryo240"; }; =20 -&CPU5 { +&cpu5 { compatible =3D "qcom,kryo240"; }; =20 -&CPU6 { +&cpu6 { compatible =3D "qcom,kryo240"; }; =20 -&CPU7 { +&cpu7 { compatible =3D "qcom,kryo240"; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index 41216cc319d65e34737b2e1e4376c6ac6bc1a646..abaabeb414396ff3c8dd001b474= 901f16cb722bf 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -40,7 +40,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x0>; @@ -48,18 +48,18 @@ CPU0: cpu@0 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x1>; @@ -67,13 +67,13 @@ CPU1: cpu@1 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x2>; @@ -81,13 +81,13 @@ CPU2: cpu@2 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x3>; @@ -95,13 +95,13 @@ CPU3: cpu@3 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x100>; @@ -109,18 +109,18 @@ CPU4: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1638>; dynamic-power-coefficient =3D <282>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; - L2_1: l2-cache { + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x101>; @@ -128,13 +128,13 @@ CPU5: cpu@101 { capacity-dmips-mhz =3D <1638>; dynamic-power-coefficient =3D <282>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x102>; @@ -142,13 +142,13 @@ CPU6: cpu@102 { capacity-dmips-mhz =3D <1638>; dynamic-power-coefficient =3D <282>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x103>; @@ -156,46 +156,46 @@ CPU7: cpu@103 { capacity-dmips-mhz =3D <1638>; dynamic-power-coefficient =3D <282>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -203,7 +203,7 @@ core3 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -213,7 +213,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -225,7 +225,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { + cluster_0_sleep_0: cluster-sleep-0-0 { /* GDHS */ compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x40000022>; @@ -234,7 +234,7 @@ CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { min-residency-us =3D <782>; }; =20 - CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { + cluster_0_sleep_1: cluster-sleep-0-1 { /* Power Collapse */ compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; @@ -243,7 +243,7 @@ CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { min-residency-us =3D <7376>; }; =20 - CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { + cluster_1_sleep_0: cluster-sleep-1-0 { /* GDHS */ compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x40000042>; @@ -252,7 +252,7 @@ CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { min-residency-us =3D <660>; }; =20 - CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { + cluster_1_sleep_1: cluster-sleep-1-1 { /* Power Collapse */ compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; @@ -306,62 +306,62 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_0_PD: power-domain-cpu-cluster0 { + cluster_0_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; + domain-idle-states =3D <&cluster_0_sleep_0>, <&cluster_0_sleep_1>; }; =20 - CLUSTER_1_PD: power-domain-cpu-cluster1 { + cluster_1_pd: power-domain-cpu-cluster1 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; + domain-idle-states =3D <&cluster_1_sleep_0>, <&cluster_1_sleep_1>; }; }; =20 @@ -2405,7 +2405,7 @@ etm@9040000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 status =3D "disabled"; =20 @@ -2426,7 +2426,7 @@ etm@9140000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 status =3D "disabled"; =20 @@ -2447,7 +2447,7 @@ etm@9240000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 status =3D "disabled"; =20 @@ -2468,7 +2468,7 @@ etm@9340000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 190 +++++++++++++++++--------------= ---- arch/arm64/boot/dts/qcom/sm7225.dtsi | 16 +-- 2 files changed, 103 insertions(+), 103 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 17d03045ff33e89e38c7bb65e0386df4c7223d25..2ca5a59ba4fb8a88b189aa906a3= 4995ec33ec4c7 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -45,7 +45,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x0>; @@ -53,21 +53,21 @@ CPU0: cpu@0 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -75,7 +75,7 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x100>; @@ -83,24 +83,24 @@ CPU1: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x200>; @@ -108,24 +108,24 @@ CPU2: cpu@200 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x300>; @@ -133,24 +133,24 @@ CPU3: cpu@300 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x400>; @@ -158,24 +158,24 @@ CPU4: cpu@400 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x500>; @@ -183,24 +183,24 @@ CPU5: cpu@500 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x600>; @@ -208,24 +208,24 @@ CPU6: cpu@600 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <703>; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo560"; reg =3D <0x0 0x700>; @@ -233,61 +233,61 @@ CPU7: cpu@700 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <703>; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; =20 domain-idle-states { - CLUSTER_SLEEP_PC: cluster-sleep-0 { + cluster_sleep_pc: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <2752>; @@ -295,7 +295,7 @@ CLUSTER_SLEEP_PC: cluster-sleep-0 { min-residency-us =3D <6118>; }; =20 - CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + cluster_sleep_cx_ret: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41001244>; entry-latency-us =3D <3638>; @@ -303,7 +303,7 @@ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { min-residency-us =3D <8467>; }; =20 - CLUSTER_AOSS_SLEEP: cluster-sleep-2 { + cluster_aoss_sleep: cluster-sleep-2 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100b244>; entry-latency-us =3D <3263>; @@ -315,7 +315,7 @@ CLUSTER_AOSS_SLEEP: cluster-sleep-2 { cpu_idle_states: idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -325,7 +325,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + little_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -335,7 +335,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -345,7 +345,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + big_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -504,59 +504,59 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_PC - &CLUSTER_SLEEP_CX_RET - &CLUSTER_AOSS_SLEEP>; + domain-idle-states =3D <&cluster_sleep_pc + &cluster_sleep_cx_ret + &cluster_aoss_sleep>; }; }; =20 @@ -2777,7 +2777,7 @@ apps_rsc: rsc@18200000 { qcom,drv-id =3D <2>; qcom,tcs-config =3D , , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 rpmhcc: clock-controller { compatible =3D "qcom,sm6350-rpmh-clk"; @@ -2954,7 +2954,7 @@ cpu0-crit { cooling-maps { map0 { trip =3D <&cpu0_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -2979,7 +2979,7 @@ cpu1-crit { cooling-maps { map0 { trip =3D <&cpu1_alert0>; - cooling-device =3D <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3004,7 +3004,7 @@ cpu2-crit { cooling-maps { map0 { trip =3D <&cpu2_alert0>; - cooling-device =3D <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3029,7 +3029,7 @@ cpu3-crit { cooling-maps { map0 { trip =3D <&cpu3_alert0>; - cooling-device =3D <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3054,7 +3054,7 @@ cpu4-crit { cooling-maps { map0 { trip =3D <&cpu4_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3079,7 +3079,7 @@ cpu5-crit { cooling-maps { map0 { trip =3D <&cpu5_alert0>; - cooling-device =3D <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3104,7 +3104,7 @@ cpu6-left-crit { cooling-maps { map0 { trip =3D <&cpu6_left_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3129,7 +3129,7 @@ cpu6-right-crit { cooling-maps { map0 { trip =3D <&cpu6_right_alert0>; - cooling-device =3D <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3154,7 +3154,7 @@ cpu7-left-crit { cooling-maps { map0 { trip =3D <&cpu7_left_alert0>; - cooling-device =3D <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3179,7 +3179,7 @@ cpu7-right-crit { cooling-maps { map0 { trip =3D <&cpu7_right_alert0>; - cooling-device =3D <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225.dtsi b/arch/arm64/boot/dts/qco= m/sm7225.dtsi index b7b4044e9bb0cb25e01b782acffd1e0069ed6a6b..a8ffdfb254fe61245a0b073b41e= 6db172e6b5415 100644 --- a/arch/arm64/boot/dts/qcom/sm7225.dtsi +++ b/arch/arm64/boot/dts/qcom/sm7225.dtsi @@ -6,14 +6,14 @@ #include "sm6350.dtsi" =20 /* SM7225 uses Kryo 570 instead of Kryo 560 */ -&CPU0 { compatible =3D "qcom,kryo570"; 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Tue, 22 Oct 2024 08:48:11 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5cb66c725fesm3439959a12.87.2024.10.22.08.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 08:48:10 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 22 Oct 2024 17:47:34 +0200 Subject: [PATCH v3 09/18] arm64: dts: qcom: sm8150: change labels to lower-case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-9-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 370 +++++++++++++++++--------------= ---- 1 file changed, 185 insertions(+), 185 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 28e57ad885f4f64abbf429c337d45504ff2830ad..cedae8d03a519e252e0ca9c1137= d1a0b9b8a6e6a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -48,7 +48,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x0>; @@ -56,20 +56,20 @@ CPU0: cpu@0 { enable-method =3D "psci"; capacity-dmips-mhz =3D <488>; dynamic-power-coefficient =3D <232>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -77,7 +77,7 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x100>; @@ -85,23 +85,23 @@ CPU1: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <488>; dynamic-power-coefficient =3D <232>; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x200>; @@ -109,23 +109,23 @@ CPU2: cpu@200 { enable-method =3D "psci"; capacity-dmips-mhz =3D <488>; dynamic-power-coefficient =3D <232>; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x300>; @@ -133,23 +133,23 @@ CPU3: cpu@300 { enable-method =3D "psci"; capacity-dmips-mhz =3D <488>; dynamic-power-coefficient =3D <232>; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x400>; @@ -157,23 +157,23 @@ CPU4: cpu@400 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <369>; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x500>; @@ -181,23 +181,23 @@ CPU5: cpu@500 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <369>; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x600>; @@ -205,23 +205,23 @@ CPU6: cpu@600 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <369>; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x700>; @@ -229,54 +229,54 @@ CPU7: cpu@700 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <421>; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; qcom,freq-domain =3D <&cpufreq_hw 2>; operating-points-v2 =3D <&cpu7_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -284,7 +284,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -294,7 +294,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -306,7 +306,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c244>; entry-latency-us =3D <3263>; @@ -628,57 +628,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>; + domain-idle-states =3D <&cluster_sleep_0>; }; }; =20 @@ -3096,7 +3096,7 @@ etm@7040000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07040000 0 0x1000>; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3116,7 +3116,7 @@ etm@7140000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07140000 0 0x1000>; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3136,7 +3136,7 @@ etm@7240000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07240000 0 0x1000>; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3156,7 +3156,7 @@ etm@7340000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07340000 0 0x1000>; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3176,7 +3176,7 @@ etm@7440000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07440000 0 0x1000>; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3196,7 +3196,7 @@ etm@7540000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07540000 0 0x1000>; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3216,7 +3216,7 @@ etm@7640000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07640000 0 0x1000>; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3236,7 +3236,7 @@ etm@7740000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07740000 0 0x1000>; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -4458,7 +4458,7 @@ apps_rsc: rsc@18200000 { , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 rpmhcc: clock-controller { compatible =3D "qcom,sm8150-rpmh-clk"; @@ -4554,7 +4554,7 @@ lmh_cluster1: lmh@18350800 { compatible =3D "qcom,sm8150-lmh"; reg =3D <0 0x18350800 0 0x400>; interrupts =3D ; - cpus =3D <&CPU4>; + cpus =3D <&cpu4>; qcom,lmh-temp-arm-millicelsius =3D <60000>; qcom,lmh-temp-low-millicelsius =3D <84500>; qcom,lmh-temp-high-millicelsius =3D <85000>; @@ -4566,7 +4566,7 @@ lmh_cluster0: lmh@18358800 { compatible =3D "qcom,sm8150-lmh"; reg =3D <0 0x18358800 0 0x400>; interrupts =3D ; - cpus =3D <&CPU0>; + cpus =3D <&cpu0>; qcom,lmh-temp-arm-millicelsius =3D <60000>; qcom,lmh-temp-low-millicelsius =3D <84500>; qcom,lmh-temp-high-millicelsius =3D <85000>; @@ -4635,17 +4635,17 @@ cpu0_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu0_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4678,17 +4678,17 @@ cpu1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu1_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu1_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4721,17 +4721,17 @@ cpu2_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu2_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4764,17 +4764,17 @@ cpu3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu3_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu3_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4807,17 +4807,17 @@ cpu4_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4850,17 +4850,17 @@ cpu5_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4893,17 +4893,17 @@ cpu6_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4936,17 +4936,17 @@ cpu7_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4979,17 +4979,17 @@ cpu4_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -5022,17 +5022,17 @@ cpu5_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -5065,17 +5065,17 @@ cpu6_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -5108,17 +5108,17 @@ cpu7_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; --=20 2.43.0 From nobody Tue Nov 26 02:43:14 2024 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4168E1BD4F9 for ; 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Tue, 22 Oct 2024 08:48:13 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5cb66c725fesm3439959a12.87.2024.10.22.08.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 08:48:12 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 22 Oct 2024 17:47:35 +0200 Subject: [PATCH v3 10/18] arm64: dts: qcom: sm8250: change labels to lower-case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-10-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 4 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 366 +++++++++++++++------------= ---- 2 files changed, 185 insertions(+), 185 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts= /qcom/qrb5165-rb5.dts index ccff6cd73fdfab52707b53473b1d989a0ce25a9d..52eef88e882c356a62bf563fcd7= ce3d54b5ea824 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -32,7 +32,7 @@ chosen { }; =20 /* Fixed crystal oscillator dedicated to MCP2518FD */ - clk40M: can-clock { + clk40m: can-clock { compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <40000000>; @@ -1118,7 +1118,7 @@ &spi0 { can@0 { compatible =3D "microchip,mcp2518fd"; reg =3D <0>; - clocks =3D <&clk40M>; + clocks =3D <&clk40m>; interrupts-extended =3D <&tlmm 15 IRQ_TYPE_LEVEL_LOW>; spi-max-frequency =3D <10000000>; vdd-supply =3D <&vdc_5v>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 630f4eff20bf810e347685066dce74ab92a23b56..48318ed1ce98ab40de75129cb9b= dfe32eda4c004 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -93,7 +93,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x0>; @@ -101,21 +101,21 @@ CPU0: cpu@0 { enable-method =3D "psci"; capacity-dmips-mhz =3D <448>; dynamic-power-coefficient =3D <105>; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x20000>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-size =3D <0x400000>; @@ -124,7 +124,7 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x100>; @@ -132,24 +132,24 @@ CPU1: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <448>; dynamic-power-coefficient =3D <105>; - next-level-cache =3D <&L2_100>; - power-domains =3D <&CPU_PD1>; + next-level-cache =3D <&l2_100>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x20000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x200>; @@ -157,24 +157,24 @@ CPU2: cpu@200 { enable-method =3D "psci"; capacity-dmips-mhz =3D <448>; dynamic-power-coefficient =3D <105>; - next-level-cache =3D <&L2_200>; - power-domains =3D <&CPU_PD2>; + next-level-cache =3D <&l2_200>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x20000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x300>; @@ -182,24 +182,24 @@ CPU3: cpu@300 { enable-method =3D "psci"; capacity-dmips-mhz =3D <448>; dynamic-power-coefficient =3D <105>; - next-level-cache =3D <&L2_300>; - power-domains =3D <&CPU_PD3>; + next-level-cache =3D <&l2_300>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x20000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x400>; @@ -207,24 +207,24 @@ CPU4: cpu@400 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <379>; - next-level-cache =3D <&L2_400>; - power-domains =3D <&CPU_PD4>; + next-level-cache =3D <&l2_400>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x40000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x500>; @@ -232,24 +232,24 @@ CPU5: cpu@500 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <379>; - next-level-cache =3D <&L2_500>; - power-domains =3D <&CPU_PD5>; + next-level-cache =3D <&l2_500>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x40000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x600>; @@ -257,24 +257,24 @@ CPU6: cpu@600 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <379>; - next-level-cache =3D <&L2_600>; - power-domains =3D <&CPU_PD6>; + next-level-cache =3D <&l2_600>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x40000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x700>; @@ -282,55 +282,55 @@ CPU7: cpu@700 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <444>; - next-level-cache =3D <&L2_700>; - power-domains =3D <&CPU_PD7>; + next-level-cache =3D <&l2_700>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 2>; operating-points-v2 =3D <&cpu7_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x80000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -338,7 +338,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -348,7 +348,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -360,7 +360,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c244>; entry-latency-us =3D <3264>; @@ -689,57 +689,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>; + domain-idle-states =3D <&cluster_sleep_0>; }; }; =20 @@ -3522,7 +3522,7 @@ etm@7040000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07040000 0 0x1000>; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3541,7 +3541,7 @@ etm@7140000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07140000 0 0x1000>; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3560,7 +3560,7 @@ etm@7240000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07240000 0 0x1000>; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3579,7 +3579,7 @@ etm@7340000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07340000 0 0x1000>; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3598,7 +3598,7 @@ etm@7440000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07440000 0 0x1000>; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3617,7 +3617,7 @@ etm@7540000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07540000 0 0x1000>; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3636,7 +3636,7 @@ etm@7640000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07640000 0 0x1000>; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3655,7 +3655,7 @@ etm@7740000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07740000 0 0x1000>; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -6165,7 +6165,7 @@ apps_rsc: rsc@18200000 { qcom,drv-id =3D <2>; qcom,tcs-config =3D , , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 rpmhcc: clock-controller { compatible =3D "qcom,sm8250-rpmh-clk"; @@ -6302,17 +6302,17 @@ cpu0_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu0_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6345,17 +6345,17 @@ cpu1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu1_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu1_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6388,17 +6388,17 @@ cpu2_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu2_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6431,17 +6431,17 @@ cpu3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu3_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu3_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6474,17 +6474,17 @@ cpu4_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6517,17 +6517,17 @@ cpu5_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6560,17 +6560,17 @@ cpu6_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6603,17 +6603,17 @@ cpu7_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6646,17 +6646,17 @@ cpu4_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6689,17 +6689,17 @@ cpu5_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6732,17 +6732,17 @@ cpu6_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6775,17 +6775,17 @@ cpu7_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-11-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=23867; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=gAsrCSwbKGwlFSrxL8881rHmfxVVltqWLQbDV89byO0=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kdT764If2xKW/1nCutA3WHIpwLG8reedlsn t4Ci3rhN7SJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJHQAKCRDBN2bmhouD 1w64EACV9rvEGKrsDpVFR1dd1PnIR16sEmZaLF20DkjvfoWclOt0nU2S8IbJm2blDxgPs0p9nK7 xQ2AhZfhAcJM+Ovt84J/XeqrJ6oKNIUdtyLQzApsaSHsYnVLGkvlS6UfB2TKuHMc5PK4E2XNjm9 LTqjJA3sH+vsbazEmDt4tTP6gHZ4d5MPX6jTLyXRixxWE9LpRTfppl5mMiM2l+LNV+6YX7uDl9s GNb0zoC0Xh/9n2qFotWTqIGOeyS1OHpxZYOeu/UV1LZPtgEsUOj3Fkhx12SC1j9vW22X5G7YwBP XhSyljQH+jrKym6oADxsIqBEOwMI7Fw1CKMwUK8MoDyZTzg2JjVYuFwKt6JRPlQmYh7XBzZ7FWU m4aRL97PDUVNx/MuqzFKxSr4k0y7hOX4vOZOYdFc45+DMddmqkl929bIMi3T6qj0Y0kAAvwAvUW LL9FevvxvQaycmNP0bKtPcrLWS5kCvjsr3Tb8LzLHfH9zFmptnc9nf9BrITBwRR1sgXTCS3abiE Z+PAg8Bp77yC1xmj0/QyKkzx1WtBvAZtUtyfwmiDabmpUJKNoRmiG93iR9SFJxnOIUJhhLr4vGq BCJ4mF27A9yTUpb1xE0I3kzBpeRUYMhCptB+CGSncwS7O7JihzQCFSoiUdL9JqYRqrsaPLECMrz L4ct4OmBHpQ50LA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 352 +++++++++++++++++--------------= ---- 1 file changed, 176 insertions(+), 176 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 3156aff90f16b32e8458bcc9a93e6fa6084c5a09..877905dfd861edbcd083e6691a7= cfa1279164ffc 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -51,23 +51,23 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -75,171 +75,171 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x300>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78"; reg =3D <0x0 0x400>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78"; reg =3D <0x0 0x500>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78"; reg =3D <0x0 0x600>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "arm,cortex-x1"; reg =3D <0x0 0x700>; clocks =3D <&cpufreq_hw 2>; enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; qcom,freq-domain =3D <&cpufreq_hw 2>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -247,7 +247,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -257,7 +257,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -269,7 +269,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { + cluster_sleep_apss_off: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <2752>; @@ -277,7 +277,7 @@ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { min-residency-us =3D <6118>; }; =20 - CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { + cluster_sleep_aoss_sleep: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c344>; entry-latency-us =3D <3263>; @@ -320,57 +320,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLE= EP>; + domain-idle-states =3D <&cluster_sleep_apss_off &cluster_sleep_aoss_sle= ep>; }; }; =20 @@ -3505,7 +3505,7 @@ apps_rsc: rsc@18200000 { qcom,drv-id =3D <2>; qcom,tcs-config =3D , , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 rpmhcc: clock-controller { compatible =3D "qcom,sm8350-rpmh-clk"; @@ -3729,17 +3729,17 @@ cpu0_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu0_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3772,17 +3772,17 @@ cpu1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu1_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu1_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3815,17 +3815,17 @@ cpu2_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu2_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3858,17 +3858,17 @@ cpu3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu3_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu3_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3901,17 +3901,17 @@ cpu4_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3944,17 +3944,17 @@ cpu5_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3987,17 +3987,17 @@ cpu6_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4030,17 +4030,17 @@ cpu7_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4073,17 +4073,17 @@ cpu4_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4116,17 +4116,17 @@ cpu5_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4159,17 +4159,17 @@ cpu6_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -4202,17 +4202,17 @@ cpu7_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 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Tue, 22 Oct 2024 08:48:15 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 22 Oct 2024 17:47:37 +0200 Subject: [PATCH v3 12/18] arm64: dts: qcom: sm8450: change labels to lower-case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-12-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10625; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=iPL390E5JLXtD3wTFEtOSzANh7PbtLmD4GW7T04H1Gs=; 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No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 160 +++++++++++++++++--------------= ---- 1 file changed, 80 insertions(+), 80 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 1b5dc5b8cecb94cc1ac637cb929ab0d25eeb0b7c..e2601ea4ce42936d53a6df50492= a3f361a44ef53 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -51,23 +51,23 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo780"; reg =3D <0x0 0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -75,171 +75,171 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo780"; reg =3D <0x0 0x100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_100>; - power-domains =3D <&CPU_PD1>; + next-level-cache =3D <&l2_100>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo780"; reg =3D <0x0 0x200>; enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; - power-domains =3D <&CPU_PD2>; + next-level-cache =3D <&l2_200>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo780"; reg =3D <0x0 0x300>; enable-method =3D "psci"; - next-level-cache =3D <&L2_300>; - power-domains =3D <&CPU_PD3>; + next-level-cache =3D <&l2_300>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo780"; reg =3D <0x0 0x400>; enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; - power-domains =3D <&CPU_PD4>; + next-level-cache =3D <&l2_400>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo780"; reg =3D <0x0 0x500>; enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; - power-domains =3D <&CPU_PD5>; + next-level-cache =3D <&l2_500>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo780"; reg =3D <0x0 0x600>; enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; - power-domains =3D <&CPU_PD6>; + next-level-cache =3D <&l2_600>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo780"; reg =3D <0x0 0x700>; enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; - power-domains =3D <&CPU_PD7>; + next-level-cache =3D <&l2_700>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 2>; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -247,7 +247,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -257,7 +257,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -269,7 +269,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <1050>; @@ -277,7 +277,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { min-residency-us =3D <5309>; }; =20 - CLUSTER_SLEEP_1: cluster-sleep-1 { + cluster_sleep_1: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c344>; entry-latency-us =3D <2700>; @@ -323,57 +323,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; + domain-idle-states =3D <&cluster_sleep_0>, <&cluster_sleep_1>; }; }; =20 @@ -4354,7 +4354,7 @@ apps_rsc: rsc@17a00000 { qcom,drv-id =3D <2>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-13-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11525; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=fdf5q7Kdg5agvSReu+CjfGcEHicH6nlf1t2RIbqvN1I=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kfZCwdQUtnoJZTzVx95Q4Oy8Z9Vh8f7Fvue DrohB/TiTCJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJHwAKCRDBN2bmhouD 14xYD/oDqHPB1D03/2Vuzud1vu1jfBDzrFRB4sWdmF+M/5t+WpTe9bxX60TaaU7PVeUe29pjRDU Ckxu08/Fm93ogTTMPl4poD9SH0so6cjQoReaqRO0bH30+Ukae2v4d/0Sp2l2pBmPB1geGUnyBAc fX/e59mK0AKHKxnTpopToAqsmXlVulxkkzp46hWtJokmLzyasH9DMaDGJz2vXrJoskUSmVVvDDk bYJfBxc9NNlU/NHW3yX9PQFKUyzwLEA0aMtcXdv6WGC6ZcsypzTnO8Ipl+v+Fhn5Xn1+kVO0eNK H2FgDlOOdaMazb6hs06MDEZ8zD/t1YA+og/gI8yUii0P6CFwkFqZACsuZQaigN50sR38YNN35Zy ScJI+JNebAJ30KcE0Hjr9a6fyp2QOXAwLQEA1tFiiaf1jqD1dv783z2tJglY1WPy74KElG2cl5O GhTMzct1D9ZxBGfJgvXFzO4IMR0KfetCwqctSpcn6GspjEdas25VzVRwof+vj1lxytRzX/IUFs8 d/OCNLxnu96Px4jAnXfrfgHPmmnXRoBzIOif5Kk4nRIxt6bZBf0n/zdYz2kCbPa7TPEC3C3gUD1 GZKBUvrfk4pJwUZQV7A9/CRf19o/e+oUSyDHD5EsdnUZ1Tq2bHskYIWxAW2iTfJBFylTkvEH0Wp 3ndR8CTUXMHrJ/A== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 162 +++++++++++++++++--------------= ---- 1 file changed, 81 insertions(+), 81 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 93c8aa32e411b4aecb3140110073f422b407bf80..9d2ee372b225783c0fd2acc0fe2= 3329fa42abb12 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -64,25 +64,25 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a510"; reg =3D <0 0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -90,185 +90,185 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a510"; reg =3D <0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_100>; - power-domains =3D <&CPU_PD1>; + next-level-cache =3D <&l2_100>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a510"; reg =3D <0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; - power-domains =3D <&CPU_PD2>; + next-level-cache =3D <&l2_200>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a715"; reg =3D <0 0x300>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_300>; - power-domains =3D <&CPU_PD3>; + next-level-cache =3D <&l2_300>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a715"; reg =3D <0 0x400>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; - power-domains =3D <&CPU_PD4>; + next-level-cache =3D <&l2_400>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a710"; reg =3D <0 0x500>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; - power-domains =3D <&CPU_PD5>; + next-level-cache =3D <&l2_500>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-a710"; reg =3D <0 0x600>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; - power-domains =3D <&CPU_PD6>; + next-level-cache =3D <&l2_600>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "arm,cortex-x3"; reg =3D <0 0x700>; clocks =3D <&cpufreq_hw 2>; enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; - power-domains =3D <&CPU_PD7>; + next-level-cache =3D <&l2_700>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 2>; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <588>; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -276,7 +276,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -286,7 +286,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -296,7 +296,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { + prime_cpu_sleep_0: cpu-sleep-2-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "goldplus-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -308,7 +308,7 @@ PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <750>; @@ -316,7 +316,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { min-residency-us =3D <9144>; }; =20 - CLUSTER_SLEEP_1: cluster-sleep-1 { + cluster_sleep_1: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c344>; entry-latency-us =3D <2800>; @@ -376,57 +376,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 156 +++++++++++++++++--------------= ---- 1 file changed, 78 insertions(+), 78 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 3d8a807a81c9c15eeeaadf624a8e7f085b68ae9e..0c2b2a12663363b7d35eec89051= 697d69aba287d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -68,18 +68,18 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a520"; reg =3D <0 0>; =20 clocks =3D <&cpufreq_hw 0>; =20 - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; =20 @@ -87,13 +87,13 @@ CPU0: cpu@0 { =20 #cooling-cells =3D <2>; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; =20 - L3_0: l3-cache { + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -101,18 +101,18 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a520"; reg =3D <0 0x100>; =20 clocks =3D <&cpufreq_hw 0>; =20 - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; =20 @@ -121,18 +121,18 @@ CPU1: cpu@100 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x200>; =20 clocks =3D <&cpufreq_hw 3>; =20 - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -140,26 +140,26 @@ CPU2: cpu@200 { =20 #cooling-cells =3D <2>; =20 - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x300>; =20 clocks =3D <&cpufreq_hw 3>; =20 - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -168,18 +168,18 @@ CPU3: cpu@300 { #cooling-cells =3D <2>; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x400>; =20 clocks =3D <&cpufreq_hw 3>; =20 - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -187,26 +187,26 @@ CPU4: cpu@400 { =20 #cooling-cells =3D <2>; =20 - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x500>; =20 clocks =3D <&cpufreq_hw 1>; =20 - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -214,26 +214,26 @@ CPU5: cpu@500 { =20 #cooling-cells =3D <2>; =20 - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-a720"; reg =3D <0 0x600>; =20 clocks =3D <&cpufreq_hw 1>; =20 - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <238>; =20 @@ -241,26 +241,26 @@ CPU6: cpu@600 { =20 #cooling-cells =3D <2>; =20 - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "arm,cortex-x4"; reg =3D <0 0x700>; =20 clocks =3D <&cpufreq_hw 2>; =20 - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; =20 enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <588>; =20 @@ -268,46 +268,46 @@ CPU7: cpu@700 { =20 #cooling-cells =3D <2>; =20 - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -315,7 +315,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { + silver_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -325,7 +325,7 @@ SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { + gold_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -335,7 +335,7 @@ GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { + gold_plus_cpu_sleep_0: cpu-sleep-2-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-plus-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -347,7 +347,7 @@ GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <750>; @@ -355,7 +355,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { min-residency-us =3D <9144>; }; =20 - CLUSTER_SLEEP_1: cluster-sleep-1 { + cluster_sleep_1: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c344>; entry-latency-us =3D <2800>; @@ -411,58 +411,58 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&SILVER_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&SILVER_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&SILVER_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>; 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Tue, 22 Oct 2024 08:48:21 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5cb66c725fesm3439959a12.87.2024.10.22.08.48.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 08:48:20 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 22 Oct 2024 17:47:40 +0200 Subject: [PATCH v3 15/18] arm64: dts: qcom: sm: change labels to lower-case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-15-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 4 +- arch/arm64/boot/dts/qcom/sm4450.dtsi | 160 +++++++++++++++------------= ---- arch/arm64/boot/dts/qcom/sm6125.dtsi | 52 +++++----- arch/arm64/boot/dts/qcom/sm6375.dtsi | 160 +++++++++++++++------------= ---- 4 files changed, 188 insertions(+), 188 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts= /qcom/qrb4210-rb2.dts index 1888d99d398b11fc54ee43998721722e8eb9d10a..a9540e92d3e6fc314fa91d4f055= 325680233f6c4 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -25,7 +25,7 @@ chosen { }; =20 clocks { - clk40M: can-clk { + clk40m: can-clk { compatible =3D "fixed-clock"; clock-frequency =3D <40000000>; #clock-cells =3D <0>; @@ -537,7 +537,7 @@ can@0 { compatible =3D "microchip,mcp2518fd"; reg =3D <0>; interrupts-extended =3D <&tlmm 39 IRQ_TYPE_LEVEL_LOW>; - clocks =3D <&clk40M>; + clocks =3D <&clk40m>; spi-max-frequency =3D <10000000>; vdd-supply =3D <&vdc_5v>; xceiver-supply =3D <&vdc_5v>; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qco= m/sm4450.dtsi index 1e05cd00b635ee803857cb9107e1406520f016f5..a0de5fe16faae5674efb0070d40= 17983c86603c4 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -46,25 +46,25 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; =20 - L3_0: l3-cache { + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -72,178 +72,178 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_100>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_100>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; =20 - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_200>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; =20 - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x300>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_300>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_300>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; =20 - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x400>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_400>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; =20 - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x500>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_500>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; =20 - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78"; reg =3D <0x0 0x600>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_600>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; =20 - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "arm,cortex-a78"; reg =3D <0x0 0x700>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_700>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; =20 - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -251,7 +251,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; arm,psci-suspend-param =3D <0x40000004>; entry-latency-us =3D <800>; @@ -260,7 +260,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; arm,psci-suspend-param =3D <0x40000004>; entry-latency-us =3D <600>; @@ -271,7 +271,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <1050>; @@ -279,7 +279,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { min-residency-us =3D <5309>; }; =20 - CLUSTER_SLEEP_1: cluster-sleep-1 { + cluster_sleep_1: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41003344>; entry-latency-us =3D <1561>; @@ -309,57 +309,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; + domain-idle-states =3D <&cluster_sleep_0>, <&cluster_sleep_1>; }; }; =20 @@ -579,7 +579,7 @@ apps_rsc: rsc@17a00000 { qcom,drv-id =3D <2>; qcom,tcs-config =3D , , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qco= m/sm6125.dtsi index 133610d14fc41a524a2d570ccdad621155342728..1a4e196391a66199a2ff8020016= 37df0bd47cff5 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -37,122 +37,122 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x0>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x1>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x2>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x3>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x100>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1638>; - next-level-cache =3D <&L2_1>; - L2_1: l2-cache { + next-level-cache =3D <&l2_1>; + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x101>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1638>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x102>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1638>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x103>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1638>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qco= m/sm6375.dtsi index 4d519dd6e7ef2f9c13a3c26da185ddbdfd2f334d..e0b1c54e98c0e8d244b5f658eae= e2af5001c3855 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -38,25 +38,25 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo660"; reg =3D <0x0 0x0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L= 3_SHARED>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -64,185 +64,185 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo660"; reg =3D <0x0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L= 3_SHARED>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo660"; reg =3D <0x0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L= 3_SHARED>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo660"; reg =3D <0x0 0x300>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L= 3_SHARED>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo660"; reg =3D <0x0 0x400>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L= 3_SHARED>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo660"; reg =3D <0x0 0x500>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L= 3_SHARED>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo660"; reg =3D <0x0 0x600>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L= 3_SHARED>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo660"; reg =3D <0x0 0x700>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L= 3_SHARED>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -250,7 +250,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -260,7 +260,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + little_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -270,7 +270,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -280,7 +280,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + big_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -292,7 +292,7 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <2752>; @@ -455,58 +455,58 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; power-domains =3D <&mpm>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>; + domain-idle-states =3D <&cluster_sleep_0>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241022-dts-qcom-label-v3-16-0505bc7d2c56@linaro.org> References: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> In-Reply-To: <20241022-dts-qcom-label-v3-0-0505bc7d2c56@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=40126; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=z2V+4u1LWPFrmfIjYgSrcFfj6WxI1KiZdRtfHazDVYY=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnF8kiJFhmj4Wb9sRbBcGvxIdsS/uhn7p2cM4Rd XorrWzp02+JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZxfJIgAKCRDBN2bmhouD 16dQD/4iGRXrGozwZcMaNFm5HtZJ097je7vdF8M6U9rDw3sF0dIRv/GLGTiCtdRaOh/fIsbwApv RFkTPrjYoAjU8wU/ytuiEWvjmGMabpI68cxnHhLtZL8peD192g0z4SjXpcOgw/xU3zjwXcVk9VW uY3+PKlh2ECNuG7Gn9a9+BxH+cjWof/V9UQweOH+0sbbsdxsykPAWpdIdYmIBK8GCmK3gvhQbJx +QCGWuTFfMCtHBCQz5/Q3F/ylTvbxX0D1MBbY5YKDyPNsPeHZy6/tiUAw9JYVfIlDWHhP71rb/r mvRjJMFPZLa53fLyaB5IVS/askdF9yQVnipPgMQJv9jOUVUqxTHsKwJSklDQ5VmCFc06gLCPAn/ WxTPSwFDDOQ0+aHeem2rkYXwKrehc8KUZipHFJ2V+EPbtor79zM1mdrBtaZdFecni65ElLH7t4k wHyX7P3RKkYQVVtNmADagVMhPLiFTA1Bhppv1SKG+7bf/3dSqnQZzaaOZlFf8p4UmsfxEyuFFF6 /d5HwDJuvW8wacgQD1MlkbuehrwGDRUj4QPvPVG7bLc9tc0eL89eHjUqBaxGG054yinl57YTwoV 89MSoZvDhS+2NSLOYEy7jzT1AIJbj5hPlSfZF5xFmDqURneq0ba4+UEwIFi6T08g7mf36Joeywt B8ueCf7VOePD63w== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 152 ++++++++++++------------ arch/arm64/boot/dts/qcom/sdm660.dtsi | 16 +-- arch/arm64/boot/dts/qcom/sdm670.dtsi | 158 ++++++++++++------------- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 74 ++++++------ arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 178 ++++++++++++++-----------= ---- 6 files changed, 291 insertions(+), 291 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qco= m/sdm630.dtsi index 4536fa45869a757808f9a4486d41f0f6a039334e..19420cfdadf151394c4ebc821f6= 8675036fe782f 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -49,170 +49,170 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@100 { + cpu0: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x100>; enable-method =3D "psci"; - cpu-idle-states =3D <&PERF_CPU_SLEEP_0 - &PERF_CPU_SLEEP_1 - &PERF_CLUSTER_SLEEP_0 - &PERF_CLUSTER_SLEEP_1 - &PERF_CLUSTER_SLEEP_2>; + cpu-idle-states =3D <&perf_cpu_sleep_0 + &perf_cpu_sleep_1 + &perf_cluster_sleep_0 + &perf_cluster_sleep_1 + &perf_cluster_sleep_2>; capacity-dmips-mhz =3D <1126>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_1>; - L2_1: l2-cache { + next-level-cache =3D <&l2_1>; + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@101 { + cpu1: cpu@101 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x101>; enable-method =3D "psci"; - cpu-idle-states =3D <&PERF_CPU_SLEEP_0 - &PERF_CPU_SLEEP_1 - &PERF_CLUSTER_SLEEP_0 - &PERF_CLUSTER_SLEEP_1 - &PERF_CLUSTER_SLEEP_2>; + cpu-idle-states =3D <&perf_cpu_sleep_0 + &perf_cpu_sleep_1 + &perf_cluster_sleep_0 + &perf_cluster_sleep_1 + &perf_cluster_sleep_2>; capacity-dmips-mhz =3D <1126>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU2: cpu@102 { + cpu2: cpu@102 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x102>; enable-method =3D "psci"; - cpu-idle-states =3D <&PERF_CPU_SLEEP_0 - &PERF_CPU_SLEEP_1 - &PERF_CLUSTER_SLEEP_0 - &PERF_CLUSTER_SLEEP_1 - &PERF_CLUSTER_SLEEP_2>; + cpu-idle-states =3D <&perf_cpu_sleep_0 + &perf_cpu_sleep_1 + &perf_cluster_sleep_0 + &perf_cluster_sleep_1 + &perf_cluster_sleep_2>; capacity-dmips-mhz =3D <1126>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU3: cpu@103 { + cpu3: cpu@103 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x103>; enable-method =3D "psci"; - cpu-idle-states =3D <&PERF_CPU_SLEEP_0 - &PERF_CPU_SLEEP_1 - &PERF_CLUSTER_SLEEP_0 - &PERF_CLUSTER_SLEEP_1 - &PERF_CLUSTER_SLEEP_2>; + cpu-idle-states =3D <&perf_cpu_sleep_0 + &perf_cpu_sleep_1 + &perf_cluster_sleep_0 + &perf_cluster_sleep_1 + &perf_cluster_sleep_2>; capacity-dmips-mhz =3D <1126>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; }; =20 - CPU4: cpu@0 { + cpu4: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x0>; enable-method =3D "psci"; - cpu-idle-states =3D <&PWR_CPU_SLEEP_0 - &PWR_CPU_SLEEP_1 - &PWR_CLUSTER_SLEEP_0 - &PWR_CLUSTER_SLEEP_1 - &PWR_CLUSTER_SLEEP_2>; + cpu-idle-states =3D <&pwr_cpu_sleep_0 + &pwr_cpu_sleep_1 + &pwr_cluster_sleep_0 + &pwr_cluster_sleep_1 + &pwr_cluster_sleep_2>; capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@1 { + cpu5: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x1>; enable-method =3D "psci"; - cpu-idle-states =3D <&PWR_CPU_SLEEP_0 - &PWR_CPU_SLEEP_1 - &PWR_CLUSTER_SLEEP_0 - &PWR_CLUSTER_SLEEP_1 - &PWR_CLUSTER_SLEEP_2>; + cpu-idle-states =3D <&pwr_cpu_sleep_0 + &pwr_cpu_sleep_1 + &pwr_cluster_sleep_0 + &pwr_cluster_sleep_1 + &pwr_cluster_sleep_2>; capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU6: cpu@2 { + cpu6: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x2>; enable-method =3D "psci"; - cpu-idle-states =3D <&PWR_CPU_SLEEP_0 - &PWR_CPU_SLEEP_1 - &PWR_CLUSTER_SLEEP_0 - &PWR_CLUSTER_SLEEP_1 - &PWR_CLUSTER_SLEEP_2>; + cpu-idle-states =3D <&pwr_cpu_sleep_0 + &pwr_cpu_sleep_1 + &pwr_cluster_sleep_0 + &pwr_cluster_sleep_1 + &pwr_cluster_sleep_2>; capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 - CPU7: cpu@3 { + cpu7: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x3>; enable-method =3D "psci"; - cpu-idle-states =3D <&PWR_CPU_SLEEP_0 - &PWR_CPU_SLEEP_1 - &PWR_CLUSTER_SLEEP_0 - &PWR_CLUSTER_SLEEP_1 - &PWR_CLUSTER_SLEEP_2>; + cpu-idle-states =3D <&pwr_cpu_sleep_0 + &pwr_cpu_sleep_1 + &pwr_cluster_sleep_0 + &pwr_cluster_sleep_1 + &pwr_cluster_sleep_2>; capacity-dmips-mhz =3D <1024>; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; }; @@ -220,7 +220,7 @@ core3 { idle-states { entry-method =3D "psci"; =20 - PWR_CPU_SLEEP_0: cpu-sleep-0-0 { + pwr_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "pwr-retention"; arm,psci-suspend-param =3D <0x40000002>; @@ -229,7 +229,7 @@ PWR_CPU_SLEEP_0: cpu-sleep-0-0 { min-residency-us =3D <200>; }; =20 - PWR_CPU_SLEEP_1: cpu-sleep-0-1 { + pwr_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "pwr-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -239,7 +239,7 @@ PWR_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - PERF_CPU_SLEEP_0: cpu-sleep-1-0 { + perf_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "perf-retention"; arm,psci-suspend-param =3D <0x40000002>; @@ -248,7 +248,7 @@ PERF_CPU_SLEEP_0: cpu-sleep-1-0 { min-residency-us =3D <200>; }; =20 - PERF_CPU_SLEEP_1: cpu-sleep-1-1 { + perf_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "perf-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -258,7 +258,7 @@ PERF_CPU_SLEEP_1: cpu-sleep-1-1 { local-timer-stop; }; =20 - PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { + pwr_cluster_sleep_0: cluster-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "pwr-cluster-dynamic-retention"; arm,psci-suspend-param =3D <0x400000F2>; @@ -268,7 +268,7 @@ PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { local-timer-stop; }; =20 - PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { + pwr_cluster_sleep_1: cluster-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "pwr-cluster-retention"; arm,psci-suspend-param =3D <0x400000F3>; @@ -278,7 +278,7 @@ PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { local-timer-stop; }; =20 - PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { + pwr_cluster_sleep_2: cluster-sleep-0-2 { compatible =3D "arm,idle-state"; idle-state-name =3D "pwr-cluster-retention"; arm,psci-suspend-param =3D <0x400000F4>; @@ -288,7 +288,7 @@ PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { local-timer-stop; }; =20 - PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { + perf_cluster_sleep_0: cluster-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "perf-cluster-dynamic-retention"; arm,psci-suspend-param =3D <0x400000F2>; @@ -298,7 +298,7 @@ PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { local-timer-stop; }; =20 - PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { + perf_cluster_sleep_1: cluster-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "perf-cluster-retention"; arm,psci-suspend-param =3D <0x400000F3>; @@ -308,7 +308,7 @@ PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { local-timer-stop; }; =20 - PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { + perf_cluster_sleep_2: cluster-sleep-1-2 { compatible =3D "arm,idle-state"; idle-state-name =3D "perf-cluster-retention"; arm,psci-suspend-param =3D <0x400000F4>; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qco= m/sdm660.dtsi index f89b27c99f40cf0c2edb71aa2e54c413971d0989..3164a4817e3267d458d81cabf2a= e4223a7a94963 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -85,49 +85,49 @@ opp-160000000 { }; }; =20 -&CPU0 { +&cpu0 { compatible =3D "qcom,kryo260"; capacity-dmips-mhz =3D <1024>; /delete-property/ operating-points-v2; }; =20 -&CPU1 { +&cpu1 { compatible =3D "qcom,kryo260"; capacity-dmips-mhz =3D <1024>; /delete-property/ operating-points-v2; }; =20 -&CPU2 { +&cpu2 { compatible =3D "qcom,kryo260"; capacity-dmips-mhz =3D <1024>; /delete-property/ operating-points-v2; }; =20 -&CPU3 { +&cpu3 { compatible =3D "qcom,kryo260"; capacity-dmips-mhz =3D <1024>; /delete-property/ operating-points-v2; }; =20 -&CPU4 { +&cpu4 { compatible =3D "qcom,kryo260"; capacity-dmips-mhz =3D <640>; /delete-property/ operating-points-v2; }; =20 -&CPU5 { +&cpu5 { compatible =3D "qcom,kryo260"; capacity-dmips-mhz =3D <640>; /delete-property/ operating-points-v2; }; =20 -&CPU6 { +&cpu6 { compatible =3D "qcom,kryo260"; capacity-dmips-mhz =3D <640>; /delete-property/ operating-points-v2; }; =20 -&CPU7 { +&cpu7 { compatible =3D "qcom,kryo260"; capacity-dmips-mhz =3D <640>; /delete-property/ operating-points-v2; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qco= m/sdm670.dtsi index a08a64bc033ffdea283645c6bf4ed835a59c3366..c93dd06c0b7d6444aefd0e24201= cea999dcb23a4 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -32,7 +32,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo360"; reg =3D <0x0 0x0>; @@ -43,15 +43,15 @@ CPU0: cpu@0 { operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_= CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; cache-level =3D <2>; cache-unified; - L3_0: l3-cache { + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -59,7 +59,7 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo360"; reg =3D <0x0 0x100>; @@ -70,18 +70,18 @@ CPU1: cpu@100 { operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_= CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_100>; - L2_100: l2-cache { + next-level-cache =3D <&l2_100>; + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo360"; reg =3D <0x0 0x200>; @@ -92,18 +92,18 @@ CPU2: cpu@200 { operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_= CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_200>; - L2_200: l2-cache { + next-level-cache =3D <&l2_200>; + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo360"; reg =3D <0x0 0x300>; @@ -114,18 +114,18 @@ CPU3: cpu@300 { operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_= CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_300>; - L2_300: l2-cache { + next-level-cache =3D <&l2_300>; + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo360"; reg =3D <0x0 0x400>; @@ -136,18 +136,18 @@ CPU4: cpu@400 { operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_= CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_400>; - L2_400: l2-cache { + next-level-cache =3D <&l2_400>; + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo360"; reg =3D <0x0 0x500>; @@ -158,18 +158,18 @@ CPU5: cpu@500 { operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_= CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_500>; - L2_500: l2-cache { + next-level-cache =3D <&l2_500>; + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo360"; reg =3D <0x0 0x600>; @@ -180,18 +180,18 @@ CPU6: cpu@600 { operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_= CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_600>; - L2_600: l2-cache { + next-level-cache =3D <&l2_600>; + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo360"; reg =3D <0x0 0x700>; @@ -202,49 +202,49 @@ CPU7: cpu@700 { operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_= CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_700>; - L2_700: l2-cache { + next-level-cache =3D <&l2_700>; + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -252,7 +252,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -262,7 +262,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -274,7 +274,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c244>; entry-latency-us =3D <3263>; @@ -429,57 +429,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>; + domain-idle-states =3D <&cluster_sleep_0>; }; }; =20 @@ -1763,7 +1763,7 @@ apps_rsc: rsc@179c0000 { , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/d= ts/qcom/sdm845-cheza.dtsi index e8276db9eabb29b8a6021fcdf33e959d2450af5d..743c339ba1081e3a70d94a58b13= c12c5525a1b11 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -164,7 +164,7 @@ &cpus { }; =20 &cpu_idle_states { - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-power-down"; arm,psci-suspend-param =3D <0x40000003>; @@ -174,7 +174,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + little_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-down"; arm,psci-suspend-param =3D <0x40000004>; @@ -184,7 +184,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-power-down"; arm,psci-suspend-param =3D <0x40000003>; @@ -194,7 +194,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + big_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-down"; arm,psci-suspend-param =3D <0x40000004>; @@ -204,7 +204,7 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 { local-timer-stop; }; =20 - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "cluster-power-down"; arm,psci-suspend-param =3D <0x400000F4>; @@ -215,68 +215,68 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { }; }; =20 -&CPU0 { +&cpu0 { /delete-property/ power-domains; /delete-property/ power-domain-names; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 + &little_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU1 { +&cpu1 { /delete-property/ power-domains; /delete-property/ power-domain-names; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 + &little_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU2 { +&cpu2 { /delete-property/ power-domains; /delete-property/ power-domain-names; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 + &little_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU3 { +&cpu3 { /delete-property/ power-domains; /delete-property/ power-domain-names; - cpu-idle-states =3D <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&little_cpu_sleep_0 + &little_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU4 { +&cpu4 { /delete-property/ power-domains; /delete-property/ power-domain-names; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&big_cpu_sleep_0 + &big_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU5 { +&cpu5 { /delete-property/ power-domains; /delete-property/ power-domain-names; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&big_cpu_sleep_0 + &big_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU6 { +&cpu6 { /delete-property/ power-domains; /delete-property/ power-domain-names; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&big_cpu_sleep_0 + &big_cpu_sleep_1 + &cluster_sleep_0>; }; =20 -&CPU7 { +&cpu7 { /delete-property/ power-domains; /delete-property/ power-domain-names; - cpu-idle-states =3D <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&big_cpu_sleep_0 + &big_cpu_sleep_1 + &cluster_sleep_0>; }; =20 &lmh_cluster0 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/d= ts/qcom/sdm845-db845c.dts index 9a6d3d0c0ee43af337728546626ec70ce47b9ec6..1cc0f571e1f7f3023efa08adf27= 91ffce5f2fecf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -31,7 +31,7 @@ chosen { }; =20 /* Fixed crystal oscillator dedicated to MCP2517FD */ - clk40M: can-clock { + clk40m: can-clock { compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <40000000>; @@ -863,7 +863,7 @@ &spi0 { can@0 { compatible =3D "microchip,mcp2517fd"; reg =3D <0>; - clocks =3D <&clk40M>; + clocks =3D <&clk40m>; interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; spi-max-frequency =3D <10000000>; vdd-supply =3D <&vdc_5v>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 49440d1b2cf6caf6da9d97c635cbd751f0700326..1ed794638a7cee7ec5ead15160e= 5fd97037ba5ff 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -91,7 +91,7 @@ cpus: cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo385"; reg =3D <0x0 0x0>; @@ -103,16 +103,16 @@ CPU0: cpu@0 { operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -120,7 +120,7 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo385"; reg =3D <0x0 0x100>; @@ -132,19 +132,19 @@ CPU1: cpu@100 { operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_100>; - L2_100: l2-cache { + next-level-cache =3D <&l2_100>; + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo385"; reg =3D <0x0 0x200>; @@ -156,19 +156,19 @@ CPU2: cpu@200 { operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_200>; - L2_200: l2-cache { + next-level-cache =3D <&l2_200>; + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo385"; reg =3D <0x0 0x300>; @@ -181,18 +181,18 @@ CPU3: cpu@300 { interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_300>; - L2_300: l2-cache { + next-level-cache =3D <&l2_300>; + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo385"; reg =3D <0x0 0x400>; @@ -204,19 +204,19 @@ CPU4: cpu@400 { operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_400>; - L2_400: l2-cache { + next-level-cache =3D <&l2_400>; + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo385"; reg =3D <0x0 0x500>; @@ -228,19 +228,19 @@ CPU5: cpu@500 { operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_500>; - L2_500: l2-cache { + next-level-cache =3D <&l2_500>; + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo385"; reg =3D <0x0 0x600>; @@ -252,19 +252,19 @@ CPU6: cpu@600 { operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_600>; - L2_600: l2-cache { + next-level-cache =3D <&l2_600>; + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo385"; reg =3D <0x0 0x700>; @@ -276,50 +276,50 @@ CPU7: cpu@700 { operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; - next-level-cache =3D <&L2_700>; - L2_700: l2-cache { + next-level-cache =3D <&l2_700>; + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -327,7 +327,7 @@ core7 { cpu_idle_states: idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -337,7 +337,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -349,7 +349,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c244>; entry-latency-us =3D <3263>; @@ -717,57 +717,57 @@ psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>; + domain-idle-states =3D <&cluster_sleep_0>; }; }; =20 @@ -3615,7 +3615,7 @@ etm@7040000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07040000 0 0x1000>; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3635,7 +3635,7 @@ etm@7140000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07140000 0 0x1000>; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3655,7 +3655,7 @@ etm@7240000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07240000 0 0x1000>; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3675,7 +3675,7 @@ etm@7340000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07340000 0 0x1000>; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3695,7 +3695,7 @@ etm@7440000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07440000 0 0x1000>; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3715,7 +3715,7 @@ etm@7540000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07540000 0 0x1000>; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3735,7 +3735,7 @@ etm@7640000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07640000 0 0x1000>; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3755,7 +3755,7 @@ etm@7740000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07740000 0 0x1000>; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3959,7 +3959,7 @@ lmh_cluster1: lmh@17d70800 { compatible =3D "qcom,sdm845-lmh"; reg =3D <0 0x17d70800 0 0x400>; interrupts =3D ; - cpus =3D <&CPU4>; + cpus =3D <&cpu4>; qcom,lmh-temp-arm-millicelsius =3D <65000>; qcom,lmh-temp-low-millicelsius =3D <94500>; qcom,lmh-temp-high-millicelsius =3D <95000>; @@ -3971,7 +3971,7 @@ lmh_cluster0: lmh@17d78800 { compatible =3D "qcom,sdm845-lmh"; reg =3D <0 0x17d78800 0 0x400>; interrupts =3D ; - cpus =3D <&CPU0>; + cpus =3D <&cpu0>; qcom,lmh-temp-arm-millicelsius =3D <65000>; qcom,lmh-temp-low-millicelsius =3D <94500>; qcom,lmh-temp-high-millicelsius =3D <95000>; @@ -5278,7 +5278,7 @@ apps_rsc: rsc@179c0000 { , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; --=20 2.43.0 From nobody Tue Nov 26 02:43:14 2024 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9A8A1A7AD0 for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 68 +++++------ arch/arm64/boot/dts/qcom/qcs404.dtsi | 68 +++++------ arch/arm64/boot/dts/qcom/qdu1000.dtsi | 86 ++++++------- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 14 +-- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 188 ++++++++++++++-------------- arch/arm64/boot/dts/qcom/sdx75.dtsi | 90 +++++++------- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 202 +++++++++++++++------------= ---- 7 files changed, 358 insertions(+), 358 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qc= om/qcm2290.dtsi index 79bc42ffb6a1ffa257b4c2efd744bb390362ded3..f0746123e594d5ce5cc314c956e= aca11556a9211 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -42,7 +42,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x0>; @@ -50,18 +50,18 @@ CPU0: cpu@0 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x1>; @@ -69,13 +69,13 @@ CPU1: cpu@1 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x2>; @@ -83,13 +83,13 @@ CPU2: cpu@2 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x3>; @@ -97,34 +97,34 @@ CPU3: cpu@3 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; }; =20 domain-idle-states { - CLUSTER_SLEEP: cluster-sleep-0 { + cluster_sleep: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000043>; entry-latency-us =3D <800>; @@ -136,7 +136,7 @@ CLUSTER_SLEEP: cluster-sleep-0 { idle-states { entry-method =3D "psci"; =20 - CPU_SLEEP: cpu-sleep-0 { + cpu_sleep: cpu-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -174,34 +174,34 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_SLEEP>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster { + cluster_pd: power-domain-cpu-cluster { #power-domain-cells =3D <0>; power-domains =3D <&mpm>; - domain-idle-states =3D <&CLUSTER_SLEEP>; + domain-idle-states =3D <&cluster_sleep>; }; }; =20 @@ -2067,7 +2067,7 @@ lmh_cluster: lmh@f550800 { compatible =3D "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; reg =3D <0x0 0x0f550800 0x0 0x400>; interrupts =3D ; - cpus =3D <&CPU0>; + cpus =3D <&cpu0>; qcom,lmh-temp-arm-millicelsius =3D <65000>; qcom,lmh-temp-low-millicelsius =3D <94500>; qcom,lmh-temp-high-millicelsius =3D <95000>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qco= m/qcs404.dtsi index cddc16bac0cea4a95e65d1849fe84f34c6ddbfce..215ba146207afd2512869278192= 6cf1964743655 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -36,13 +36,13 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@100 { + cpu0: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x100>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; - next-level-cache =3D <&L2_0>; + cpu-idle-states =3D <&cpu_sleep_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; clocks =3D <&apcs_glb>; operating-points-v2 =3D <&cpu_opp_table>; @@ -50,13 +50,13 @@ CPU0: cpu@100 { power-domain-names =3D "cpr"; }; =20 - CPU1: cpu@101 { + cpu1: cpu@101 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x101>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; - next-level-cache =3D <&L2_0>; + cpu-idle-states =3D <&cpu_sleep_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; clocks =3D <&apcs_glb>; operating-points-v2 =3D <&cpu_opp_table>; @@ -64,13 +64,13 @@ CPU1: cpu@101 { power-domain-names =3D "cpr"; }; =20 - CPU2: cpu@102 { + cpu2: cpu@102 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x102>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; - next-level-cache =3D <&L2_0>; + cpu-idle-states =3D <&cpu_sleep_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; clocks =3D <&apcs_glb>; operating-points-v2 =3D <&cpu_opp_table>; @@ -78,13 +78,13 @@ CPU2: cpu@102 { power-domain-names =3D "cpr"; }; =20 - CPU3: cpu@103 { + cpu3: cpu@103 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x103>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_SLEEP_0>; - next-level-cache =3D <&L2_0>; + cpu-idle-states =3D <&cpu_sleep_0>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; clocks =3D <&apcs_glb>; operating-points-v2 =3D <&cpu_opp_table>; @@ -92,7 +92,7 @@ CPU3: cpu@103 { power-domain-names =3D "cpr"; }; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -101,7 +101,7 @@ L2_0: l2-cache { idle-states { entry-method =3D "psci"; =20 - CPU_SLEEP_0: cpu-sleep-0 { + cpu_sleep_0: cpu-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "standalone-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -1679,10 +1679,10 @@ cluster_crit: cluster-crit { cooling-maps { map0 { trip =3D <&cluster_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -1712,10 +1712,10 @@ cpu0_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -1745,10 +1745,10 @@ cpu1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu1_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -1778,10 +1778,10 @@ cpu2_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -1811,10 +1811,10 @@ cpu3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu3_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qc= om/qdu1000.dtsi index bc1d37b3f6f04d629c96fa893daf4d91fb5f406e..47c0dd31aaf2e42d6d854119562= 07b2509a605b0 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -25,22 +25,22 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domains =3D <&cpufreq_hw 0>; - next-level-cache =3D <&L2_0>; - L2_0: l2-cache { + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -48,76 +48,76 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,freq-domains =3D <&cpufreq_hw 0>; - next-level-cache =3D <&L2_100>; - L2_100: l2-cache { + next-level-cache =3D <&l2_100>; + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,freq-domains =3D <&cpufreq_hw 0>; - next-level-cache =3D <&L2_200>; - L2_200: l2-cache { + next-level-cache =3D <&l2_200>; + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x300>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,freq-domains =3D <&cpufreq_hw 0>; - next-level-cache =3D <&L2_300>; - L2_300: l2-cache { + next-level-cache =3D <&l2_300>; + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; }; @@ -126,7 +126,7 @@ core3 { idle-states { entry-method =3D "psci"; =20 - CPU_OFF: cpu-sleep-0 { + cpu_off: cpu-sleep-0 { compatible =3D "arm,idle-state"; entry-latency-us =3D <274>; exit-latency-us =3D <480>; @@ -137,7 +137,7 @@ CPU_OFF: cpu-sleep-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; entry-latency-us =3D <584>; exit-latency-us =3D <2332>; @@ -145,7 +145,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { arm,psci-suspend-param =3D <0x41000044>; }; =20 - CLUSTER_SLEEP_1: cluster-sleep-1 { + cluster_sleep_1: cluster-sleep-1 { compatible =3D "domain-idle-state"; entry-latency-us =3D <2893>; exit-latency-us =3D <4023>; @@ -187,33 +187,33 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_OFF>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_off>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_OFF>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_off>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_OFF>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_off>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_OFF>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_off>; }; =20 - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; + domain-idle-states =3D <&cluster_sleep_0 &cluster_sleep_1>; }; }; =20 @@ -1499,7 +1499,7 @@ apps_rsc: rsc@17a00000 { qcom,tcs-config =3D , , , ; label =3D "apps_rsc"; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts= /qcom/qrb2210-rb1.dts index e19790464a1159d3ab6e788b8aa22adaa52c56d3..7a789b41c2f1887f0c41ae24da2= e2fe8915ab13c 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -24,7 +24,7 @@ chosen { }; =20 clocks { - clk40M: can-clk { + clk40m: can-clk { compatible =3D "fixed-clock"; clock-frequency =3D <40000000>; #clock-cells =3D <0>; @@ -188,23 +188,23 @@ vph_pwr: regulator-vph-pwr { }; }; =20 -&CPU_PD0 { +&cpu_pd0 { /delete-property/ power-domains; }; =20 -&CPU_PD1 { +&cpu_pd1 { /delete-property/ power-domains; }; =20 -&CPU_PD2 { +&cpu_pd2 { /delete-property/ power-domains; }; =20 -&CPU_PD3 { +&cpu_pd3 { /delete-property/ power-domains; }; =20 -/delete-node/ &CLUSTER_PD; +/delete-node/ &cluster_pd; =20 &gpi_dma0 { status =3D "okay"; @@ -541,7 +541,7 @@ can@0 { compatible =3D "microchip,mcp2518fd"; reg =3D <0>; interrupts-extended =3D <&tlmm 39 IRQ_TYPE_LEVEL_LOW>; - clocks =3D <&clk40M>; + clocks =3D <&clk40m>; spi-max-frequency =3D <10000000>; vdd-supply =3D <&vdc_5v>; xceiver-supply =3D <&vdc_5v>; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 07b3d9f656840357a4ab16ddbd0931da45127e61..036ae4306234f34577d53c7e452= 8a6adbde5df23 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -38,21 +38,21 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x0>; enable-method =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -60,72 +60,72 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x100>; enable-method =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - L2_1: l2-cache { + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x200>; enable-method =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; - next-level-cache =3D <&L2_2>; + next-level-cache =3D <&l2_2>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - L2_2: l2-cache { + l2_2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x300>; enable-method =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; - next-level-cache =3D <&L2_3>; + next-level-cache =3D <&l2_3>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - L2_3: l2-cache { + l2_3: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@10000 { + cpu4: cpu@10000 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x10000>; enable-method =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; - next-level-cache =3D <&L2_4>; + next-level-cache =3D <&l2_4>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - L2_4: l2-cache { + l2_4: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_1>; - L3_1: l3-cache { + next-level-cache =3D <&l3_1>; + l3_1: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -134,91 +134,91 @@ L3_1: l3-cache { }; }; =20 - CPU5: cpu@10100 { + cpu5: cpu@10100 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x10100>; enable-method =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; - next-level-cache =3D <&L2_5>; + next-level-cache =3D <&l2_5>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - L2_5: l2-cache { + l2_5: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_1>; + next-level-cache =3D <&l3_1>; }; }; =20 - CPU6: cpu@10200 { + cpu6: cpu@10200 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x10200>; enable-method =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; - next-level-cache =3D <&L2_6>; + next-level-cache =3D <&l2_6>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - L2_6: l2-cache { + l2_6: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_1>; + next-level-cache =3D <&l3_1>; }; }; =20 - CPU7: cpu@10300 { + cpu7: cpu@10300 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x10300>; enable-method =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; - next-level-cache =3D <&L2_7>; + next-level-cache =3D <&l2_7>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - L2_7: l2-cache { + l2_7: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_1>; + next-level-cache =3D <&l3_1>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -226,7 +226,7 @@ core3 { idle-states { entry-method =3D "psci"; =20 - GOLD_CPU_SLEEP_0: cpu-sleep-0 { + gold_cpu_sleep_0: cpu-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -236,7 +236,7 @@ GOLD_CPU_SLEEP_0: cpu-sleep-0 { local-timer-stop; }; =20 - GOLD_RAIL_CPU_SLEEP_0: cpu-sleep-1 { + gold_rail_cpu_sleep_0: cpu-sleep-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -248,7 +248,7 @@ GOLD_RAIL_CPU_SLEEP_0: cpu-sleep-1 { }; =20 domain-idle-states { - CLUSTER_SLEEP_GOLD: cluster-sleep-0 { + cluster_sleep_gold: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <2752>; @@ -256,7 +256,7 @@ CLUSTER_SLEEP_GOLD: cluster-sleep-0 { min-residency-us =3D <6118>; }; =20 - CLUSTER_SLEEP_APSS_RSC_PC: cluster-sleep-1 { + cluster_sleep_apss_rsc_pc: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x42000144>; entry-latency-us =3D <3263>; @@ -394,77 +394,77 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>, - <&GOLD_RAIL_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>, - <&GOLD_RAIL_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>, - <&GOLD_RAIL_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>, - <&GOLD_RAIL_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>, - <&GOLD_RAIL_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>, - <&GOLD_RAIL_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>, - <&GOLD_RAIL_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&GOLD_CPU_SLEEP_0>, - <&GOLD_RAIL_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; =20 - CLUSTER_0_PD: power-domain-cluster0 { + cluster_0_pd: power-domain-cluster0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_2_PD>; - domain-idle-states =3D <&CLUSTER_SLEEP_GOLD>; + power-domains =3D <&cluster_2_pd>; + domain-idle-states =3D <&cluster_sleep_gold>; }; =20 - CLUSTER_1_PD: power-domain-cluster1 { + cluster_1_pd: power-domain-cluster1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_2_PD>; - domain-idle-states =3D <&CLUSTER_SLEEP_GOLD>; + power-domains =3D <&cluster_2_pd>; + domain-idle-states =3D <&cluster_sleep_gold>; }; =20 - CLUSTER_2_PD: power-domain-cluster2 { + cluster_2_pd: power-domain-cluster2 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_APSS_RSC_PC>; + domain-idle-states =3D <&cluster_sleep_apss_rsc_pc>; }; }; =20 @@ -2613,7 +2613,7 @@ aoss_cti: cti@4b13000 { etm@6040000 { compatible =3D "arm,primecell"; reg =3D <0x0 0x6040000 0x0 0x1000>; - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2633,7 +2633,7 @@ etm0_out: endpoint { etm@6140000 { compatible =3D "arm,primecell"; reg =3D <0x0 0x6140000 0x0 0x1000>; - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2653,7 +2653,7 @@ etm1_out: endpoint { etm@6240000 { compatible =3D "arm,primecell"; reg =3D <0x0 0x6240000 0x0 0x1000>; - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2673,7 +2673,7 @@ etm2_out: endpoint { etm@6340000 { compatible =3D "arm,primecell"; reg =3D <0x0 0x6340000 0x0 0x1000>; - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2693,7 +2693,7 @@ etm3_out: endpoint { etm@6440000 { compatible =3D "arm,primecell"; reg =3D <0x0 0x6440000 0x0 0x1000>; - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2713,7 +2713,7 @@ etm4_out: endpoint { etm@6540000 { compatible =3D "arm,primecell"; reg =3D <0x0 0x6540000 0x0 0x1000>; - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2733,7 +2733,7 @@ etm5_out: endpoint { etm@6640000 { compatible =3D "arm,primecell"; reg =3D <0x0 0x6640000 0x0 0x1000>; - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -2753,7 +2753,7 @@ etm6_out: endpoint { etm@6740000 { compatible =3D "arm,primecell"; reg =3D <0x0 0x6740000 0x0 0x1000>; - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom= /sdx75.dtsi index 7cf3fcb469a8682f0898f5d66d4ec0964cd0c80f..5f7e59ecf1ca6298cb252ee0654= bc7eaeefbd303 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -43,25 +43,25 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -69,85 +69,85 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; =20 - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; =20 - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x300>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; =20 - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; }; @@ -155,7 +155,7 @@ core3 { idle-states { entry-method =3D "psci"; =20 - CPU_OFF: cpu-sleep-0 { + cpu_off: cpu-sleep-0 { compatible =3D "arm,idle-state"; entry-latency-us =3D <235>; exit-latency-us =3D <428>; @@ -164,7 +164,7 @@ CPU_OFF: cpu-sleep-0 { local-timer-stop; }; =20 - CPU_RAIL_OFF: cpu-rail-sleep-1 { + cpu_rail_off: cpu-rail-sleep-1 { compatible =3D "arm,idle-state"; entry-latency-us =3D <800>; exit-latency-us =3D <750>; @@ -176,7 +176,7 @@ CPU_RAIL_OFF: cpu-rail-sleep-1 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <1050>; @@ -184,7 +184,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { min-residency-us =3D <5309>; }; =20 - CLUSTER_SLEEP_1: cluster-sleep-1 { + cluster_sleep_1: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41001344>; entry-latency-us =3D <2761>; @@ -192,7 +192,7 @@ CLUSTER_SLEEP_1: cluster-sleep-1 { min-residency-us =3D <8467>; }; =20 - CLUSTER_SLEEP_2: cluster-sleep-2 { + cluster_sleep_2: cluster-sleep-2 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100b344>; entry-latency-us =3D <2793>; @@ -235,33 +235,33 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_OFF &CPU_RAIL_OFF>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_off &cpu_rail_off>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_OFF &CPU_RAIL_OFF>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_off &cpu_rail_off>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_OFF &CPU_RAIL_OFF>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_off &cpu_rail_off>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&CPU_OFF &CPU_RAIL_OFF>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_off &cpu_rail_off>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEE= P_2>; + domain-idle-states =3D <&cluster_sleep_0 &cluster_sleep_1 &cluster_slee= p_2>; }; }; =20 @@ -1444,7 +1444,7 @@ apps_rsc: rsc@17a00000 { , ; =20 - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; qcom,tcs-offset =3D <0xd00>; qcom,drv-id =3D <2>; qcom,tcs-config =3D , diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index bc3c7294abc37054f9f782b3c5285444df206430..99f8bee10a38b6659771a7175be= 4240239683e50 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -65,208 +65,208 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x0>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD1>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x200>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD2>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x300>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD3>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; }; =20 - CPU4: cpu@10000 { + cpu4: cpu@10000 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x10000>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; - power-domains =3D <&CPU_PD4>; + next-level-cache =3D <&l2_1>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; =20 - L2_1: l2-cache { + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@10100 { + cpu5: cpu@10100 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x10100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; - power-domains =3D <&CPU_PD5>; + next-level-cache =3D <&l2_1>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; }; =20 - CPU6: cpu@10200 { + cpu6: cpu@10200 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x10200>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; - power-domains =3D <&CPU_PD6>; + next-level-cache =3D <&l2_1>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; }; =20 - CPU7: cpu@10300 { + cpu7: cpu@10300 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x10300>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; - power-domains =3D <&CPU_PD7>; + next-level-cache =3D <&l2_1>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; }; =20 - CPU8: cpu@20000 { + cpu8: cpu@20000 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x20000>; enable-method =3D "psci"; - next-level-cache =3D <&L2_2>; - power-domains =3D <&CPU_PD8>; + next-level-cache =3D <&l2_2>; + power-domains =3D <&cpu_pd8>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; =20 - L2_2: l2-cache { + l2_2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU9: cpu@20100 { + cpu9: cpu@20100 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x20100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_2>; - power-domains =3D <&CPU_PD9>; + next-level-cache =3D <&l2_2>; + power-domains =3D <&cpu_pd9>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; }; =20 - CPU10: cpu@20200 { + cpu10: cpu@20200 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x20200>; enable-method =3D "psci"; - next-level-cache =3D <&L2_2>; - power-domains =3D <&CPU_PD10>; + next-level-cache =3D <&l2_2>; + power-domains =3D <&cpu_pd10>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; }; =20 - CPU11: cpu@20300 { + cpu11: cpu@20300 { device_type =3D "cpu"; compatible =3D "qcom,oryon"; reg =3D <0x0 0x20300>; enable-method =3D "psci"; - next-level-cache =3D <&L2_2>; - power-domains =3D <&CPU_PD11>; + next-level-cache =3D <&l2_2>; + power-domains =3D <&cpu_pd11>; power-domain-names =3D "psci"; - cpu-idle-states =3D <&CLUSTER_C4>; + cpu-idle-states =3D <&cluster_c4>; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; =20 cluster2 { core0 { - cpu =3D <&CPU8>; + cpu =3D <&cpu8>; }; =20 core1 { - cpu =3D <&CPU9>; + cpu =3D <&cpu9>; }; =20 core2 { - cpu =3D <&CPU10>; + cpu =3D <&cpu10>; }; =20 core3 { - cpu =3D <&CPU11>; + cpu =3D <&cpu11>; }; }; }; @@ -274,7 +274,7 @@ core3 { idle-states { entry-method =3D "psci"; =20 - CLUSTER_C4: cpu-sleep-0 { + cluster_c4: cpu-sleep-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "ret"; arm,psci-suspend-param =3D <0x00000004>; @@ -285,7 +285,7 @@ CLUSTER_C4: cpu-sleep-0 { }; =20 domain-idle-states { - CLUSTER_CL4: cluster-sleep-0 { + cluster_cl4: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x01000044>; entry-latency-us =3D <350>; @@ -293,7 +293,7 @@ CLUSTER_CL4: cluster-sleep-0 { min-residency-us =3D <2500>; }; =20 - CLUSTER_CL5: cluster-sleep-1 { + cluster_cl5: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x01000054>; entry-latency-us =3D <2200>; @@ -339,85 +339,85 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD0>; + power-domains =3D <&cluster_pd0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD0>; + power-domains =3D <&cluster_pd0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD0>; + power-domains =3D <&cluster_pd0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD0>; + power-domains =3D <&cluster_pd0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD1>; + power-domains =3D <&cluster_pd1>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD1>; + power-domains =3D <&cluster_pd1>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD1>; + power-domains =3D <&cluster_pd1>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD1>; + power-domains =3D <&cluster_pd1>; }; =20 - CPU_PD8: power-domain-cpu8 { + cpu_pd8: power-domain-cpu8 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD2>; + power-domains =3D <&cluster_pd2>; }; =20 - CPU_PD9: power-domain-cpu9 { + cpu_pd9: power-domain-cpu9 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD2>; + power-domains =3D <&cluster_pd2>; }; =20 - CPU_PD10: power-domain-cpu10 { + cpu_pd10: power-domain-cpu10 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD2>; + power-domains =3D <&cluster_pd2>; }; =20 - CPU_PD11: power-domain-cpu11 { + cpu_pd11: power-domain-cpu11 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD2>; + power-domains =3D <&cluster_pd2>; }; =20 - CLUSTER_PD0: power-domain-cpu-cluster0 { + cluster_pd0: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_CL4>, <&CLUSTER_CL5>; - power-domains =3D <&SYSTEM_PD>; + domain-idle-states =3D <&cluster_cl4>, <&cluster_cl5>; + power-domains =3D <&system_pd>; }; =20 - CLUSTER_PD1: power-domain-cpu-cluster1 { + cluster_pd1: power-domain-cpu-cluster1 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_CL4>, <&CLUSTER_CL5>; - power-domains =3D <&SYSTEM_PD>; + domain-idle-states =3D <&cluster_cl4>, <&cluster_cl5>; + power-domains =3D <&system_pd>; }; =20 - CLUSTER_PD2: power-domain-cpu-cluster2 { + cluster_pd2: power-domain-cpu-cluster2 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_CL4>, <&CLUSTER_CL5>; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- 1. New patch --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 36 ++++++++++++++++------------= ---- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 20 +++++++++--------- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 ++++----- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 6 +++--- arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi | 4 ++-- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 34 +++++++++++++++-------------= -- arch/arm/boot/dts/qcom/qcom-msm8660.dtsi | 6 +++--- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 6 +++--- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 36 ++++++++++++++++------------= ---- 9 files changed, 79 insertions(+), 79 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/q= com/qcom-apq8064.dtsi index 1bc935d900854ea40e7520ac5762f307c73232f2..5f1a6b4b764492486df1a261097= 9f56c0a37b64a 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -36,58 +36,58 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <2>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc2>; qcom,saw =3D <&saw2>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <3>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc3>; qcom,saw =3D <&saw3>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; =20 idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible =3D "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us =3D <400>; @@ -1625,7 +1625,7 @@ etm@1a1c000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 out-ports { port { @@ -1643,7 +1643,7 @@ etm@1a1d000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 out-ports { port { @@ -1661,7 +1661,7 @@ etm@1a1e000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 out-ports { port { @@ -1679,7 +1679,7 @@ etm@1a1f000 { clocks =3D <&rpmcc RPM_QDSS_CLK>; clock-names =3D "apb_pclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 out-ports { port { diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/q= com/qcom-apq8084.dtsi index 40dbbf8655f09ff3c6259c69bdd08b2fe3c39594..cee0694ef127b5e2450e274659c= 403e0be81f401 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -32,10 +32,10 @@ cpu@0 { compatible =3D "qcom,krait"; reg =3D <0>; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 cpu@1 { @@ -43,10 +43,10 @@ cpu@1 { compatible =3D "qcom,krait"; reg =3D <1>; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 cpu@2 { @@ -54,10 +54,10 @@ cpu@2 { compatible =3D "qcom,krait"; reg =3D <2>; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc2>; qcom,saw =3D <&saw2>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 cpu@3 { @@ -65,13 +65,13 @@ cpu@3 { compatible =3D "qcom,krait"; reg =3D <3>; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc3>; qcom,saw =3D <&saw3>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -79,7 +79,7 @@ L2: l2-cache { }; =20 idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible =3D "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us =3D <150>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/q= com/qcom-ipq4019.dtsi index 56415ab34083f38f0f5c6aefa873947409c8cc6a..06b20c196faf3fe35983d7ee2ab= ebd2066f83b02 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -47,7 +47,7 @@ cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; reg =3D <0x0>; @@ -61,7 +61,7 @@ cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; reg =3D <0x1>; @@ -75,7 +75,7 @@ cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc2>; qcom,saw =3D <&saw2>; reg =3D <0x2>; @@ -89,7 +89,7 @@ cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,kpss-acc-v2"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc3>; qcom,saw =3D <&saw3>; reg =3D <0x3>; @@ -99,7 +99,7 @@ cpu@3 { operating-points-v2 =3D <&cpu0_opp_table>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/q= com/qcom-ipq8064.dtsi index 0f02f59c282a25698bade3ef3cac3082bd056b3c..96e97350153506922b7560131e3= 3664d51e891b5 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -27,7 +27,7 @@ cpu0: cpu@0 { enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; }; @@ -37,12 +37,12 @@ cpu1: cpu@1 { enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/q= com/qcom-mdm9615.dtsi index 573feb3218c33c449f95f4922c24400cea9ac0cc..7de8d6c550167ac37e09dc5d92b= 7a3b2e21753cb 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -30,7 +30,7 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a5"; reg =3D <0>; device_type =3D "cpu"; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; }; }; =20 @@ -61,7 +61,7 @@ soc: soc { ranges; compatible =3D "simple-bus"; =20 - L2: cache-controller@2040000 { + l2: cache-controller@2040000 { compatible =3D "arm,pl310-cache"; reg =3D <0x02040000 0x1000>; arm,data-latency =3D <2 2 0>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8226.dtsi index 3a685ff7e8ccf505e2801607a70099f4b3c16137..64c8ac94f352e46dc4a18f902d2= c30114ecd91d2 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -39,12 +39,12 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,msm8226-smp"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; qcom,acc =3D <&acc0>; @@ -52,12 +52,12 @@ CPU0: cpu@0 { #cooling-cells =3D <2>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,msm8226-smp"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; qcom,acc =3D <&acc1>; @@ -65,12 +65,12 @@ CPU1: cpu@1 { #cooling-cells =3D <2>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,msm8226-smp"; device_type =3D "cpu"; reg =3D <2>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; qcom,acc =3D <&acc2>; @@ -78,12 +78,12 @@ CPU2: cpu@2 { #cooling-cells =3D <2>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { compatible =3D "arm,cortex-a7"; enable-method =3D "qcom,msm8226-smp"; device_type =3D "cpu"; reg =3D <3>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; clocks =3D <&apcs>; operating-points-v2 =3D <&cpu_opp_table>; qcom,acc =3D <&acc3>; @@ -91,7 +91,7 @@ CPU3: cpu@3 { #cooling-cells =3D <2>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -1264,10 +1264,10 @@ cpu0-thermal { cooling-maps { map0 { trip =3D <&cpu_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; =20 @@ -1295,10 +1295,10 @@ cpu1-thermal { cooling-maps { map0 { trip =3D <&cpu_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; =20 diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8660.dtsi index a66c474cd1aa0d4303dbb1fdaa97072c1f45a7b2..3f69b98d0041eb16093668d6b83= a2da0c3496638 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -22,7 +22,7 @@ cpu@0 { enable-method =3D "qcom,gcc-msm8660"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; }; =20 cpu@1 { @@ -30,10 +30,10 @@ cpu@1 { enable-method =3D "qcom,gcc-msm8660"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8960.dtsi index ebc43c5c6e5f756995a5d48bdee102b0b3c47106..865fe7cc39511d7cb9ec5c4b121= 00404f77e2989 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -25,7 +25,7 @@ cpu@0 { enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; }; @@ -35,12 +35,12 @@ cpu@1 { enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8974.dtsi index 742d2104b4fe5db54fcbf8c55c6fb2e0fb12a410..e3f9c56a778cf8c64735ede1e85= 286bde12c1c87 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -35,51 +35,51 @@ cpus { #size-cells =3D <0>; interrupts =3D ; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v2"; device_type =3D "cpu"; reg =3D <0>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v2"; device_type =3D "cpu"; reg =3D <1>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v2"; device_type =3D "cpu"; reg =3D <2>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc2>; qcom,saw =3D <&saw2>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { compatible =3D "qcom,krait"; enable-method =3D "qcom,kpss-acc-v2"; device_type =3D "cpu"; reg =3D <3>; - next-level-cache =3D <&L2>; + next-level-cache =3D <&l2>; qcom,acc =3D <&acc3>; qcom,saw =3D <&saw3>; - cpu-idle-states =3D <&CPU_SPC>; + cpu-idle-states =3D <&cpu_spc>; }; =20 - L2: l2-cache { + l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; @@ -87,7 +87,7 @@ L2: l2-cache { }; =20 idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible =3D "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us =3D <150>; @@ -960,7 +960,7 @@ etm@fc33c000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 out-ports { port { @@ -978,7 +978,7 @@ etm@fc33d000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 out-ports { port { @@ -996,7 +996,7 @@ etm@fc33e000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 out-ports { port { @@ -1014,7 +1014,7 @@ etm@fc33f000 { clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names =3D "apb_pclk", "atclk"; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 out-ports { port { --=20 2.43.0