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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Lijuan Gao --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 0d451082570e..74316c6af300 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -42,6 +42,7 @@ description: | msm8996 msm8998 qcs404 + qcs615 qcs8550 qcm2290 qcm6490 @@ -896,6 +897,11 @@ properties: - const: qcom,qcs404-evb - const: qcom,qcs404 =20 + - items: + - enum: + - qcom,qcs615-ride + - const: qcom,qcs615 + - items: - enum: - qcom,sa8155p-adp --=20 2.46.0 From nobody Tue Nov 26 02:31:36 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 027B3155330; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Lijuan Gao --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pd= c.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.ya= ml index b1ea08a41bb0..ac7ccd989441 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,qcs615-pdc - qcom,qdu1000-pdc - qcom,sa8255p-pdc - qcom,sa8775p-pdc --=20 2.46.0 From nobody Tue Nov 26 02:31:36 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5525A1991CC; Tue, 22 Oct 2024 08:55:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Lijuan Gao --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 3c14df7a382c..524c523a296c 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -445,6 +445,7 @@ static const struct soc_id soc_id[] =3D { { qcom_board_id(IPQ5321) }, { qcom_board_id(QCS8300) }, { qcom_board_id(QCS8275) }, + { qcom_board_id(QCS615) }, }; =20 static const char *socinfo_machine(struct device *dev, unsigned int id) --=20 2.46.0 From nobody Tue Nov 26 02:31:36 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5BF219922E; Tue, 22 Oct 2024 08:55:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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Features added in this revision: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - QFPROM - TLMM - Watchdog - RPMH controller - Sleep stats driver - Rpmhpd power controller - Interconnect - GCC and Rpmhcc - QUP with Uart serial support [Tingguo: added rpmhpd power controller nodes] Co-developed-by: Tingguo Cheng Signed-off-by: Tingguo Cheng [Taniya: added clocks nodes] Co-developed-by: Taniya Das Signed-off-by: Taniya Das [Swetha: added interconnect nodes] Co-developed-by: Swetha Chintavatla Signed-off-by: Swetha Chintavatla Signed-off-by: Lijuan Gao --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 688 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 688 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi new file mode 100644 index 000000000000..ac4c4c751da1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_100>; + + l2_100: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_200>; + + l2_200: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_300>; + + l2_300: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_400>; + + l2_400: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_500>; + + l2_500: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x0 0x600>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_600>; + #cooling-cells =3D <2>; + + l2_600: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x0 0x700>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_700>; + + l2_700: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + + core6 { + cpu =3D <&cpu6>; + }; + + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + + idle-states { + entry-method =3D "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <549>; + exit-latency-us =3D <901>; + min-residency-us =3D <1774>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-0-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <702>; + exit-latency-us =3D <915>; + min-residency-us =3D <4001>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <523>; + exit-latency-us =3D <1244>; + min-residency-us =3D <2207>; + local-timer-stop; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <526>; + exit-latency-us =3D <1854>; + min-residency-us =3D <5555>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <2752>; + exit-latency-us =3D <3048>; + min-residency-us =3D <6118>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41001344>; + entry-latency-us =3D <3263>; + exit-latency-us =3D <4562>; + min-residency-us =3D <8467>; + }; + + cluster_sleep_2: cluster-sleep-2 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x4100b344>; + entry-latency-us =3D <3638>; + exit-latency-us =3D <6562>; + min-residency-us =3D <9826>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0 0x80000000 0 0>; + }; + + camnoc_virt: interconnect-0 { + compatible =3D "qcom,qcs615-camnoc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + ipa_virt: interconnect-1 { + compatible =3D "qcom,qcs615-ipa-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-2 { + compatible =3D "qcom,qcs615-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_0 + &cluster_sleep_1 + &cluster_sleep_2>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + smem_region: smem@86000000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86000000 0x0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0 0x10 0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,qcs615-gcc"; + reg =3D <0 0x00100000 0 0x1f0000>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + qfprom: efuse@780000 { + compatible =3D "qcom,qcs615-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x00780000 0x0 0x7000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + qupv3_id_0: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x8c0000 0x0 0x6000>; + ranges; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + uart0: serial@880000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x880000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart0_tx>, <&qup_uart0_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&aggre1_noc MASTER_QUP_0 0 + &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + status =3D "disabled"; + }; + }; + + config_noc: interconnect@1500000 { + reg =3D <0x0 0x1500000 0x0 0x5080>; + compatible =3D "qcom,qcs615-config-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg =3D <0x0 0x1620000 0x0 0x1f300>; + compatible =3D "qcom,qcs615-system-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@1700000 { + reg =3D <0x0 0x1700000 0x0 0x3f200>; + compatible =3D "qcom,qcs615-aggre1-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + reg =3D <0x0 0x1740000 0x0 0x1c100>; + compatible =3D "qcom,qcs615-mmss-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1fc0000 { + compatible =3D "qcom,qcs615-tcsr", "syscon"; + reg =3D <0x0 0x1fc0000 0x0 0x30000>; + }; + + tlmm: pinctrl@3100000 { + compatible =3D "qcom,qcs615-tlmm"; + reg =3D <0x0 0x03100000 0x0 0x300000>, + <0x0 0x03500000 0x0 0x300000>, + <0x0 0x03d00000 0x0 0x300000>; + reg-names =3D "east", + "west", + "south"; + interrupts =3D ; + gpio-ranges =3D <&tlmm 0 0 123>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + wakeup-parent =3D <&pdc>; + + qup_uart0_tx: qup-uart0-tx-state { + pins =3D "gpio16"; + function =3D "qup0"; + }; + + qup_uart0_rx: qup-uart0-rx-state { + pins =3D "gpio17"; + function =3D "qup0"; + }; + }; + + dc_noc: interconnect@9160000 { + reg =3D <0x0 0x9160000 0x0 0x3200>; + compatible =3D "qcom,qcs615-dc-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg =3D <0x0 0x9680000 0x0 0x3e200>; + compatible =3D "qcom,qcs615-gem-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,qcs615-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x17c000f0 0x0 0x64>; + qcom,pdc-ranges =3D <0 480 94>, <94 609 31>, <125 63 1>; + interrupt-parent =3D <&intc>; + #interrupt-cells =3D <2>; + interrupt-controller; + }; + + sram@c3f0000 { + compatible =3D "qcom,rpmh-stats"; + reg =3D <0x0 0x0c3f0000 0x0 0x400>; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + }; + + watchdog: watchdog@17c10000 { + compatible =3D "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; + reg =3D <0x0 0x17c10000 0x0 0x1000>; + interrupts =3D ; + }; + + timer@17c20000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + ranges =3D <0 0 0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17c21000 { + reg =3D <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@17c23000 { + reg =3D <0x17c23000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c25000 { + reg =3D <0x17c25000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c27000 { + reg =3D <0x17c27000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c29000 { + reg =3D <0x17c29000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c2b000 { + reg =3D <0x17c2b000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c2d000 { + reg =3D <0x17c2d000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + + interrupts =3D , + , + ; + + qcom,drv-id =3D <2>; + qcom,tcs-offset =3D <0xd00>; + qcom,tcs-config =3D , + , + , + ; + + label =3D "apps_rsc"; + power-domains =3D <&cluster_pd>; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,qcs615-rpmh-clk"; + clock-names =3D "xo"; + + #clock-cells =3D <1>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,qcs615-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-2 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level =3D ; 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[Tingguo: added regulator nodes] Co-developed-by: Tingguo Cheng Signed-off-by: Tingguo Cheng Signed-off-by: Lijuan Gao --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs615-ride.dts | 219 +++++++++++++++++++++++++++= ++++ 2 files changed, 220 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 065bb19481c1..f14643187cac 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcm6490-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs615-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qdu1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts new file mode 100644 index 000000000000..ee6cab3924a6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ +/dts-v1/; + +#include +#include "qcs615.dtsi" +/ { + model =3D "Qualcomm Technologies, Inc. QCS615 Ride"; + compatible =3D "qcom,qcs615-ride", "qcom,qcs615"; + chassis-type =3D "embedded"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_s3a: smps3 { + regulator-name =3D "vreg_s3a"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <650000>; + regulator-initial-mode =3D ; + }; + + vreg_s4a: smps4 { + regulator-name =3D "vreg_s4a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1829000>; + regulator-initial-mode =3D ; + }; + + vreg_s5a: smps5 { + regulator-name =3D "vreg_s5a"; + regulator-min-microvolt =3D <1896000>; + regulator-max-microvolt =3D <2040000>; + regulator-initial-mode =3D ; + }; + + vreg_s6a: smps6 { + regulator-name =3D "vreg_s6a"; + regulator-min-microvolt =3D <1304000>; + regulator-max-microvolt =3D <1404000>; + regulator-initial-mode =3D ; + }; + + vreg_l1a: ldo1 { + regulator-name =3D "vreg_l1a"; + regulator-min-microvolt =3D <488000>; + regulator-max-microvolt =3D <852000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2a: ldo2 { + regulator-name =3D "vreg_l2a"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3a: ldo3 { + regulator-name =3D "vreg_l3a"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1248000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <875000>; + regulator-max-microvolt =3D <975000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1900000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a: ldo8 { + regulator-name =3D "vreg_l8a"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10a: ldo10 { + regulator-name =3D "vreg_l10a"; + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11a: ldo11 { + regulator-name =3D "vreg_l11a"; + regulator-min-microvolt =3D <1232000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12a: ldo12 { + regulator-name =3D "vreg_l12a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1890000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13a: ldo13 { + regulator-name =3D "vreg_l13a"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3230000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15a: ldo15 { + regulator-name =3D "vreg_l15a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1904000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16a: ldo16 { + regulator-name =3D "vreg_l16a"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; 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Tue, 22 Oct 2024 08:55:18 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 22 Oct 2024 01:55:11 -0700 From: Lijuan Gao Date: Tue, 22 Oct 2024 16:54:35 +0800 Subject: [PATCH v4 7/7] arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241022-add_initial_support_for_qcs615-v4-7-0a551c6dd342@quicinc.com> References: <20241022-add_initial_support_for_qcs615-v4-0-0a551c6dd342@quicinc.com> In-Reply-To: <20241022-add_initial_support_for_qcs615-v4-0-0a551c6dd342@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Catalin Marinas , Will Deacon CC: , , , , , Lijuan Gao X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; 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The serial engine depends on gcc, interconnect and pinctrl. Since the serial console driver is only available as built-in, so these configs needs be built-in for the UART device to probe and register the console. Signed-off-by: Lijuan Gao --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 36b33b9f1704..fd0dfa9ebae0 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -607,6 +607,7 @@ CONFIG_PINCTRL_MSM8996=3Dy CONFIG_PINCTRL_MSM8998=3Dy CONFIG_PINCTRL_QCM2290=3Dy CONFIG_PINCTRL_QCS404=3Dy +CONFIG_PINCTRL_QCS615=3Dy CONFIG_PINCTRL_QDF2XXX=3Dy CONFIG_PINCTRL_QDU1000=3Dy CONFIG_PINCTRL_SA8775P=3Dy @@ -1323,6 +1324,7 @@ CONFIG_MSM_MMCC_8998=3Dm CONFIG_QCM_GCC_2290=3Dy CONFIG_QCM_DISPCC_2290=3Dm CONFIG_QCS_GCC_404=3Dy +CONFIG_QCS_GCC_615=3Dy CONFIG_SC_CAMCC_7280=3Dm CONFIG_QDU_GCC_1000=3Dy CONFIG_SC_CAMCC_8280XP=3Dm @@ -1629,6 +1631,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=3Dy CONFIG_INTERCONNECT_QCOM_OSM_L3=3Dm CONFIG_INTERCONNECT_QCOM_QCM2290=3Dy CONFIG_INTERCONNECT_QCOM_QCS404=3Dm +CONFIG_INTERCONNECT_QCOM_QCS615=3Dy CONFIG_INTERCONNECT_QCOM_QDU1000=3Dy CONFIG_INTERCONNECT_QCOM_SA8775P=3Dy CONFIG_INTERCONNECT_QCOM_SC7180=3Dy --=20 2.46.0