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Signed-off-by: Puranam V G Tejaswi Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19 ++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++++++++++- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 33 +++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ 4 files changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index c4c1d8120bd6..0c560e84ad5a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -972,6 +972,25 @@ static const struct adreno_info a6xx_gpus[] =3D { .prim_fifo_threshold =3D 0x00300200, }, .address_space_size =3D SZ_16G, + }, { + .chip_ids =3D ADRENO_CHIP_IDS(0x06060300), + .family =3D ADRENO_6XX_GEN4, + .fw =3D { + [ADRENO_FW_SQE] =3D "a660_sqe.fw", + [ADRENO_FW_GMU] =3D "a663_gmu.bin", + }, + .gmem =3D SZ_1M + SZ_512K, + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init =3D a6xx_gpu_init, + .a6xx =3D &(const struct a6xx_info) { + .hwcg =3D a690_hwcg, + .protect =3D &a660_protect, + .gmu_cgc_mode =3D 0x00020200, + .prim_fifo_threshold =3D 0x00300200, + }, + .address_space_size =3D SZ_16G, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x06030500), .family =3D ADRENO_6XX_GEN4, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index d74f0cbf3146..2a4e5ebf7259 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -625,6 +625,15 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) gpu->ubwc_config.macrotile_mode =3D 1; } =20 + if (adreno_is_a663(gpu)) { + gpu->ubwc_config.highest_bank_bit =3D 13; + gpu->ubwc_config.amsbc =3D 1; + gpu->ubwc_config.rgb565_predicator =3D 1; + gpu->ubwc_config.uavflagprd_inv =3D 2; + gpu->ubwc_config.macrotile_mode =3D 1; + gpu->ubwc_config.ubwc_swizzle =3D 0x4; + } + if (adreno_is_7c3(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 14; gpu->ubwc_config.amsbc =3D 1; @@ -1230,7 +1239,7 @@ static int hw_init(struct msm_gpu *gpu) if (adreno_is_a690(adreno_gpu)) gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90); /* Set dualQ + disable afull for A660 GPU */ - else if (adreno_is_a660(adreno_gpu)) + else if (adreno_is_a660(adreno_gpu) || adreno_is_a663(adreno_gpu)) gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); else if (adreno_is_a7xx(adreno_gpu)) gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/ad= reno/a6xx_hfi.c index cdb3f6e74d3e..f1196d66055c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -478,6 +478,37 @@ static void a660_build_bw_table(struct a6xx_hfi_msg_bw= _table *msg) msg->cnoc_cmds_data[1][0] =3D 0x60000001; } =20 +static void a663_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) +{ + /* + * Send a single "off" entry just to get things running + * TODO: bus scaling + */ + msg->bw_level_num =3D 1; + + msg->ddr_cmds_num =3D 3; + msg->ddr_wait_bitmask =3D 0x07; + + msg->ddr_cmds_addrs[0] =3D 0x50004; + msg->ddr_cmds_addrs[1] =3D 0x50000; + msg->ddr_cmds_addrs[2] =3D 0x500b4; + + msg->ddr_cmds_data[0][0] =3D 0x40000000; + msg->ddr_cmds_data[0][1] =3D 0x40000000; + msg->ddr_cmds_data[0][2] =3D 0x40000000; + + /* + * These are the CX (CNOC) votes - these are used by the GMU but the + * votes are known and fixed for the target + */ + msg->cnoc_cmds_num =3D 1; + msg->cnoc_wait_bitmask =3D 0x01; + + msg->cnoc_cmds_addrs[0] =3D 0x50058; + msg->cnoc_cmds_data[0][0] =3D 0x40000000; + msg->cnoc_cmds_data[1][0] =3D 0x60000001; +} + static void adreno_7c3_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) { /* @@ -646,6 +677,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) adreno_7c3_build_bw_table(&msg); else if (adreno_is_a660(adreno_gpu)) a660_build_bw_table(&msg); + else if (adreno_is_a663(adreno_gpu)) + a663_build_bw_table(&msg); else if (adreno_is_a690(adreno_gpu)) a690_build_bw_table(&msg); else if (adreno_is_a730(adreno_gpu)) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 610ad59ce180..e71f420f8b3a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -470,6 +470,11 @@ static inline int adreno_is_a680(const struct adreno_g= pu *gpu) return adreno_is_revn(gpu, 680); } =20 +static inline int adreno_is_a663(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] =3D=3D 0x06060300; +} + static inline int adreno_is_a690(const struct adreno_gpu *gpu) { return gpu->info->chip_ids[0] =3D=3D 0x06090000; --=20 2.45.2 From nobody Tue Nov 26 04:31:31 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8B031FEFBE; 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Signed-off-by: Puranam V G Tejaswi Signed-off-by: Akhil P Oommen Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Docum= entation/devicetree/bindings/display/msm/gmu.yaml index b1bd372996d5..ab884e236429 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -125,6 +125,7 @@ allOf: enum: - qcom,adreno-gmu-635.0 - qcom,adreno-gmu-660.1 + - qcom,adreno-gmu-663.0 then: properties: reg: --=20 2.45.2 From nobody Tue Nov 26 04:31:31 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B0581E282D; Mon, 21 Oct 2024 21:47:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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As of now all SKUs have the same GPU fmax, so there is no requirement of speed bin support. Signed-off-by: Puranam V G Tejaswi Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 94 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index e8dbc8d820a6..c6cb18193787 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3072,6 +3072,100 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells =3D <1>; }; =20 + gpu: gpu@3d00000 { + compatible =3D "qcom,adreno-663.0", "qcom,adreno"; + reg =3D <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names =3D "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts =3D ; + iommus =3D <&adreno_smmu 0 0xc00>, + <&adreno_smmu 1 0xc00>; + operating-points-v2 =3D <&gpu_opp_table>; + qcom,gmu =3D <&gmu>; + interconnects =3D <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "gfx-mem"; + #cooling-cells =3D <2>; + + status =3D "disabled"; + + gpu_zap_shader: zap-shader { + memory-region =3D <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-405000000 { + opp-hz =3D /bits/ 64 <405000000>; + opp-level =3D ; + opp-peak-kBps =3D <5285156>; + }; + + opp-676000000 { + opp-hz =3D /bits/ 64 <676000000>; + opp-level =3D ; + opp-peak-kBps =3D <8171875>; + }; + + opp-778000000 { + opp-hz =3D /bits/ 64 <778000000>; + opp-level =3D ; + opp-peak-kBps =3D <10687500>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-level =3D ; + opp-peak-kBps =3D <12484375>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible =3D "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; + reg =3D <0x0 0x03d6a000 0x0 0x34000>, + <0x0 0x03de0000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names =3D "gmu", "rscc", "gmu_pdc"; + interrupts =3D , + ; + interrupt-names =3D "hfi", "gmu"; + clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 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Signed-off-by: Puranam V G Tejaswi Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/d= ts/qcom/sa8775p-ride.dtsi index 0c1b21def4b6..4901163df8f3 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -407,6 +407,14 @@ queue3 { }; }; =20 +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sa8775p/a663_zap.mbn"; +}; + &i2c11 { clock-frequency =3D <400000>; pinctrl-0 =3D <&qup_i2c11_default>; --=20 2.45.2