From nobody Tue Nov 26 06:26:15 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CE09200C9D; Mon, 21 Oct 2024 23:04:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729551860; cv=none; b=f6COZmMVuRxYAlET/oyJyrI/yofTT8duRA1TfJsn5yClRMwzsZ30UTUaLXPM0spY8U7NcqwHyxYv9Ehzin5EQgRXLBLxRTBcpN+Wh+GM17BLYRo3yaH9bjc6p+2l7DLyQO5G3vgpU2UWQFO6Uij4B3W/WoMhavxzsdel5ZDWtng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729551860; c=relaxed/simple; bh=7g7WJ64a6XbG9+5/DtkleYkFcgumIDo6V2DBD0UJI3A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pUjY5J301tX5FY+rMojeqjkie2x6L6/q48VS9cGt6bd6RTzbEpHjVnDq2eubRpXq90NoDh7mbpYrWEvoegnGZrItFBk/ZgvrkMQHvegSUiIjVVPpZFCbX7Ac0SlODc0+po46DksljsIh5ByYK5+5EbVgQuyFHyfn/msuV6rCMvs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=AvAzsuE3; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="AvAzsuE3" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49LN3umr031865; Mon, 21 Oct 2024 23:04:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= RTwjklxf7XUVJUkFBfiRIGllVw2TeOo3mTS19UObwRI=; b=AvAzsuE3b6fJAf/4 hskCVb2LpXwGe171V/kBRG9l+W6yeu52zM4iD+Nii5WMrgzT1+XjewTtO6YSiAmP 6UrkwDiT5+Y6/N6lVihnhXf38hsakg949vmYJS91NXX2xmm7u9NaRgOCZLEtfd0N 2AiPybK1/ZhIrZ92hpi8ZDoomKrVK0Di8Afwa1KEdfygxQ0pyilW2ZU9c9PeVyPI lae5BH6wITNpu0Jhhs/uVn/HrZ9gQlEq3G60knohwJqtWtPHBFDdcs/PUbiNjsEF OlVv2VX4jYkpC1xu+FtcBuU+9Ny1G83GZFkIs622uBx9imy/HEcilNzFsCRaDz6h Z+bOlQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42c6rj67d2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 21 Oct 2024 23:04:14 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49LN4DOv009018 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 21 Oct 2024 23:04:13 GMT Received: from hu-molvera-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 21 Oct 2024 16:04:13 -0700 From: Melody Olvera To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Trilok Soni , "Satya Durga Srinivasu Prabhala --cc=linux-arm-msm @ vger . kernel . org" CC: , , , Melody Olvera Subject: [PATCH 6/7] dt-bindings: clock: qcom: Document the SM8750 TCSR Clock Controller Date: Mon, 21 Oct 2024 16:03:58 -0700 Message-ID: <20241021230359.2632414-7-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20241021230359.2632414-1-quic_molvera@quicinc.com> References: <20241021230359.2632414-1-quic_molvera@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: eGwecT1VnHv8MYao2qJqQfh7FMMFxfAQ X-Proofpoint-ORIG-GUID: eGwecT1VnHv8MYao2qJqQfh7FMMFxfAQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 bulkscore=0 malwarescore=0 mlxscore=0 spamscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410210163 Content-Type: text/plain; charset="utf-8" From: Taniya Das Add bindings documentation for the SM8750 Clock Controller. Signed-off-by: Taniya Das Signed-off-by: Melody Olvera Acked-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 2 ++ include/dt-bindings/clock/qcom,sm8750-tcsr.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sm8750-tcsr.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 48fdd562d743..e7d521355699 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -16,6 +16,7 @@ description: | See also: - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h + - include/dt-bindings/clock/qcom,sm8750-tcsr.h =20 properties: compatible: @@ -23,6 +24,7 @@ properties: - enum: - qcom,sm8550-tcsr - qcom,sm8650-tcsr + - qcom,sm8750-tcsr - qcom,x1e80100-tcsr - const: syscon =20 diff --git a/include/dt-bindings/clock/qcom,sm8750-tcsr.h b/include/dt-bind= ings/clock/qcom,sm8750-tcsr.h new file mode 100644 index 000000000000..1c502ac7c7f4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-tcsr.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H + +/* TCSR_CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_UFS_CLKREF_EN 1 +#define TCSR_USB2_CLKREF_EN 2 +#define TCSR_USB3_CLKREF_EN 3 + +#endif --=20 2.46.1