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([178.197.202.204]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4316f5c2df7sm56460595e9.33.2024.10.21.05.49.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 05:49:26 -0700 (PDT) From: Stefan Eichenberger To: hongxing.zhu@nxp.com, l.stach@pengutronix.de, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, francesco.dolcini@toradex.com, Frank.li@nxp.com Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, Stefan Eichenberger Subject: [PATCH v3] PCI: imx6: Add suspend/resume support for i.MX6QDL Date: Mon, 21 Oct 2024 14:49:13 +0200 Message-ID: <20241021124922.5361-1-eichest@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefan Eichenberger The suspend/resume support is broken on the i.MX6QDL platform. This patch resets the link upon resuming to recover functionality. It shares most of the sequences with other i.MX devices but does not touch the critical registers, which might break PCIe. This patch addresses the same issue as the following downstream commit: https://github.com/nxp-imx/linux-imx/commit/4e92355e1f79d225ea842511fcfd42b= 343b32995 In comparison this patch will also reset the device if possible because the downstream patch alone would still make the ath10k driver crash. Without this patch suspend/resume will not work if a PCIe device is connected. The kernel will hang on resume and print an error: ath10k_pci 0000:01:00.0: Unable to change power state from D3hot to D0, dev= ice inaccessible 8<--- cut here --- Unhandled fault: imprecise external abort (0x1406) at 0x0106f944 Signed-off-by: Stefan Eichenberger --- Changes in v3: - Added a new flag to the driver data to indicate that the suspend/resume is broken on the i.MX6QDL platform. (Frank) - Fix comments to be more relevant (Mani) - Use imx_pcie_assert_core_reset in suspend (Mani) drivers/pci/controller/dwc/pci-imx6.c | 57 +++++++++++++++++++++------ 1 file changed, 46 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 808d1f1054173..09e3b15f0908a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -82,6 +82,11 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) #define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) +/** + * Because of ERR005723 (PCIe does not support L2 power down) we need to + * workaround suspend resume on some devices which are affected by this er= rata. + */ +#define IMX_PCIE_FLAG_BROKEN_SUSPEND BIT(9) =20 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) =20 @@ -1237,9 +1242,19 @@ static int imx_pcie_suspend_noirq(struct device *dev) return 0; =20 imx_pcie_msi_save_restore(imx_pcie, true); - imx_pcie_pm_turnoff(imx_pcie); - imx_pcie_stop_link(imx_pcie->pci); - imx_pcie_host_exit(pp); + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_BROKEN_SUSPEND)) { + /** + * The minimum for a workaround would be to set PERST# and to + * set the PCIE_TEST_PD flag. However, we can also disable the + * clock which saves some power. + */ + imx_pcie_assert_core_reset(imx_pcie); + imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); + } else { + imx_pcie_pm_turnoff(imx_pcie); + imx_pcie_stop_link(imx_pcie->pci); + imx_pcie_host_exit(pp); + } =20 return 0; } @@ -1253,14 +1268,32 @@ static int imx_pcie_resume_noirq(struct device *dev) if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; =20 - ret =3D imx_pcie_host_init(pp); - if (ret) - return ret; - imx_pcie_msi_save_restore(imx_pcie, false); - dw_pcie_setup_rc(pp); + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_BROKEN_SUSPEND)) { + ret =3D imx_pcie->drvdata->enable_ref_clk(imx_pcie, true); + if (ret) + return ret; + ret =3D imx_pcie_deassert_core_reset(imx_pcie); + if (ret) + return ret; + /** + * Using PCIE_TEST_PD seems to disable msi and powers down the + * root complex. This is why we have to setup the rc again and + * why we have to restore the msi register. + */ + ret =3D dw_pcie_setup_rc(&imx_pcie->pci->pp); + if (ret) + return ret; + imx_pcie_msi_save_restore(imx_pcie, false); + } else { + ret =3D imx_pcie_host_init(pp); + if (ret) + return ret; + imx_pcie_msi_save_restore(imx_pcie, false); + dw_pcie_setup_rc(pp); =20 - if (imx_pcie->link_is_up) - imx_pcie_start_link(imx_pcie->pci); + if (imx_pcie->link_is_up) + imx_pcie_start_link(imx_pcie->pci); + } =20 return 0; } @@ -1485,7 +1518,9 @@ static const struct imx_pcie_drvdata drvdata[] =3D { [IMX6Q] =3D { .variant =3D IMX6Q, .flags =3D IMX_PCIE_FLAG_IMX_PHY | - IMX_PCIE_FLAG_IMX_SPEED_CHANGE, + IMX_PCIE_FLAG_IMX_SPEED_CHANGE | + IMX_PCIE_FLAG_BROKEN_SUSPEND | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length =3D 0x200, .gpr =3D "fsl,imx6q-iomuxc-gpr", .clk_names =3D imx6q_clks, --=20 2.43.0