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charset="utf-8" From: Yassine Oudjana Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets on MT6735. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 4 ++ drivers/clk/mediatek/Kconfig | 32 +++++++++ drivers/clk/mediatek/Makefile | 4 ++ drivers/clk/mediatek/clk-mt6735-imgsys.c | 57 ++++++++++++++++ drivers/clk/mediatek/clk-mt6735-mfgcfg.c | 61 +++++++++++++++++ drivers/clk/mediatek/clk-mt6735-vdecsys.c | 81 +++++++++++++++++++++++ drivers/clk/mediatek/clk-mt6735-vencsys.c | 53 +++++++++++++++ 7 files changed, 292 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-imgsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-mfgcfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-vdecsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-vencsys.c diff --git a/MAINTAINERS b/MAINTAINERS index 25484783f6a0b..939f9d29fc9bf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14533,9 +14533,13 @@ L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c +F: drivers/clk/mediatek/clk-mt6735-imgsys.c F: drivers/clk/mediatek/clk-mt6735-infracfg.c +F: drivers/clk/mediatek/clk-mt6735-mfgcfg.c F: drivers/clk/mediatek/clk-mt6735-pericfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c +F: drivers/clk/mediatek/clk-mt6735-vdecsys.c +F: drivers/clk/mediatek/clk-mt6735-vencsys.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 7a33f9e92d963..4dd6d2d6263fd 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -133,6 +133,38 @@ config COMMON_CLK_MT6735 by apmixedsys, topckgen, infracfg and pericfg on the MediaTek MT6735 SoC. =20 +config COMMON_CLK_MT6735_IMGSYS + tristate "Clock driver for MediaTek MT6735 imgsys" + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This enables a driver for clocks provided by imgsys + on the MediaTek MT6735 SoC. + +config COMMON_CLK_MT6735_MFGCFG + tristate "Clock driver for MediaTek MT6735 mfgcfg" + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This enables a driver for clocks and resets provided + by mfgcfg on the MediaTek MT6735 SoC. + +config COMMON_CLK_MT6735_VDECSYS + tristate "Clock driver for MediaTek MT6735 vdecsys" + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This enables a driver for clocks and resets provided + by vdecsys on the MediaTek MT6735 SoC. + +config COMMON_CLK_MT6735_VENCSYS + tristate "Clock driver for MediaTek MT6735 vencsys" + depends on (ARCH_MEDIATEK && COMMON_CLK_MT6735) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This enables a driver for clocks provided by vencsys + on the MediaTek MT6735 SoC. + config COMMON_CLK_MT6765 bool "Clock driver for MediaTek MT6765" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 70456ffc6c492..6efec95406bd5 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -3,6 +3,10 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mtk.o clk-pll.o= clk-gate.o clk-apmixed. obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) +=3D clk-fhctl.o clk-pllfh.o =20 obj-$(CONFIG_COMMON_CLK_MT6735) +=3D clk-mt6735-apmixedsys.o clk-mt6735-in= fracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o +obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) +=3D clk-mt6735-imgsys.o +obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) +=3D clk-mt6735-mfgcfg.o +obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) +=3D clk-mt6735-vdecsys.o +obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) +=3D clk-mt6735-vencsys.o obj-$(CONFIG_COMMON_CLK_MT6765) +=3D clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) +=3D clk-mt6765-audio.o obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) +=3D clk-mt6765-cam.o diff --git a/drivers/clk/mediatek/clk-mt6735-imgsys.c b/drivers/clk/mediate= k/clk-mt6735-imgsys.c new file mode 100644 index 0000000000000..c564f8f724324 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-imgsys.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define IMG_CG_CON 0x00 +#define IMG_CG_SET 0x04 +#define IMG_CG_CLR 0x08 + +static struct mtk_gate_regs imgsys_cg_regs =3D { + .set_ofs =3D IMG_CG_SET, + .clr_ofs =3D IMG_CG_CLR, + .sta_ofs =3D IMG_CG_CON, +}; + +static const struct mtk_gate imgsys_gates[] =3D { + GATE_MTK(CLK_IMG_SMI_LARB2, "smi_larb2", "mm_sel", &imgsys_cg_regs, 0, &m= tk_clk_gate_ops_setclr), + GATE_MTK(CLK_IMG_CAM_SMI, "cam_smi", "mm_sel", &imgsys_cg_regs, 5, &mtk_c= lk_gate_ops_setclr), + GATE_MTK(CLK_IMG_CAM_CAM, "cam_cam", "mm_sel", &imgsys_cg_regs, 6, &mtk_c= lk_gate_ops_setclr), + GATE_MTK(CLK_IMG_SEN_TG, "sen_tg", "mm_sel", &imgsys_cg_regs, 7, &mtk_clk= _gate_ops_setclr), + GATE_MTK(CLK_IMG_SEN_CAM, "sen_cam", "mm_sel", &imgsys_cg_regs, 8, &mtk_c= lk_gate_ops_setclr), + GATE_MTK(CLK_IMG_CAM_SV, "cam_sv", "mm_sel", &imgsys_cg_regs, 9, &mtk_clk= _gate_ops_setclr), + GATE_MTK(CLK_IMG_SUFOD, "sufod", "mm_sel", &imgsys_cg_regs, 10, &mtk_clk_= gate_ops_setclr), + GATE_MTK(CLK_IMG_FD, "fd", "mm_sel", &imgsys_cg_regs, 11, &mtk_clk_gate_o= ps_setclr), +}; + +static const struct mtk_clk_desc imgsys_clks =3D { + .clks =3D imgsys_gates, + .num_clks =3D ARRAY_SIZE(imgsys_gates), +}; + +static const struct of_device_id of_match_mt6735_imgsys[] =3D { + { .compatible =3D "mediatek,mt6735-imgsys", .data =3D &imgsys_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_imgsys =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-imgsys", + .of_match_table =3D of_match_mt6735_imgsys, + }, +}; +module_platform_driver(clk_mt6735_imgsys); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("MediaTek MT6735 imgsys clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-mfgcfg.c b/drivers/clk/mediate= k/clk-mt6735-mfgcfg.c new file mode 100644 index 0000000000000..1f5aedddf209d --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define MFG_CG_CON 0x00 +#define MFG_CG_SET 0x04 +#define MFG_CG_CLR 0x08 +#define MFG_RESET 0x0c + +static struct mtk_gate_regs mfgcfg_cg_regs =3D { + .set_ofs =3D MFG_CG_SET, + .clr_ofs =3D MFG_CG_CLR, + .sta_ofs =3D MFG_CG_CON, +}; + +static const struct mtk_gate mfgcfg_gates[] =3D { + GATE_MTK(CLK_MFG_BG3D, "bg3d", "mfg_sel", &mfgcfg_cg_regs, 0, &mtk_clk_ga= te_ops_setclr), +}; + +static u16 mfgcfg_rst_ofs[] =3D { MFG_RESET }; + +static const struct mtk_clk_rst_desc mfgcfg_resets =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D mfgcfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(mfgcfg_rst_ofs) +}; + +static const struct mtk_clk_desc mfgcfg_clks =3D { + .clks =3D mfgcfg_gates, + .num_clks =3D ARRAY_SIZE(mfgcfg_gates), + + .rst_desc =3D &mfgcfg_resets +}; + +static const struct of_device_id of_match_mt6735_mfgcfg[] =3D { + { .compatible =3D "mediatek,mt6735-mfgcfg", .data =3D &mfgcfg_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_mfgcfg =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-mfgcfg", + .of_match_table =3D of_match_mt6735_mfgcfg, + }, +}; +module_platform_driver(clk_mt6735_mfgcfg); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 mfgcfg clock and reset driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-vdecsys.c b/drivers/clk/mediat= ek/clk-mt6735-vdecsys.c new file mode 100644 index 0000000000000..f59b481aaa6da --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-vdecsys.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include +#include + +#define VDEC_CKEN_SET 0x00 +#define VDEC_CKEN_CLR 0x04 +#define SMI_LARB1_CKEN_SET 0x08 +#define SMI_LARB1_CKEN_CLR 0x0c +#define VDEC_RESETB_CON 0x10 +#define SMI_LARB1_RESETB_CON 0x14 + +#define RST_NR_PER_BANK 32 + +static struct mtk_gate_regs vdec_cg_regs =3D { + .set_ofs =3D VDEC_CKEN_SET, + .clr_ofs =3D VDEC_CKEN_CLR, + .sta_ofs =3D VDEC_CKEN_SET, +}; + +static struct mtk_gate_regs smi_larb1_cg_regs =3D { + .set_ofs =3D SMI_LARB1_CKEN_SET, + .clr_ofs =3D SMI_LARB1_CKEN_CLR, + .sta_ofs =3D SMI_LARB1_CKEN_SET, +}; + +static const struct mtk_gate vdecsys_gates[] =3D { + GATE_MTK(CLK_VDEC_VDEC, "vdec", "vdec_sel", &vdec_cg_regs, 0, &mtk_clk_ga= te_ops_setclr_inv), + GATE_MTK(CLK_VDEC_SMI_LARB1, "smi_larb1", "vdec_sel", &smi_larb1_cg_regs,= 0, &mtk_clk_gate_ops_setclr_inv), +}; + +static u16 vdecsys_rst_bank_ofs[] =3D { VDEC_RESETB_CON, SMI_LARB1_RESETB_= CON }; + +static u16 vdecsys_rst_idx_map[] =3D { + [MT6735_VDEC_RST0_VDEC] =3D 0 * RST_NR_PER_BANK + 0, + + [MT6735_VDEC_RST1_SMI_LARB1] =3D 1 * RST_NR_PER_BANK + 0, +}; + +static const struct mtk_clk_rst_desc vdecsys_resets =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D vdecsys_rst_bank_ofs, + .rst_bank_nr =3D ARRAY_SIZE(vdecsys_rst_bank_ofs), + .rst_idx_map =3D vdecsys_rst_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(vdecsys_rst_idx_map) +}; + +static const struct mtk_clk_desc vdecsys_clks =3D { + .clks =3D vdecsys_gates, + .num_clks =3D ARRAY_SIZE(vdecsys_gates), + + .rst_desc =3D &vdecsys_resets +}; + +static const struct of_device_id of_match_mt6735_vdecsys[] =3D { + { .compatible =3D "mediatek,mt6735-vdecsys", .data =3D &vdecsys_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_vdecsys =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-vdecsys", + .of_match_table =3D of_match_mt6735_vdecsys, + }, +}; +module_platform_driver(clk_mt6735_vdecsys); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("MediaTek MT6735 vdecsys clock and reset driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-vencsys.c b/drivers/clk/mediat= ek/clk-mt6735-vencsys.c new file mode 100644 index 0000000000000..8dec7f98492ac --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-vencsys.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define VENC_CG_CON 0x00 +#define VENC_CG_SET 0x04 +#define VENC_CG_CLR 0x08 + +static struct mtk_gate_regs venc_cg_regs =3D { + .set_ofs =3D VENC_CG_SET, + .clr_ofs =3D VENC_CG_CLR, + .sta_ofs =3D VENC_CG_CON, +}; + +static const struct mtk_gate vencsys_gates[] =3D { + GATE_MTK(CLK_VENC_SMI_LARB3, "smi_larb3", "mm_sel", &venc_cg_regs, 0, &mt= k_clk_gate_ops_setclr_inv), + GATE_MTK(CLK_VENC_VENC, "venc", "mm_sel", &venc_cg_regs, 4, &mtk_clk_gate= _ops_setclr_inv), + GATE_MTK(CLK_VENC_JPGENC, "jpgenc", "mm_sel", &venc_cg_regs, 8, &mtk_clk_= gate_ops_setclr_inv), + GATE_MTK(CLK_VENC_JPGDEC, "jpgdec", "mm_sel", &venc_cg_regs, 12, &mtk_clk= _gate_ops_setclr_inv), +}; + +static const struct mtk_clk_desc vencsys_clks =3D { + .clks =3D vencsys_gates, + .num_clks =3D ARRAY_SIZE(vencsys_gates), +}; + +static const struct of_device_id of_match_mt6735_vencsys[] =3D { + { .compatible =3D "mediatek,mt6735-vencsys", .data =3D &vencsys_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_vencsys =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-vencsys", + .of_match_table =3D of_match_mt6735_vencsys, + }, +}; +module_platform_driver(clk_mt6735_vencsys); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 vencsys clock driver"); +MODULE_LICENSE("GPL"); --=20 2.47.0