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From: Md Sadre Alam <quic_mdalam@quicinc.com>
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Subject: [PATCH v12 1/8] spi: dt-bindings: Introduce qcom,spi-qpic-snand
Date: Mon, 21 Oct 2024 17:26:13 +0530
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Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs.
It can work both in serial and parallel mode and supports typical
SPI-NAND page cache operations.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
Change in [v12]
* Added Reviewed-by tag
Change in [v11]
* Dropped Reviewed-by tag
* Added Soc based compitable "qcom,ipq9574-snand"
=20
Change in [v10]
* No change
Change in [v9]
* No change
Change in [v8]
* No change
Change in [v7]
* No change
Change in [v6]
* No change
Change in [v5]
* No change
Change in [v4]
* Fix spelling mistake in HW description
* Added commit message
* Removed '|' from description
* Removed minItems in clock
* Added blank line
* Removed co-developed by
Change in [v3]
* Updated commit message, removed "dt-bindings" from commit
message
* Updated compatible name as file name
* Added hardware description
* Documented clock-name
* Moved dma-names property to top
* Droped unused label "qpic_nand"
* Fixed indentation in example dt node
Change in [v2]
* Added initial support for dt-bindings
Change in [v1]
* This patch was not included in [v1]
.../bindings/spi/qcom,spi-qpic-snand.yaml | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-sna=
nd.yaml
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml=
b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
new file mode 100644
index 000000000000..aa3f93319203
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QPIC NAND controller
+
+maintainers:
+ - Md sadre Alam <quic_mdalam@quicinc.com>
+
+description:
+ The QCOM QPIC-SPI-NAND flash controller is an extended version of
+ the QCOM QPIC NAND flash controller. It can work both in serial
+ and parallel mode. It supports typical SPI-NAND page cache
+ operations in single, dual or quad IO mode with pipelined ECC
+ encoding/decoding using the QPIC ECC HW engine.
+
+allOf:
+ - $ref: /schemas/spi/spi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq9574-snand
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: core
+ - const: aon
+ - const: iom
+
+ dmas:
+ items:
+ - description: tx DMA channel
+ - description: rx DMA channel
+ - description: cmd DMA channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+ - const: cmd
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+ spi@79b0000 {
+ compatible =3D "qcom,ipq9574-snand";
+ reg =3D <0x1ac00000 0x800>;
+
+ clocks =3D <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>,
+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
+ clock-names =3D "core", "aon", "iom";
+
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+
+ flash@0 {
+ compatible =3D "spi-nand";
+ reg =3D <0>;
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ nand-ecc-engine =3D <&qpic_nand>;
+ nand-ecc-strength =3D <4>;
+ nand-ecc-step-size =3D <512>;
+ };
+ };
--=20
2.34.1