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charset="utf-8" The UART of SG2044 is modified version of the standard Synopsys DesignWare UART. The UART on SG2044 relys on the internal divisor and can not set right clock rate for the common bitrates. Add compatibles string for the Sophgo SG2044 uarts. Signed-off-by: Inochi Amaoto --- .../devicetree/bindings/serial/snps-dw-apb-uart.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 4cdb0dcaccf3..6963f89a1848 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -58,6 +58,10 @@ properties: - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart - const: snps,dw-apb-uart + - items: + - enum: + - sophgo,sg2044-uart + - const: snps,dw-apb-uart - items: - enum: - starfive,jh7100-hsuart --=20 2.47.0 From nobody Tue Nov 26 05:35:56 2024 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4B141DD861; Mon, 21 Oct 2024 07:26:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 21 Oct 2024 00:26:50 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7eee884dsm19919975ad.9.2024.10.21.00.26.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 00:26:50 -0700 (PDT) From: Inochi Amaoto To: Chen Wang , Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Andy Shevchenko , Paul Walmsley , Palmer Dabbelt , Albert Ou , Inochi Amaoto Cc: Yixun Lan , Inochi Amaoto , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 2/2] serial: 8250_dw: Add Sophgo SG2044 quirk Date: Mon, 21 Oct 2024 15:26:06 +0800 Message-ID: <20241021072606.585878-3-inochiama@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241021072606.585878-1-inochiama@gmail.com> References: <20241021072606.585878-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SG2044 relys on an internal divisor when calculating bitrate, which means a wrong clock for the most common bitrates. So add a quirk for this uart device to skip the set rate call and only relys on the internal UART divisor. Signed-off-by: Inochi Amaoto Reviewed-by: Andy Shevchenko Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/tty/serial/8250/8250_dw.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/82= 50_dw.c index ab9e7f204260..51894c93c8a3 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -750,7 +750,7 @@ static const struct dw8250_platform_data dw8250_renesas= _rzn1_data =3D { .quirks =3D DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC, }; =20 -static const struct dw8250_platform_data dw8250_starfive_jh7100_data =3D { +static const struct dw8250_platform_data dw8250_skip_set_rate_data =3D { .usr_reg =3D DW_UART_USR, .quirks =3D DW_UART_QUIRK_SKIP_SET_RATE, }; @@ -760,7 +760,8 @@ static const struct of_device_id dw8250_of_match[] =3D { { .compatible =3D "cavium,octeon-3860-uart", .data =3D &dw8250_octeon_386= 0_data }, { .compatible =3D "marvell,armada-38x-uart", .data =3D &dw8250_armada_38x= _data }, { .compatible =3D "renesas,rzn1-uart", .data =3D &dw8250_renesas_rzn1_dat= a }, - { .compatible =3D "starfive,jh7100-uart", .data =3D &dw8250_starfive_jh71= 00_data }, + { .compatible =3D "sophgo,sg2044-uart", .data =3D &dw8250_skip_set_rate_d= ata }, + { .compatible =3D "starfive,jh7100-uart", .data =3D &dw8250_skip_set_rate= _data }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, dw8250_of_match); --=20 2.47.0