From nobody Tue Nov 26 10:41:44 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B4081EA90; Mon, 21 Oct 2024 00:29:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729470594; cv=none; b=NYsfoJPv39CLVUUNhHJsqcMMsFTh7vKJFfkzUhj9c5fRjWvdvU0aULE9A/NsjElZWlOLQpXEu1MC+6gaY6L0OvtCTdB6V7NT51HwX0JliPBGt7PB1nIstoy0vaW5lUBPR3xCKxS89zf4TrYs8MN0DAi2qs1MMz10wilyW1N1cew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729470594; c=relaxed/simple; bh=37CoKYQY/K3vVxK+pZWLWenOAuTcA9gdgPZY9Xy3FH0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LFkBzggQbrRstC6T3nZUU1GEGahUyVio1qmTvP7qJ0BmQqKJ22n4iFqf5synh/6XDsHRon7K0ufYs/CjhUCcXTEW+R7J6dZHT5AccBZDrmssrPSzA1t2LvE9orXPPPYUNB/8ZsEli7OQIycKznLDFAV6fdk0bd7ilNZ6RrOi+Ms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=o/pntV4f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o/pntV4f" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 298E6C32781; Mon, 21 Oct 2024 00:29:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729470593; bh=37CoKYQY/K3vVxK+pZWLWenOAuTcA9gdgPZY9Xy3FH0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o/pntV4fvxNp74EG7L0BOfz/Y3MKLRRECrwFRjgeDEIXmaA3+rceRzCKbuWLMPE+f qtyzibI8U93xIJE79UM9hPanmlBjvSKd1aK5065xqOnPrVw6g2inNhXFW+9vXVPUGG PvoxQwVL/sz5QUuCtfH2cgbO+omhgkUzibTqImLp+epZArwlzvMA0ggiUY3jkymx/V uwDzgQu1GERDcJDSQtQFvjmEi+D3v4y1Z3msRQLPY2IhaOtB4g61KJyGvYzc9RSJMx Wt7NB07EgzhgoYwY4B2KceV69Qm7s/1lAO0DbqYhs1efNPWjjtqmREiV0/9PjhmwQb sJnR3Opzy1Jjg== From: Eric Biggers To: linux-kernel@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, linux-ext4@vger.kernel.org, linux-f2fs-devel@lists.sourceforge.net, linux-mips@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, loongarch@lists.linux.dev, sparclinux@vger.kernel.org, x86@kernel.org Subject: [PATCH 05/15] mips/crc32: expose CRC32 functions through lib Date: Sun, 20 Oct 2024 17:29:25 -0700 Message-ID: <20241021002935.325878-6-ebiggers@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241021002935.325878-1-ebiggers@kernel.org> References: <20241021002935.325878-1-ebiggers@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Eric Biggers Move the mips CRC32 assembly code into the lib directory and wire it up to the library interface. This allows it to be used without going through the crypto API. It remains usable via the crypto API too via the shash algorithms that use the library interface. Thus all the arch-specific "shash" code becomes unnecessary and is removed. Note: to see the diff from arch/mips/crypto/crc32-mips.c to arch/mips/lib/crc32-mips.c, view this commit with 'git show -M10'. Signed-off-by: Eric Biggers --- arch/mips/Kconfig | 5 +- arch/mips/configs/eyeq5_defconfig | 1 - arch/mips/configs/eyeq6_defconfig | 1 - arch/mips/configs/generic/32r6.config | 2 - arch/mips/configs/generic/64r6.config | 1 - arch/mips/crypto/Kconfig | 9 - arch/mips/crypto/Makefile | 2 - arch/mips/crypto/crc32-mips.c | 354 -------------------------- arch/mips/lib/Makefile | 2 + arch/mips/lib/crc32-mips.c | 184 +++++++++++++ 10 files changed, 187 insertions(+), 374 deletions(-) delete mode 100644 arch/mips/crypto/crc32-mips.c create mode 100644 arch/mips/lib/crc32-mips.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 397edf05dd722..f80ea80d792f5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1993,15 +1993,15 @@ config CPU_MIPSR5 select MIPS_SPRAM =20 config CPU_MIPSR6 bool default y if CPU_MIPS32_R6 || CPU_MIPS64_R6 + select ARCH_HAS_CRC32 select CPU_HAS_RIXI select CPU_HAS_DIEI if !CPU_DIEI_BROKEN select HAVE_ARCH_BITREVERSE select MIPS_ASID_BITS_VARIABLE - select MIPS_CRC_SUPPORT select MIPS_SPRAM =20 config TARGET_ISA_REV int default 1 if CPU_MIPSR1 @@ -2473,13 +2473,10 @@ config MIPS_ASID_BITS default 8 =20 config MIPS_ASID_BITS_VARIABLE bool =20 -config MIPS_CRC_SUPPORT - bool - # R4600 erratum. Due to the lack of errata information the exact # technical details aren't known. I've experimentally found that disabling # interrupts during indexed I-cache flushes seems to be sufficient to deal # with the issue. config WAR_R4600_V1_INDEX_ICACHEOP diff --git a/arch/mips/configs/eyeq5_defconfig b/arch/mips/configs/eyeq5_de= fconfig index ae9a09b16e40b..ff7af5dc6d9d3 100644 --- a/arch/mips/configs/eyeq5_defconfig +++ b/arch/mips/configs/eyeq5_defconfig @@ -97,11 +97,10 @@ CONFIG_NFS_FS=3Dy CONFIG_NFS_V3_ACL=3Dy CONFIG_NFS_V4=3Dy CONFIG_NFS_V4_1=3Dy CONFIG_NFS_V4_2=3Dy CONFIG_ROOT_NFS=3Dy -CONFIG_CRYPTO_CRC32_MIPS=3Dy CONFIG_FRAME_WARN=3D1024 CONFIG_DEBUG_FS=3Dy # CONFIG_RCU_TRACE is not set # CONFIG_FTRACE is not set CONFIG_CMDLINE_BOOL=3Dy diff --git a/arch/mips/configs/eyeq6_defconfig b/arch/mips/configs/eyeq6_de= fconfig index 6597d5e88b335..0afbb45a78e8e 100644 --- a/arch/mips/configs/eyeq6_defconfig +++ b/arch/mips/configs/eyeq6_defconfig @@ -100,11 +100,10 @@ CONFIG_NFS_FS=3Dy CONFIG_NFS_V3_ACL=3Dy CONFIG_NFS_V4=3Dy CONFIG_NFS_V4_1=3Dy CONFIG_NFS_V4_2=3Dy CONFIG_ROOT_NFS=3Dy -CONFIG_CRYPTO_CRC32_MIPS=3Dy CONFIG_FRAME_WARN=3D1024 CONFIG_DEBUG_FS=3Dy # CONFIG_RCU_TRACE is not set # CONFIG_FTRACE is not set CONFIG_CMDLINE_BOOL=3Dy diff --git a/arch/mips/configs/generic/32r6.config b/arch/mips/configs/gene= ric/32r6.config index 1a5d5ea4ab2b5..ca606e71f4d02 100644 --- a/arch/mips/configs/generic/32r6.config +++ b/arch/mips/configs/generic/32r6.config @@ -1,4 +1,2 @@ CONFIG_CPU_MIPS32_R6=3Dy CONFIG_HIGHMEM=3Dy - -CONFIG_CRYPTO_CRC32_MIPS=3Dy diff --git a/arch/mips/configs/generic/64r6.config b/arch/mips/configs/gene= ric/64r6.config index 63b4e95f303de..23a3009149570 100644 --- a/arch/mips/configs/generic/64r6.config +++ b/arch/mips/configs/generic/64r6.config @@ -2,7 +2,6 @@ CONFIG_CPU_MIPS64_R6=3Dy CONFIG_64BIT=3Dy CONFIG_MIPS32_O32=3Dy CONFIG_MIPS32_N32=3Dy =20 CONFIG_CPU_HAS_MSA=3Dy -CONFIG_CRYPTO_CRC32_MIPS=3Dy CONFIG_VIRTUALIZATION=3Dy diff --git a/arch/mips/crypto/Kconfig b/arch/mips/crypto/Kconfig index 9003a5c1e879f..7decd40c4e204 100644 --- a/arch/mips/crypto/Kconfig +++ b/arch/mips/crypto/Kconfig @@ -1,18 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 =20 menu "Accelerated Cryptographic Algorithms for CPU (mips)" =20 -config CRYPTO_CRC32_MIPS - tristate "CRC32c and CRC32" - depends on MIPS_CRC_SUPPORT - select CRYPTO_HASH - help - CRC32c and CRC32 CRC algorithms - - Architecture: mips - config CRYPTO_POLY1305_MIPS tristate "Hash functions: Poly1305" depends on MIPS select CRYPTO_ARCH_HAVE_LIB_POLY1305 help diff --git a/arch/mips/crypto/Makefile b/arch/mips/crypto/Makefile index 5e4105cccf9fa..fddc882814123 100644 --- a/arch/mips/crypto/Makefile +++ b/arch/mips/crypto/Makefile @@ -1,12 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 # # Makefile for MIPS crypto files.. # =20 -obj-$(CONFIG_CRYPTO_CRC32_MIPS) +=3D crc32-mips.o - obj-$(CONFIG_CRYPTO_CHACHA_MIPS) +=3D chacha-mips.o chacha-mips-y :=3D chacha-core.o chacha-glue.o AFLAGS_chacha-core.o +=3D -O2 # needed to fill branch delay slots =20 obj-$(CONFIG_CRYPTO_POLY1305_MIPS) +=3D poly1305-mips.o diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c deleted file mode 100644 index 90eacf00cfc31..0000000000000 --- a/arch/mips/crypto/crc32-mips.c +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * crc32-mips.c - CRC32 and CRC32C using optional MIPSr6 instructions - * - * Module based on arm64/crypto/crc32-arm.c - * - * Copyright (C) 2014 Linaro Ltd - * Copyright (C) 2018 MIPS Tech, LLC - */ - -#include -#include -#include -#include -#include -#include -#include - -#include - -enum crc_op_size { - b, h, w, d, -}; - -enum crc_type { - crc32, - crc32c, -}; - -#ifndef TOOLCHAIN_SUPPORTS_CRC -#define _ASM_SET_CRC(OP, SZ, TYPE) \ -_ASM_MACRO_3R(OP, rt, rs, rt2, \ - ".ifnc \\rt, \\rt2\n\t" \ - ".error \"invalid operands \\\"" #OP " \\rt,\\rs,\\rt2\\\"\"\n\t" \ - ".endif\n\t" \ - _ASM_INSN_IF_MIPS(0x7c00000f | (__rt << 16) | (__rs << 21) | \ - ((SZ) << 6) | ((TYPE) << 8)) \ - _ASM_INSN32_IF_MM(0x00000030 | (__rs << 16) | (__rt << 21) | \ - ((SZ) << 14) | ((TYPE) << 3))) -#define _ASM_UNSET_CRC(op, SZ, TYPE) ".purgem " #op "\n\t" -#else /* !TOOLCHAIN_SUPPORTS_CRC */ -#define _ASM_SET_CRC(op, SZ, TYPE) ".set\tcrc\n\t" -#define _ASM_UNSET_CRC(op, SZ, TYPE) -#endif - -#define __CRC32(crc, value, op, SZ, TYPE) \ -do { \ - __asm__ __volatile__( \ - ".set push\n\t" \ - _ASM_SET_CRC(op, SZ, TYPE) \ - #op " %0, %1, %0\n\t" \ - _ASM_UNSET_CRC(op, SZ, TYPE) \ - ".set pop" \ - : "+r" (crc) \ - : "r" (value)); \ -} while (0) - -#define _CRC32_crc32b(crc, value) __CRC32(crc, value, crc32b, 0, 0) -#define _CRC32_crc32h(crc, value) __CRC32(crc, value, crc32h, 1, 0) -#define _CRC32_crc32w(crc, value) __CRC32(crc, value, crc32w, 2, 0) -#define _CRC32_crc32d(crc, value) __CRC32(crc, value, crc32d, 3, 0) -#define _CRC32_crc32cb(crc, value) __CRC32(crc, value, crc32cb, 0, 1) -#define _CRC32_crc32ch(crc, value) __CRC32(crc, value, crc32ch, 1, 1) -#define _CRC32_crc32cw(crc, value) __CRC32(crc, value, crc32cw, 2, 1) -#define _CRC32_crc32cd(crc, value) __CRC32(crc, value, crc32cd, 3, 1) - -#define _CRC32(crc, value, size, op) \ - _CRC32_##op##size(crc, value) - -#define CRC32(crc, value, size) \ - _CRC32(crc, value, size, crc32) - -#define CRC32C(crc, value, size) \ - _CRC32(crc, value, size, crc32c) - -static u32 crc32_mips_le_hw(u32 crc_, const u8 *p, unsigned int len) -{ - u32 crc =3D crc_; - - if (IS_ENABLED(CONFIG_64BIT)) { - for (; len >=3D sizeof(u64); p +=3D sizeof(u64), len -=3D sizeof(u64)) { - u64 value =3D get_unaligned_le64(p); - - CRC32(crc, value, d); - } - - if (len & sizeof(u32)) { - u32 value =3D get_unaligned_le32(p); - - CRC32(crc, value, w); - p +=3D sizeof(u32); - } - } else { - for (; len >=3D sizeof(u32); len -=3D sizeof(u32)) { - u32 value =3D get_unaligned_le32(p); - - CRC32(crc, value, w); - p +=3D sizeof(u32); - } - } - - if (len & sizeof(u16)) { - u16 value =3D get_unaligned_le16(p); - - CRC32(crc, value, h); - p +=3D sizeof(u16); - } - - if (len & sizeof(u8)) { - u8 value =3D *p++; - - CRC32(crc, value, b); - } - - return crc; -} - -static u32 crc32c_mips_le_hw(u32 crc_, const u8 *p, unsigned int len) -{ - u32 crc =3D crc_; - - if (IS_ENABLED(CONFIG_64BIT)) { - for (; len >=3D sizeof(u64); p +=3D sizeof(u64), len -=3D sizeof(u64)) { - u64 value =3D get_unaligned_le64(p); - - CRC32C(crc, value, d); - } - - if (len & sizeof(u32)) { - u32 value =3D get_unaligned_le32(p); - - CRC32C(crc, value, w); - p +=3D sizeof(u32); - } - } else { - for (; len >=3D sizeof(u32); len -=3D sizeof(u32)) { - u32 value =3D get_unaligned_le32(p); - - CRC32C(crc, value, w); - p +=3D sizeof(u32); - } - } - - if (len & sizeof(u16)) { - u16 value =3D get_unaligned_le16(p); - - CRC32C(crc, value, h); - p +=3D sizeof(u16); - } - - if (len & sizeof(u8)) { - u8 value =3D *p++; - - CRC32C(crc, value, b); - } - return crc; -} - -#define CHKSUM_BLOCK_SIZE 1 -#define CHKSUM_DIGEST_SIZE 4 - -struct chksum_ctx { - u32 key; -}; - -struct chksum_desc_ctx { - u32 crc; -}; - -static int chksum_init(struct shash_desc *desc) -{ - struct chksum_ctx *mctx =3D crypto_shash_ctx(desc->tfm); - struct chksum_desc_ctx *ctx =3D shash_desc_ctx(desc); - - ctx->crc =3D mctx->key; - - return 0; -} - -/* - * Setting the seed allows arbitrary accumulators and flexible XOR policy - * If your algorithm starts with ~0, then XOR with ~0 before you set - * the seed. - */ -static int chksum_setkey(struct crypto_shash *tfm, const u8 *key, - unsigned int keylen) -{ - struct chksum_ctx *mctx =3D crypto_shash_ctx(tfm); - - if (keylen !=3D sizeof(mctx->key)) - return -EINVAL; - mctx->key =3D get_unaligned_le32(key); - return 0; -} - -static int chksum_update(struct shash_desc *desc, const u8 *data, - unsigned int length) -{ - struct chksum_desc_ctx *ctx =3D shash_desc_ctx(desc); - - ctx->crc =3D crc32_mips_le_hw(ctx->crc, data, length); - return 0; -} - -static int chksumc_update(struct shash_desc *desc, const u8 *data, - unsigned int length) -{ - struct chksum_desc_ctx *ctx =3D shash_desc_ctx(desc); - - ctx->crc =3D crc32c_mips_le_hw(ctx->crc, data, length); - return 0; -} - -static int chksum_final(struct shash_desc *desc, u8 *out) -{ - struct chksum_desc_ctx *ctx =3D shash_desc_ctx(desc); - - put_unaligned_le32(ctx->crc, out); - return 0; -} - -static int chksumc_final(struct shash_desc *desc, u8 *out) -{ - struct chksum_desc_ctx *ctx =3D shash_desc_ctx(desc); - - put_unaligned_le32(~ctx->crc, out); - return 0; -} - -static int __chksum_finup(u32 crc, const u8 *data, unsigned int len, u8 *o= ut) -{ - put_unaligned_le32(crc32_mips_le_hw(crc, data, len), out); - return 0; -} - -static int __chksumc_finup(u32 crc, const u8 *data, unsigned int len, u8 *= out) -{ - put_unaligned_le32(~crc32c_mips_le_hw(crc, data, len), out); - return 0; -} - -static int chksum_finup(struct shash_desc *desc, const u8 *data, - unsigned int len, u8 *out) -{ - struct chksum_desc_ctx *ctx =3D shash_desc_ctx(desc); - - return __chksum_finup(ctx->crc, data, len, out); -} - -static int chksumc_finup(struct shash_desc *desc, const u8 *data, - unsigned int len, u8 *out) -{ - struct chksum_desc_ctx *ctx =3D shash_desc_ctx(desc); - - return __chksumc_finup(ctx->crc, data, len, out); -} - -static int chksum_digest(struct shash_desc *desc, const u8 *data, - unsigned int length, u8 *out) -{ - struct chksum_ctx *mctx =3D crypto_shash_ctx(desc->tfm); - - return __chksum_finup(mctx->key, data, length, out); -} - -static int chksumc_digest(struct shash_desc *desc, const u8 *data, - unsigned int length, u8 *out) -{ - struct chksum_ctx *mctx =3D crypto_shash_ctx(desc->tfm); - - return __chksumc_finup(mctx->key, data, length, out); -} - -static int chksum_cra_init(struct crypto_tfm *tfm) -{ - struct chksum_ctx *mctx =3D crypto_tfm_ctx(tfm); - - mctx->key =3D ~0; - return 0; -} - -static struct shash_alg crc32_alg =3D { - .digestsize =3D CHKSUM_DIGEST_SIZE, - .setkey =3D chksum_setkey, - .init =3D chksum_init, - .update =3D chksum_update, - .final =3D chksum_final, - .finup =3D chksum_finup, - .digest =3D chksum_digest, - .descsize =3D sizeof(struct chksum_desc_ctx), - .base =3D { - .cra_name =3D "crc32", - .cra_driver_name =3D "crc32-mips-hw", - .cra_priority =3D 300, - .cra_flags =3D CRYPTO_ALG_OPTIONAL_KEY, - .cra_blocksize =3D CHKSUM_BLOCK_SIZE, - .cra_ctxsize =3D sizeof(struct chksum_ctx), - .cra_module =3D THIS_MODULE, - .cra_init =3D chksum_cra_init, - } -}; - -static struct shash_alg crc32c_alg =3D { - .digestsize =3D CHKSUM_DIGEST_SIZE, - .setkey =3D chksum_setkey, - .init =3D chksum_init, - .update =3D chksumc_update, - .final =3D chksumc_final, - .finup =3D chksumc_finup, - .digest =3D chksumc_digest, - .descsize =3D sizeof(struct chksum_desc_ctx), - .base =3D { - .cra_name =3D "crc32c", - .cra_driver_name =3D "crc32c-mips-hw", - .cra_priority =3D 300, - .cra_flags =3D CRYPTO_ALG_OPTIONAL_KEY, - .cra_blocksize =3D CHKSUM_BLOCK_SIZE, - .cra_ctxsize =3D sizeof(struct chksum_ctx), - .cra_module =3D THIS_MODULE, - .cra_init =3D chksum_cra_init, - } -}; - -static int __init crc32_mod_init(void) -{ - int err; - - err =3D crypto_register_shash(&crc32_alg); - - if (err) - return err; - - err =3D crypto_register_shash(&crc32c_alg); - - if (err) { - crypto_unregister_shash(&crc32_alg); - return err; - } - - return 0; -} - -static void __exit crc32_mod_exit(void) -{ - crypto_unregister_shash(&crc32_alg); - crypto_unregister_shash(&crc32c_alg); -} - -MODULE_AUTHOR("Marcin Nowakowski + * Copyright (C) 2018 MIPS Tech, LLC + */ + +#include +#include +#include +#include +#include +#include +#include + +enum crc_op_size { + b, h, w, d, +}; + +enum crc_type { + crc32, + crc32c, +}; + +#ifndef TOOLCHAIN_SUPPORTS_CRC +#define _ASM_SET_CRC(OP, SZ, TYPE) \ +_ASM_MACRO_3R(OP, rt, rs, rt2, \ + ".ifnc \\rt, \\rt2\n\t" \ + ".error \"invalid operands \\\"" #OP " \\rt,\\rs,\\rt2\\\"\"\n\t" \ + ".endif\n\t" \ + _ASM_INSN_IF_MIPS(0x7c00000f | (__rt << 16) | (__rs << 21) | \ + ((SZ) << 6) | ((TYPE) << 8)) \ + _ASM_INSN32_IF_MM(0x00000030 | (__rs << 16) | (__rt << 21) | \ + ((SZ) << 14) | ((TYPE) << 3))) +#define _ASM_UNSET_CRC(op, SZ, TYPE) ".purgem " #op "\n\t" +#else /* !TOOLCHAIN_SUPPORTS_CRC */ +#define _ASM_SET_CRC(op, SZ, TYPE) ".set\tcrc\n\t" +#define _ASM_UNSET_CRC(op, SZ, TYPE) +#endif + +#define __CRC32(crc, value, op, SZ, TYPE) \ +do { \ + __asm__ __volatile__( \ + ".set push\n\t" \ + _ASM_SET_CRC(op, SZ, TYPE) \ + #op " %0, %1, %0\n\t" \ + _ASM_UNSET_CRC(op, SZ, TYPE) \ + ".set pop" \ + : "+r" (crc) \ + : "r" (value)); \ +} while (0) + +#define _CRC32_crc32b(crc, value) __CRC32(crc, value, crc32b, 0, 0) +#define _CRC32_crc32h(crc, value) __CRC32(crc, value, crc32h, 1, 0) +#define _CRC32_crc32w(crc, value) __CRC32(crc, value, crc32w, 2, 0) +#define _CRC32_crc32d(crc, value) __CRC32(crc, value, crc32d, 3, 0) +#define _CRC32_crc32cb(crc, value) __CRC32(crc, value, crc32cb, 0, 1) +#define _CRC32_crc32ch(crc, value) __CRC32(crc, value, crc32ch, 1, 1) +#define _CRC32_crc32cw(crc, value) __CRC32(crc, value, crc32cw, 2, 1) +#define _CRC32_crc32cd(crc, value) __CRC32(crc, value, crc32cd, 3, 1) + +#define _CRC32(crc, value, size, op) \ + _CRC32_##op##size(crc, value) + +#define CRC32(crc, value, size) \ + _CRC32(crc, value, size, crc32) + +#define CRC32C(crc, value, size) \ + _CRC32(crc, value, size, crc32c) + +static DEFINE_STATIC_KEY_FALSE(have_crc32); + +u32 crc32_le_arch(u32 crc, const u8 *p, size_t len) +{ + if (!static_branch_likely(&have_crc32)) + return crc32_le_base(crc, p, len); + + if (IS_ENABLED(CONFIG_64BIT)) { + for (; len >=3D sizeof(u64); p +=3D sizeof(u64), len -=3D sizeof(u64)) { + u64 value =3D get_unaligned_le64(p); + + CRC32(crc, value, d); + } + + if (len & sizeof(u32)) { + u32 value =3D get_unaligned_le32(p); + + CRC32(crc, value, w); + p +=3D sizeof(u32); + } + } else { + for (; len >=3D sizeof(u32); len -=3D sizeof(u32)) { + u32 value =3D get_unaligned_le32(p); + + CRC32(crc, value, w); + p +=3D sizeof(u32); + } + } + + if (len & sizeof(u16)) { + u16 value =3D get_unaligned_le16(p); + + CRC32(crc, value, h); + p +=3D sizeof(u16); + } + + if (len & sizeof(u8)) { + u8 value =3D *p++; + + CRC32(crc, value, b); + } + + return crc; +} +EXPORT_SYMBOL(crc32_le_arch); + +u32 crc32c_le_arch(u32 crc, const u8 *p, size_t len) +{ + if (!static_branch_likely(&have_crc32)) + return crc32c_le_base(crc, p, len); + + if (IS_ENABLED(CONFIG_64BIT)) { + for (; len >=3D sizeof(u64); p +=3D sizeof(u64), len -=3D sizeof(u64)) { + u64 value =3D get_unaligned_le64(p); + + CRC32C(crc, value, d); + } + + if (len & sizeof(u32)) { + u32 value =3D get_unaligned_le32(p); + + CRC32C(crc, value, w); + p +=3D sizeof(u32); + } + } else { + for (; len >=3D sizeof(u32); len -=3D sizeof(u32)) { + u32 value =3D get_unaligned_le32(p); + + CRC32C(crc, value, w); + p +=3D sizeof(u32); + } + } + + if (len & sizeof(u16)) { + u16 value =3D get_unaligned_le16(p); + + CRC32C(crc, value, h); + p +=3D sizeof(u16); + } + + if (len & sizeof(u8)) { + u8 value =3D *p++; + + CRC32C(crc, value, b); + } + return crc; +} +EXPORT_SYMBOL(crc32c_le_arch); + +u32 crc32_be_arch(u32 crc, const u8 *p, size_t len) +{ + return crc32_be_base(crc, p, len); +} +EXPORT_SYMBOL(crc32_be_arch); + +static int __init crc32_mips_init(void) +{ + if (cpu_have_feature(cpu_feature(MIPS_CRC32))) + static_branch_enable(&have_crc32); + return 0; +} +arch_initcall(crc32_mips_init); + +static void __exit crc32_mips_exit(void) +{ +} +module_exit(crc32_mips_exit); + +MODULE_AUTHOR("Marcin Nowakowski