From nobody Tue Nov 26 06:30:34 2024 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB2EA1F8EEC for ; Mon, 21 Oct 2024 12:41:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729514509; cv=none; b=sGirfZ4bCqUMr4/4rxQ8cljZvnlm+FLyb/OJ/iTP463jKKXLEGXWe0CXJccGRTfAqpe2UIOO48Z3AH/9etYR0AECxlFLojniaNoyAQYqYqH8psZdrw48wY3S2Ct0y8vU1T61FMZviudIkgFmEfRteSH/toXaKHnJzlvMc4zHFtM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729514509; c=relaxed/simple; bh=+o6bp04I5BqDmfOEHCO23uasXPx/7oacpZXUGndUfMw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u/V4H7WRCqTRcev2wQNgC9AtedN8fXQUrniRZgTC2OSDrU9UQ8wI2uLTMkczLiLMSj0dmSnd4lCPA0hZZ5C6QfaSfSYJfmyXVNYu9V8rdGnQKZJ1SQD0dh1spNvAEYzPgMh3s7729lBygL9v74D9E4l//YcakKXVCUdVID7wW/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=pjt9Frky; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="pjt9Frky" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4315baa51d8so43385065e9.0 for ; Mon, 21 Oct 2024 05:41:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1729514504; x=1730119304; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=f1HCPyfTHFOzi0OW+XwcggtuS5NSbaaZ9sz79P9HfH4=; b=pjt9FrkyzrSc1IF8G+lssT1zDICYzmsSR7tAaGKbysVGTLztvTX+kbpdabIGDoiUwD d56hRQmjOcFritE3BZKywxp3OJnxCdZAEO8VqiFr2cPfVBxwxjjj/BLkpibnLmtUErED FuM23yzNeXFnYZj3+aaSLZxX8tTvPRwqMp8fCmaKsGXZ2xQ5dKz+N2FyMc2aBYhLsjyv isEOyFFtOx4gnDDkGGeSqJZaiH3StjIz++io6cPxZ5WJ9ESZ7egOcL1oaLxtBkVSq7wy g20Hpvygt6IaD/3WIjFiabm85fIkkRpjhRESBOAz03J3ZXVYdh67A0c8DQm5pQRVFhGh kDUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729514504; x=1730119304; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f1HCPyfTHFOzi0OW+XwcggtuS5NSbaaZ9sz79P9HfH4=; b=Y4WcOZA+qBfmhb6x3qe8t+Pr+m7eHYvA6JTvebuB0Sv8q2418kTZxng2uKx5shIBh3 uYViWGm3JJJCeE1AsujQG7Hix2jNl4xz2YO6vewOeU6PWe7yZDRcRPBD+mOEm6TgnsiC ol+C8XKxILmV+LOtfwYK7qMt1t2l9wFqcVGHNwtXwolyxHgZ8tzdshr5/t0fWlK2qkdf wOdd9Hfa5jOJxcE8H6B6q+JvppDcYJpnV6x8dlys3ZYyZcS0OsblumA2FD/ceKtAbf7b 4ta0GsuHWDSiQMUzLA6uunAtpMh5iaiuxuwpjx13KZkeACPAGWn+S0ebXPH4jjLreVnm ffoA== X-Forwarded-Encrypted: i=1; AJvYcCUVQxKyMOVURYrTui0vntCGuC4ZW4Mh9IuBVu2ut01dJaa9OU5hTBj5WKgHWXZ5jr93uXJB4LNvy/FcdKQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwYJ0hWjcv72VdInJTPJqSD2tWzHVCeDSJtGkFuwmuq1jtVbbO3 Sf/D/Kkls9XqZvsRlcoKsjHCBrGh4dlFRYEn0VgCeDnuyf3fiF2tQkyZMysFzYY= X-Google-Smtp-Source: AGHT+IFkafWkZorc93ACmLp5j36aBlEaI2nzv6Hk69DkR2sl2P9KsOR3cVd8iGopG0YDkBWwd4fT3g== X-Received: by 2002:a05:600c:198c:b0:431:58bc:ad5e with SMTP id 5b1f17b1804b1-4316168e56dmr91800685e9.28.1729514503715; Mon, 21 Oct 2024 05:41:43 -0700 (PDT) Received: from [127.0.1.1] (host-82-61-199-210.retail.telecomitalia.it. [82.61.199.210]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4316f5cc88esm55996075e9.46.2024.10.21.05.41.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 05:41:43 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Mon, 21 Oct 2024 14:40:17 +0200 Subject: [PATCH v7 7/8] iio: dac: ad3552r: add high-speed platform driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-wip-bl-ad3552r-axi-v0-iio-testing-v7-7-969694f53c5d@baylibre.com> References: <20241021-wip-bl-ad3552r-axi-v0-iio-testing-v7-0-969694f53c5d@baylibre.com> In-Reply-To: <20241021-wip-bl-ad3552r-axi-v0-iio-testing-v7-0-969694f53c5d@baylibre.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dlechner@baylibre.com, Mark Brown , Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Add High Speed ad3552r platform driver. The ad3552r DAC is controlled by a custom (fpga-based) DAC IP through the current AXI backend, or similar alternative IIO backend. Compared to the existing driver (ad3552r.c), that is a simple SPI driver, this driver is coupled with a DAC IIO backend that finally controls the ad3552r by a fpga-based "QSPI+DDR" interface, to reach maximum transfer rate of 33MUPS using dma stream capabilities. All commands involving QSPI bus read/write are delegated to the backend through the provided APIs for bus read/write. Signed-off-by: Angelo Dureghello --- drivers/iio/dac/Kconfig | 14 ++ drivers/iio/dac/Makefile | 1 + drivers/iio/dac/ad3552r-hs.c | 547 +++++++++++++++++++++++++++++++++++++++= ++++ drivers/iio/dac/ad3552r-hs.h | 18 ++ drivers/iio/dac/ad3552r.h | 4 + 5 files changed, 584 insertions(+) diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index fa091995d002..fc11698e88f2 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -6,6 +6,20 @@ =20 menu "Digital to analog converters" =20 +config AD3552R_HS + tristate "Analog Devices AD3552R DAC High Speed driver" + select ADI_AXI_DAC + help + Say yes here to build support for Analog Devices AD3552R + Digital to Analog Converter High Speed driver. + + The driver requires the assistance of an IP core to operate, + since data is streamed into target device via DMA, sent over a + QSPI + DDR (Double Data Rate) bus. + + To compile this driver as a module, choose M here: the + module will be called ad3552r-hs. + config AD3552R tristate "Analog Devices AD3552R DAC driver" depends on SPI_MASTER diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index c92de0366238..d92e08ca93ca 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -4,6 +4,7 @@ # =20 # When adding new entries keep the list in alphabetical order +obj-$(CONFIG_AD3552R_HS) +=3D ad3552r-hs.o ad3552r-common.o obj-$(CONFIG_AD3552R) +=3D ad3552r.o ad3552r-common.o obj-$(CONFIG_AD5360) +=3D ad5360.o obj-$(CONFIG_AD5380) +=3D ad5380.o diff --git a/drivers/iio/dac/ad3552r-hs.c b/drivers/iio/dac/ad3552r-hs.c new file mode 100644 index 000000000000..27bdc35fdc29 --- /dev/null +++ b/drivers/iio/dac/ad3552r-hs.c @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices AD3552R + * Digital to Analog converter driver, High Speed version + * + * Copyright 2024 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ad3552r.h" +#include "ad3552r-hs.h" + +struct ad3552r_hs_state { + const struct ad3552r_model_data *model_data; + struct gpio_desc *reset_gpio; + struct device *dev; + struct iio_backend *back; + bool single_channel; + struct ad3552r_ch_data ch_data[AD3552R_MAX_CH]; + struct ad3552r_hs_platform_data *data; +}; + +static int ad3552r_qspi_update_reg_bits(struct ad3552r_hs_state *st, + u32 reg, u32 mask, u32 val, + size_t xfer_size) +{ + u32 rval; + int ret; + + ret =3D st->data->bus_reg_read(st->back, reg, &rval, xfer_size); + if (ret) + return ret; + + rval =3D (rval & ~mask) | val; + + return st->data->bus_reg_write(st->back, reg, rval, xfer_size); +} + +static int ad3552r_hs_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct ad3552r_hs_state *st =3D iio_priv(indio_dev); + int ret; + int ch =3D chan->channel; + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: { + int sclk; + + ret =3D iio_backend_read_raw(st->back, chan, &sclk, 0, + IIO_CHAN_INFO_FREQUENCY); + if (ret !=3D IIO_VAL_INT) + return -EINVAL; + + /* + * Using 4 lanes (QSPI), then using 2 as DDR mode is + * considered always on (considering buffering mode always). + */ + *val =3D DIV_ROUND_CLOSEST(sclk * 4 * 2, + chan->scan_type.realbits); + + return IIO_VAL_INT; + } + case IIO_CHAN_INFO_RAW: + ret =3D st->data->bus_reg_read(st->back, + AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), + val, 2); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + *val =3D st->ch_data[ch].scale_int; + *val2 =3D st->ch_data[ch].scale_dec; + return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_OFFSET: + *val =3D st->ch_data[ch].offset_int; + *val2 =3D st->ch_data[ch].offset_dec; + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static int ad3552r_hs_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct ad3552r_hs_state *st =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { + return st->data->bus_reg_write(st->back, + AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), + val, 2); + } + unreachable(); + default: + return -EINVAL; + } +} + +static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad3552r_hs_state *st =3D iio_priv(indio_dev); + struct iio_backend_data_fmt fmt =3D { + .type =3D IIO_BACKEND_DATA_UNSIGNED + }; + int loop_len, val, ret; + + switch (*indio_dev->active_scan_mask) { + case AD3552R_CH0_ACTIVE: + st->single_channel =3D true; + loop_len =3D 2; + val =3D AD3552R_REG_ADDR_CH_DAC_16B(0); + break; + case AD3552R_CH1_ACTIVE: + st->single_channel =3D true; + loop_len =3D 2; + val =3D AD3552R_REG_ADDR_CH_DAC_16B(1); + break; + case AD3552R_CH0_ACTIVE | AD3552R_CH1_ACTIVE: + st->single_channel =3D false; + loop_len =3D 4; + val =3D AD3552R_REG_ADDR_CH_DAC_16B(1); + break; + default: + return -EINVAL; + } + + ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_STREAM_MODE, + loop_len, 1); + if (ret) + return ret; + + /* Inform DAC chip to switch into DDR mode */ + ret =3D ad3552r_qspi_update_reg_bits(st, + AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + AD3552R_MASK_SPI_CONFIG_DDR, + AD3552R_MASK_SPI_CONFIG_DDR, 1); + if (ret) + return ret; + + /* Inform DAC IP to go for DDR mode from now on */ + ret =3D iio_backend_ddr_enable(st->back); + if (ret) { + dev_err(st->dev, "could not set DDR mode, not streaming"); + goto exit_err; + } + + ret =3D iio_backend_data_transfer_addr(st->back, val); + if (ret) + goto exit_err; + + ret =3D iio_backend_data_format_set(st->back, 0, &fmt); + if (ret) + goto exit_err; + + ret =3D iio_backend_data_stream_enable(st->back); + if (ret) + goto exit_err; + + return 0; + +exit_err: + ad3552r_qspi_update_reg_bits(st, + AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + AD3552R_MASK_SPI_CONFIG_DDR, + 0, 1); + + iio_backend_ddr_disable(st->back); + + return ret; +} + +static int ad3552r_hs_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad3552r_hs_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D iio_backend_data_stream_disable(st->back); + if (ret) + return ret; + + /* Inform DAC to set in SDR mode */ + ret =3D ad3552r_qspi_update_reg_bits(st, + AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + AD3552R_MASK_SPI_CONFIG_DDR, + 0, 1); + if (ret) + return ret; + + ret =3D iio_backend_ddr_disable(st->back); + if (ret) + return ret; + + return 0; +} + +static inline int ad3552r_hs_set_output_range(struct ad3552r_hs_state *st, + int ch, unsigned int mode) +{ + int val; + + if (ch =3D=3D 0) + val =3D FIELD_PREP(AD3552R_MASK_CH0_RANGE, mode); + else + val =3D FIELD_PREP(AD3552R_MASK_CH1_RANGE, mode); + + return ad3552r_qspi_update_reg_bits(st, + AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, + AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch), + val, 1); +} + +static int ad3552r_hs_reset(struct ad3552r_hs_state *st) +{ + int ret; + + /* + * Using inverted "active-high" logic here, since ad3552r classic-spi + * fdt node (and driver) is using the same logic. + */ + + st->reset_gpio =3D devm_gpiod_get_optional(st->dev, + "reset", GPIOD_OUT_LOW); + if (IS_ERR(st->reset_gpio)) + return PTR_ERR(st->reset_gpio); + + if (st->reset_gpio) { + fsleep(10); + gpiod_set_value_cansleep(st->reset_gpio, 1); + } else { + ret =3D ad3552r_qspi_update_reg_bits(st, + AD3552R_REG_ADDR_INTERFACE_CONFIG_A, + AD3552R_MASK_SOFTWARE_RESET, + AD3552R_MASK_SOFTWARE_RESET, 1); + if (ret) + return ret; + } + msleep(100); + + return 0; +} + +static int ad3552r_hs_scratch_pad_test(struct ad3552r_hs_state *st) +{ + int ret, val; + + ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, + AD3552R_SCRATCH_PAD_TEST_VAL1, 1); + if (ret) + return ret; + + ret =3D st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, + &val, 1); + if (ret) + return ret; + + if (val !=3D AD3552R_SCRATCH_PAD_TEST_VAL1) + return dev_err_probe(st->dev, -EIO, + "SCRATCH_PAD_TEST mismatch. Expected 0x%x, Read 0x%x\n", + AD3552R_SCRATCH_PAD_TEST_VAL1, val); + + ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, + AD3552R_SCRATCH_PAD_TEST_VAL2, 1); + if (ret) + return ret; + + ret =3D st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, + &val, 1); + if (ret) + return ret; + + if (val !=3D AD3552R_SCRATCH_PAD_TEST_VAL2) + return dev_err_probe(st->dev, -EIO, + "SCRATCH_PAD_TEST mismatch. Expected 0x%x, Read 0x%x\n", + AD3552R_SCRATCH_PAD_TEST_VAL2, val); + + return 0; +} + +static int ad3552r_hs_setup_custom_gain(struct ad3552r_hs_state *st, + int ch, u16 gain, u16 offset) +{ + int ret; + + ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch), + offset, 1); + if (ret) + return dev_err_probe(st->dev, ret, "Error writing register\n"); + + ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch), + gain, 1); + if (ret) + return dev_err_probe(st->dev, ret, "Error writing register\n"); + + return 0; +} + +static int ad3552r_hs_setup(struct ad3552r_hs_state *st) +{ + s16 goffs; + u16 id; + u16 gain =3D 0, offset =3D 0; + u32 ch, val, range; + int ret; + + ret =3D ad3552r_hs_reset(st); + if (ret) + return ret; + + ret =3D iio_backend_ddr_disable(st->back); + if (ret) + return ret; + + ret =3D ad3552r_hs_scratch_pad_test(st); + if (ret) + return ret; + + ret =3D st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_PRODUCT_ID_L, + &val, 1); + if (ret) + return ret; + + id =3D val; + + ret =3D st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_PRODUCT_ID_H, + &val, 1); + if (ret) + return ret; + + id |=3D val << 8; + if (id !=3D st->model_data->chip_id) + dev_info(st->dev, "Chip ID error. Expected 0x%x, Read 0x%x\n", + AD3552R_ID, id); + + ret =3D st->data->bus_reg_write(st->back, + AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, + 0, 1); + if (ret) + return ret; + + ret =3D st->data->bus_reg_write(st->back, + AD3552R_REG_ADDR_TRANSFER_REGISTER, + FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE, + AD3552R_QUAD_SPI) | + AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); + if (ret) + return ret; + + ret =3D iio_backend_data_source_set(st->back, 0, IIO_BACKEND_EXTERNAL); + if (ret) + return ret; + + ret =3D iio_backend_data_source_set(st->back, 1, IIO_BACKEND_EXTERNAL); + if (ret) + return ret; + + ret =3D ad3552r_get_ref_voltage(st->dev, &val); + if (ret < 0) + return ret; + + val =3D ret; + + ret =3D ad3552r_qspi_update_reg_bits(st, + AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, + AD3552R_MASK_REFERENCE_VOLTAGE_SEL, + val, 1); + if (ret) + return ret; + + ret =3D ad3552r_get_drive_strength(st->dev, &val); + if (!ret) { + ret =3D ad3552r_qspi_update_reg_bits(st, + AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + AD3552R_MASK_SDO_DRIVE_STRENGTH, + val, 1); + if (ret) + return ret; + } + + device_for_each_child_node_scoped(st->dev, child) { + ret =3D fwnode_property_read_u32(child, "reg", &ch); + if (ret) + return dev_err_probe(st->dev, ret, + "reg property missing\n"); + + ret =3D ad3552r_get_output_range(st->dev, st->model_data, child, + &range); + if (!ret) { + st->ch_data[ch].range =3D range; + + ret =3D ad3552r_hs_set_output_range(st, ch, range); + if (ret) + return ret; + + } else if (ret =3D=3D -ENOENT) { + ret =3D ad3552r_get_custom_gain(st->dev, child, + &st->ch_data[ch].p, + &st->ch_data[ch].n, + &st->ch_data[ch].rfb, + &st->ch_data[ch].gain_offset); + if (ret) + return ret; + + gain =3D ad3552r_calc_custom_gain(st->ch_data[ch].p, + st->ch_data[ch].n, + st->ch_data[ch].gain_offset); + offset =3D abs(goffs); + + st->ch_data[ch].range_override =3D 1; + + ret =3D ad3552r_hs_setup_custom_gain(st, ch, gain, + offset); + if (ret) + return ret; + } else { + return ret; + } + + ad3552r_calc_gain_and_offset(&st->ch_data[ch], st->model_data); + } + + return 0; +} + +static const struct iio_buffer_setup_ops ad3552r_hs_buffer_setup_ops =3D { + .postenable =3D ad3552r_hs_buffer_postenable, + .predisable =3D ad3552r_hs_buffer_predisable, +}; + +#define AD3552R_CHANNEL(ch) { \ + .type =3D IIO_VOLTAGE, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + .output =3D 1, \ + .indexed =3D 1, \ + .channel =3D (ch), \ + .scan_index =3D (ch), \ + .scan_type =3D { \ + .sign =3D 'u', \ + .realbits =3D 16, \ + .storagebits =3D 16, \ + .endianness =3D IIO_BE, \ + } \ +} + +static const struct iio_chan_spec ad3552r_hs_channels[] =3D { + AD3552R_CHANNEL(0), + AD3552R_CHANNEL(1), +}; + +static const struct iio_info ad3552r_hs_info =3D { + .read_raw =3D &ad3552r_hs_read_raw, + .write_raw =3D &ad3552r_hs_write_raw, +}; + +static int ad3552r_hs_probe(struct platform_device *pdev) +{ + struct ad3552r_hs_state *st; + struct iio_dev *indio_dev; + int ret; + + indio_dev =3D devm_iio_device_alloc(&pdev->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->dev =3D &pdev->dev; + + st->data =3D pdev->dev.platform_data; + if (!st->data) + return dev_err_probe(st->dev, -ENODEV, "No platform data !"); + + st->back =3D devm_iio_backend_get(&pdev->dev, NULL); + if (IS_ERR(st->back)) + return PTR_ERR(st->back); + + ret =3D devm_iio_backend_enable(&pdev->dev, st->back); + if (ret) + return ret; + + st->model_data =3D device_get_match_data(&pdev->dev); + if (!st->model_data) + return -ENODEV; + + indio_dev->name =3D "ad3552r"; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->setup_ops =3D &ad3552r_hs_buffer_setup_ops; + indio_dev->channels =3D ad3552r_hs_channels; + indio_dev->num_channels =3D ARRAY_SIZE(ad3552r_hs_channels); + indio_dev->info =3D &ad3552r_hs_info; + + ret =3D devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev); + if (ret) + return ret; + + ret =3D ad3552r_hs_setup(st); + if (ret) + return ret; + + return devm_iio_device_register(&pdev->dev, indio_dev); +} + +static const struct ad3552r_model_data ad3552r_model_data =3D { + .model_name =3D "ad3552r", + .chip_id =3D AD3552R_ID, + .num_hw_channels =3D 2, + .ranges_table =3D ad3552r_ch_ranges, + .num_ranges =3D ARRAY_SIZE(ad3552r_ch_ranges), +}; + +static const struct of_device_id ad3552r_hs_of_id[] =3D { + { .compatible =3D "adi,ad3552r", .data =3D &ad3552r_model_data }, + { } +}; +MODULE_DEVICE_TABLE(of, ad3552r_hs_of_id); + +static struct platform_driver ad3552r_hs_driver =3D { + .driver =3D { + .name =3D "ad3552r-hs", + .of_match_table =3D ad3552r_hs_of_id, + }, + .probe =3D ad3552r_hs_probe, +}; +module_platform_driver(ad3552r_hs_driver); + +MODULE_AUTHOR("Dragos Bogdan "); +MODULE_AUTHOR("Angelo Dureghello "); +MODULE_DESCRIPTION("AD3552R Driver - High Speed version"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(IIO_BACKEND); +MODULE_IMPORT_NS(IIO_AD3552R); diff --git a/drivers/iio/dac/ad3552r-hs.h b/drivers/iio/dac/ad3552r-hs.h new file mode 100644 index 000000000000..dbf71d5e58c1 --- /dev/null +++ b/drivers/iio/dac/ad3552r-hs.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2024 Analog Devices Inc. + * Copyright (c) 2024 Baylibre, SAS + */ +#ifndef __LINUX_PLATFORM_DATA_AD3552R_HS_H__ +#define __LINUX_PLATFORM_DATA_AD3552R_HS_H__ + +struct iio_backend; + +struct ad3552r_hs_platform_data { + int (*bus_reg_read)(struct iio_backend *back, u32 reg, u32 *val, + size_t data_size); + int (*bus_reg_write)(struct iio_backend *back, u32 reg, u32 val, + size_t data_size); +}; + +#endif /* __LINUX_PLATFORM_DATA_AD3552R_HS_H__ */ diff --git a/drivers/iio/dac/ad3552r.h b/drivers/iio/dac/ad3552r.h index 22bd9ad27c65..6120a08e08a4 100644 --- a/drivers/iio/dac/ad3552r.h +++ b/drivers/iio/dac/ad3552r.h @@ -129,8 +129,12 @@ #define AD3552R_GAIN_SCALE 1000 #define AD3552R_LDAC_PULSE_US 100 =20 +#define AD3552R_CH0_ACTIVE BIT(0) +#define AD3552R_CH1_ACTIVE BIT(1) + #define AD3552R_MAX_RANGES 5 #define AD3542R_MAX_RANGES 6 +#define AD3552R_QUAD_SPI 2 =20 extern const s32 ad3552r_ch_ranges[AD3552R_MAX_RANGES][2]; extern const s32 ad3542r_ch_ranges[AD3542R_MAX_RANGES][2]; --=20 2.45.0.rc1