From nobody Tue Nov 26 04:16:30 2024 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7CF71EABDC; Mon, 21 Oct 2024 14:08:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729519701; cv=none; b=m69oyCo4W5DN2gtnIGuTbSctyV+Kt6y0T1773xGy/hhoVtiiQoqydfjNf7YarWtBJYDeM007sowsWmY3UYiw++R2LqtZ46mYOOSdQpx2vQd3e0qH9kce0LEX7/cer1uS97yQvVc5BsJc1JO3I3Q3HPasPDlQFGIAy1wlTFQqe2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729519701; c=relaxed/simple; bh=VBitCg4mmzcbGyGk6q4vLoLZGA6NGjSGxDJCUaNRvRA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QaeOsYAM0IX515XhTsUECN6NTod4wouy1KYxQLR9UELcZnwRjeD5qe2KizZDOQuaKtszso6zmDbWpmynVVpdMx+++4lPTUFaa75he1Taaty4j5ajjZmj7Z/pGIyRDGD5gLOhYS8zqvm42tnoLRBy0RaBOk+yiDRP9SN7ST7/3Tk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=dyJ9w6Ot; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="dyJ9w6Ot" Received: from [127.0.1.1] (91-157-155-49.elisa-laajakaista.fi [91.157.155.49]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id A51D11775; Mon, 21 Oct 2024 16:06:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1729519591; bh=VBitCg4mmzcbGyGk6q4vLoLZGA6NGjSGxDJCUaNRvRA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dyJ9w6Oty908otkRxZOKWO1PS3cEDZdAKt2iIRMvLHuGuuCX/0JwLMK7d6NWRnI/j qjbgEVn9R6ktyaVu93CSVA1IglJPShVcR/OSXw0dD190svCH3FldrVTZbfN+Xsmj9w wa/8z2popAW6glKGFqdfmy0/dOgsZcijA39X0TZM= From: Tomi Valkeinen Date: Mon, 21 Oct 2024 17:07:45 +0300 Subject: [PATCH 1/7] drm/tidss: Fix issue in irq handling causing irq-flood issue Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-tidss-irq-fix-v1-1-82ddaec94e4a@ideasonboard.com> References: <20241021-tidss-irq-fix-v1-0-82ddaec94e4a@ideasonboard.com> In-Reply-To: <20241021-tidss-irq-fix-v1-0-82ddaec94e4a@ideasonboard.com> To: Devarsh Thakkar , Jyri Sarha Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jonathan Cormier , Tomi Valkeinen , Bin Liu , stable@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3147; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=VBitCg4mmzcbGyGk6q4vLoLZGA6NGjSGxDJCUaNRvRA=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBnFmBMHTozIfIAbjm5ocXIG5ei/8JY10fx5WH+c u6fVWtNOfuJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZxZgTAAKCRD6PaqMvJYe 9YSIEACmQz+oDjXeahJ5zI+JsbI5Ax7kejJ0nkUwa25a2Xm+kcbrjRgR6iJJs93GyuccBI/d9iB 865nFZO4QQNUe8zVxy1AoftrDQMGrephfAXmMhg+dy9QPD+OBj9dHfoZwzX9tOM8ZgxOAH6qYpp czJ1xC/IWbZZcjmm1+/hn9KmLSyEAYntDr1qd5SloR0jcn3dQBz+F3LoQPyR+P2aH2uXBYMWIYc 76ZEN+/PD/bAk49yLxcfAEPk7yqE2bquxoiCjDliokSxEH6gkJgI2Vn6yGx9lNpJazjm0AOzcz1 SYUK2d7GU1HjtGcsylsHT5e3PJ6J7+U7dhjEtq8NuyqqqkLtL729rh5tPGyOP01KFum83ugAXBO 5iW+fXI9RTiILT5nBLpuJWFJyKtR5KU0dbDYIDIO48VLr4LlcwX0LpuJh71yIFeUo+lAZRx+FuE +riqBc9puFiw+U8DzR9lXenUWfaxicMPhVz/VQ1CmlDIds+0J3ypwH4U4hSl+nYCeIM6vkxHMpg UDPb1msyY9VquNeuIG/FAN9ShOdvmApZtU+iUKH4gdcyPOb0b4AWOR/YwKyUVJNQN4Ki1CWrTJ4 dpPTU+C04jDQmr1AiOwSeUlawYGMm1mna8uuJed5FY4kyZc9BfBYf4UZOXGnD/SNc0lTYBYy0x/ FDag+XhxTw7HC/w== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 It has been observed that sometimes DSS will trigger an interrupt and the top level interrupt (DISPC_IRQSTATUS) is not zero, but the VP and VID level interrupt-statuses are zero. As the top level irqstatus is supposed to tell whether we have VP/VID interrupts, the thinking of the driver authors was that this particular case could never happen. Thus the driver only clears the DISPC_IRQSTATUS bits which has corresponding interrupts in VP/VID status. So when this issue happens, the driver will not clear DISPC_IRQSTATUS, and we get an interrupt flood. It is unclear why the issue happens. It could be a race issue in the driver, but no such race has been found. It could also be an issue with the HW. However a similar case can be easily triggered by manually writing to DISPC_IRQSTATUS_RAW. This will forcibly set a bit in the DISPC_IRQSTATUS and trigger an interrupt, and as the driver never clears the bit, we get an interrupt flood. To fix the issue, always clear DISPC_IRQSTATUS. The concern with this solution is that if the top level irqstatus is the one that triggers the interrupt, always clearing DISPC_IRQSTATUS might leave some interrupts unhandled if VP/VID interrupt statuses have bits set. However, testing shows that if any of the irqstatuses is set (i.e. even if DISPC_IRQSTATUS =3D=3D 0, but a VID irqstatus has a bit set), we will get an interrupt. Signed-off-by: Tomi Valkeinen Co-developed-by: Bin Liu Signed-off-by: Bin Liu Co-developed-by: Devarsh Thakkar Signed-off-by: Devarsh Thakkar Co-developed-by: Jonathan Cormier Signed-off-by: Jonathan Cormier Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Displa= y SubSystem") Cc: stable@vger.kernel.org Reviewed-by: Aradhya Bhatia Tested-by: Jonathan Cormier --- drivers/gpu/drm/tidss/tidss_dispc.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 1ad711f8d2a8..f81111067578 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -780,24 +780,20 @@ static void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clea= rmask) { unsigned int i; - u32 top_clear =3D 0; =20 for (i =3D 0; i < dispc->feat->num_vps; ++i) { - if (clearmask & DSS_IRQ_VP_MASK(i)) { + if (clearmask & DSS_IRQ_VP_MASK(i)) dispc_k3_vp_write_irqstatus(dispc, i, clearmask); - top_clear |=3D BIT(i); - } } for (i =3D 0; i < dispc->feat->num_planes; ++i) { - if (clearmask & DSS_IRQ_PLANE_MASK(i)) { + if (clearmask & DSS_IRQ_PLANE_MASK(i)) dispc_k3_vid_write_irqstatus(dispc, i, clearmask); - top_clear |=3D BIT(4 + i); - } } if (dispc->feat->subrev =3D=3D DISPC_K2G) return; =20 - dispc_write(dispc, DISPC_IRQSTATUS, top_clear); + /* always clear the top level irqstatus */ + dispc_write(dispc, DISPC_IRQSTATUS, dispc_read(dispc, DISPC_IRQSTATUS)); =20 /* Flush posted writes */ dispc_read(dispc, DISPC_IRQSTATUS); --=20 2.43.0 From nobody Tue Nov 26 04:16:30 2024 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7709B1F8922 for ; Mon, 21 Oct 2024 14:08:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; 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dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="TBlze24y" Received: from [127.0.1.1] (91-157-155-49.elisa-laajakaista.fi [91.157.155.49]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 7A05C17D6; Mon, 21 Oct 2024 16:06:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1729519592; bh=350svTouqCIMYauO1zF9sxUQfeZoXKejVvPzh3lweDI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TBlze24yHdB+GbFvSJ/ta+JIv/NeZs9S/J2cq5gbrelXj7vStwUGyUcNDzRGM5wyK FS2PWFh/SvR5rmCziL3Ou/RELIkWKSt3DnStTyoickQOkY/QDV68wdPdVQS1XeKrMe rx6LlWp/XAhW/dDr84THGT10qJP2qCNs+Tv/YD4Y= From: Tomi Valkeinen Date: Mon, 21 Oct 2024 17:07:46 +0300 Subject: [PATCH 2/7] drm/tidss: Remove unused OCP error flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 We never use the DSS_IRQ_DEVICE_OCP_ERR flag, and the HW doesn't even have such a bit... So remove it. Signed-off-by: Tomi Valkeinen Reviewed-by: Aradhya Bhatia Reviewed-by: Devarsh Thakkar --- drivers/gpu/drm/tidss/tidss_irq.c | 5 +---- drivers/gpu/drm/tidss/tidss_irq.h | 4 +--- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_irq.c b/drivers/gpu/drm/tidss/tids= s_irq.c index 604334ef526a..91498ff664a2 100644 --- a/drivers/gpu/drm/tidss/tidss_irq.c +++ b/drivers/gpu/drm/tidss/tidss_irq.c @@ -78,9 +78,6 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg) tidss_crtc_error_irq(crtc, irqstatus); } =20 - if (irqstatus & DSS_IRQ_DEVICE_OCP_ERR) - dev_err_ratelimited(tidss->dev, "OCP error\n"); - return IRQ_HANDLED; } =20 @@ -105,7 +102,7 @@ int tidss_irq_install(struct drm_device *ddev, unsigned= int irq) if (ret) return ret; =20 - tidss->irq_mask =3D DSS_IRQ_DEVICE_OCP_ERR; + tidss->irq_mask =3D 0; =20 for (unsigned int i =3D 0; i < tidss->num_crtcs; ++i) { struct tidss_crtc *tcrtc =3D to_tidss_crtc(tidss->crtcs[i]); diff --git a/drivers/gpu/drm/tidss/tidss_irq.h b/drivers/gpu/drm/tidss/tids= s_irq.h index b512614d5863..dd61f645f662 100644 --- a/drivers/gpu/drm/tidss/tidss_irq.h +++ b/drivers/gpu/drm/tidss/tidss_irq.h @@ -19,15 +19,13 @@ * bit use |D |fou|FEOL|FEOL|FEOL|FEOL| UUUU | | * bit number|0 |1-3|4-7 |8-11| 12-19 | 20-23 | 24-31 | * - * device bits: D =3D OCP error + * device bits: D =3D Unused * WB bits: f =3D frame done wb, o =3D wb buffer overflow, * u =3D wb buffer uncomplete * vp bits: F =3D frame done, E =3D vsync even, O =3D vsync odd, L =3D syn= c lost * plane bits: U =3D fifo underflow */ =20 -#define DSS_IRQ_DEVICE_OCP_ERR BIT(0) - #define DSS_IRQ_DEVICE_FRAMEDONEWB BIT(1) #define DSS_IRQ_DEVICE_WBBUFFEROVERFLOW BIT(2) #define DSS_IRQ_DEVICE_WBUNCOMPLETEERROR BIT(3) --=20 2.43.0 From nobody Tue Nov 26 04:16:30 2024 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FFE41F80AF for ; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 We check if the platform is K2G in dispc_k3_clear_irqstatus(), and return early if so. This cannot happen, as the _k3_ functions are never called on K2G in the first place. So remove the check. Signed-off-by: Tomi Valkeinen Reviewed-by: Aradhya Bhatia Reviewed-by: Devarsh Thakkar --- drivers/gpu/drm/tidss/tidss_dispc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index f81111067578..99a1138f3e69 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -789,8 +789,6 @@ void dispc_k3_clear_irqstatus(struct dispc_device *disp= c, dispc_irq_t clearmask) if (clearmask & DSS_IRQ_PLANE_MASK(i)) dispc_k3_vid_write_irqstatus(dispc, i, clearmask); } - if (dispc->feat->subrev =3D=3D DISPC_K2G) - return; =20 /* always clear the top level irqstatus */ dispc_write(dispc, DISPC_IRQSTATUS, dispc_read(dispc, DISPC_IRQSTATUS)); --=20 2.43.0 From nobody Tue Nov 26 04:16:30 2024 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF6CD1F9AAC for ; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Add printing of underflows the same way as we handle sync losts. Signed-off-by: Tomi Valkeinen Reviewed-by: Aradhya Bhatia Reviewed-by: Devarsh Thakkar --- drivers/gpu/drm/tidss/tidss_irq.c | 14 ++++++++++++++ drivers/gpu/drm/tidss/tidss_plane.c | 8 ++++++++ drivers/gpu/drm/tidss/tidss_plane.h | 2 ++ 3 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_irq.c b/drivers/gpu/drm/tidss/tids= s_irq.c index 91498ff664a2..3cc4024ec7ff 100644 --- a/drivers/gpu/drm/tidss/tidss_irq.c +++ b/drivers/gpu/drm/tidss/tidss_irq.c @@ -78,6 +78,14 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg) tidss_crtc_error_irq(crtc, irqstatus); } =20 + for (unsigned int i =3D 0; i < tidss->num_planes; ++i) { + struct drm_plane *plane =3D tidss->planes[i]; + struct tidss_plane *tplane =3D to_tidss_plane(plane); + + if (irqstatus & DSS_IRQ_PLANE_FIFO_UNDERFLOW(tplane->hw_plane_id)) + tidss_plane_error_irq(plane, irqstatus); + } + return IRQ_HANDLED; } =20 @@ -112,6 +120,12 @@ int tidss_irq_install(struct drm_device *ddev, unsigne= d int irq) tidss->irq_mask |=3D DSS_IRQ_VP_FRAME_DONE(tcrtc->hw_videoport); } =20 + for (unsigned int i =3D 0; i < tidss->num_planes; ++i) { + struct tidss_plane *tplane =3D to_tidss_plane(tidss->planes[i]); + + tidss->irq_mask |=3D DSS_IRQ_PLANE_FIFO_UNDERFLOW(tplane->hw_plane_id); + } + return 0; } =20 diff --git a/drivers/gpu/drm/tidss/tidss_plane.c b/drivers/gpu/drm/tidss/ti= dss_plane.c index a5d86822c9e3..116de124bddb 100644 --- a/drivers/gpu/drm/tidss/tidss_plane.c +++ b/drivers/gpu/drm/tidss/tidss_plane.c @@ -18,6 +18,14 @@ #include "tidss_drv.h" #include "tidss_plane.h" =20 +void tidss_plane_error_irq(struct drm_plane *plane, u64 irqstatus) +{ + struct tidss_plane *tplane =3D to_tidss_plane(plane); + + dev_err_ratelimited(plane->dev->dev, "Plane%u underflow (irq %llx)\n", + tplane->hw_plane_id, irqstatus); +} + /* drm_plane_helper_funcs */ =20 static int tidss_plane_atomic_check(struct drm_plane *plane, diff --git a/drivers/gpu/drm/tidss/tidss_plane.h b/drivers/gpu/drm/tidss/ti= dss_plane.h index e933e158b617..aecaf2728406 100644 --- a/drivers/gpu/drm/tidss/tidss_plane.h +++ b/drivers/gpu/drm/tidss/tidss_plane.h @@ -22,4 +22,6 @@ struct tidss_plane *tidss_plane_create(struct tidss_devic= e *tidss, u32 crtc_mask, const u32 *formats, u32 num_formats); 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 From: Devarsh Thakkar The driver does not touch the irqstatus register when it is disabling interrupts. This might cause an interrupt to trigger for an interrupt that was just disabled. To fix the issue, clear the irqstatus registers right after disabling the interrupts. Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Displa= y SubSystem") Cc: stable@vger.kernel.org Reported-by: Jonathan Cormier Closes: https://e2e.ti.com/support/processors-group/processors/f/processors= -forum/1394222/am625-issue-about-tidss-rcu_preempt-self-detected-stall-on-c= pu/5424479#5424479 Signed-off-by: Devarsh Thakkar [Tomi: mostly rewrote the patch] Signed-off-by: Tomi Valkeinen Reviewed-by: Aradhya Bhatia Reviewed-by: Jonathan Cormier Tested-by: Jonathan Cormier --- drivers/gpu/drm/tidss/tidss_dispc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 99a1138f3e69..515f82e8a0a5 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -700,7 +700,7 @@ void dispc_k2g_set_irqenable(struct dispc_device *dispc= , dispc_irq_t mask) { dispc_irq_t old_mask =3D dispc_k2g_read_irqenable(dispc); =20 - /* clear the irqstatus for newly enabled irqs */ + /* clear the irqstatus for irqs that will be enabled */ dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask); =20 dispc_k2g_vp_set_irqenable(dispc, 0, mask); @@ -708,6 +708,9 @@ void dispc_k2g_set_irqenable(struct dispc_device *dispc= , dispc_irq_t mask) =20 dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7)); =20 + /* clear the irqstatus for irqs that were disabled */ + dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & old_mask); + /* flush posted write */ dispc_k2g_read_irqenable(dispc); } @@ -837,7 +840,7 @@ static void dispc_k3_set_irqenable(struct dispc_device = *dispc, =20 old_mask =3D dispc_k3_read_irqenable(dispc); =20 - /* clear the irqstatus for newly enabled irqs */ + /* clear the irqstatus for irqs that will be enabled */ dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask); =20 for (i =3D 0; i < dispc->feat->num_vps; ++i) { @@ -862,6 +865,9 @@ static void dispc_k3_set_irqenable(struct dispc_device = *dispc, if (main_disable) dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable); =20 + /* clear the irqstatus for irqs that were disabled */ + dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & old_mask); 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a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1729519595; bh=ENDFVzRG/cSHhohHXAlrlu8X8vbG5ayt/Jz55IYFLDg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PxDSWj1W2hRRX6/76+mP/nye+oe6R1f6chkMM+fq6dLMYNQTSaK72ISZ7DJLhY9R4 8EgDc1vJVC2+bmbGtD4anOJmLazMkU517fAV+/SHtXKlO+XgaGOmMYiQYJgMjXg+bl WDZFelNbWIhIE5dvbT+6AxXMcGVRY5ONpBdchrmU= From: Tomi Valkeinen Date: Mon, 21 Oct 2024 17:07:50 +0300 Subject: [PATCH 6/7] drm/tidss: Fix race condition while handling interrupt registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-tidss-irq-fix-v1-6-82ddaec94e4a@ideasonboard.com> References: <20241021-tidss-irq-fix-v1-0-82ddaec94e4a@ideasonboard.com> In-Reply-To: <20241021-tidss-irq-fix-v1-0-82ddaec94e4a@ideasonboard.com> To: Devarsh Thakkar , Jyri Sarha Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jonathan Cormier , Tomi Valkeinen , stable@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 From: Devarsh Thakkar The driver has a spinlock for protecting the irq_masks field and irq enable registers. However, the driver misses protecting the irq status registers which can lead to races. Take the spinlock when accessing irqstatus too. Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Displa= y SubSystem") Cc: stable@vger.kernel.org Signed-off-by: Devarsh Thakkar [Tomi: updated the desc] Signed-off-by: Tomi Valkeinen Reviewed-by: Aradhya Bhatia Reviewed-by: Jonathan Cormier Tested-by: Jonathan Cormier --- drivers/gpu/drm/tidss/tidss_dispc.c | 4 ++++ drivers/gpu/drm/tidss/tidss_irq.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 515f82e8a0a5..07f5c26cfa26 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -2767,8 +2767,12 @@ static void dispc_init_errata(struct dispc_device *d= ispc) */ static void dispc_softreset_k2g(struct dispc_device *dispc) { + unsigned long flags; + + spin_lock_irqsave(&dispc->tidss->wait_lock, flags); dispc_set_irqenable(dispc, 0); dispc_read_and_clear_irqstatus(dispc); + spin_unlock_irqrestore(&dispc->tidss->wait_lock, flags); =20 for (unsigned int vp_idx =3D 0; vp_idx < dispc->feat->num_vps; ++vp_idx) VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0); diff --git a/drivers/gpu/drm/tidss/tidss_irq.c b/drivers/gpu/drm/tidss/tids= s_irq.c index 3cc4024ec7ff..8af4682ba56b 100644 --- a/drivers/gpu/drm/tidss/tidss_irq.c +++ b/drivers/gpu/drm/tidss/tidss_irq.c @@ -60,7 +60,9 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg) unsigned int id; dispc_irq_t irqstatus; =20 + spin_lock(&tidss->wait_lock); irqstatus =3D dispc_read_and_clear_irqstatus(tidss->dispc); + spin_unlock(&tidss->wait_lock); =20 for (id =3D 0; id < tidss->num_crtcs; id++) { struct drm_crtc *crtc =3D tidss->crtcs[id]; --=20 2.43.0 From nobody Tue Nov 26 04:16:30 2024 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55F9C1FA27C for ; Mon, 21 Oct 2024 14:08:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 The 'wait_lock' name seems to be a copy-paste from omapdrm, and makes no sense here. Rename it to 'irq_lock'. Also clarify the related comment to make it clear what it protects, and drop any comments related to 'wait_list' which doesn't exist in tidss. Signed-off-by: Tomi Valkeinen Reviewed-by: Aradhya Bhatia Reviewed-by: Devarsh Thakkar --- drivers/gpu/drm/tidss/tidss_dispc.c | 4 ++-- drivers/gpu/drm/tidss/tidss_drv.c | 2 +- drivers/gpu/drm/tidss/tidss_drv.h | 5 +++-- drivers/gpu/drm/tidss/tidss_irq.c | 19 +++++++++---------- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 07f5c26cfa26..cacb5f3d8085 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -2769,10 +2769,10 @@ static void dispc_softreset_k2g(struct dispc_device= *dispc) { unsigned long flags; =20 - spin_lock_irqsave(&dispc->tidss->wait_lock, flags); + spin_lock_irqsave(&dispc->tidss->irq_lock, flags); dispc_set_irqenable(dispc, 0); dispc_read_and_clear_irqstatus(dispc); - spin_unlock_irqrestore(&dispc->tidss->wait_lock, flags); + spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags); =20 for (unsigned int vp_idx =3D 0; vp_idx < dispc->feat->num_vps; ++vp_idx) VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0); diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tids= s_drv.c index d15f836dca95..c7de8c9fa12e 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -138,7 +138,7 @@ static int tidss_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, tidss); =20 - spin_lock_init(&tidss->wait_lock); + spin_lock_init(&tidss->irq_lock); =20 ret =3D dispc_init(tidss); if (ret) { diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tids= s_drv.h index d7f27b0b0315..7f4f4282bc04 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.h +++ b/drivers/gpu/drm/tidss/tidss_drv.h @@ -29,8 +29,9 @@ struct tidss_device { =20 unsigned int irq; =20 - spinlock_t wait_lock; /* protects the irq masks */ - dispc_irq_t irq_mask; /* enabled irqs in addition to wait_list */ + /* protects the irq masks field and irqenable/irqstatus registers */ + spinlock_t irq_lock; + dispc_irq_t irq_mask; /* enabled irqs */ }; =20 #define to_tidss(__dev) container_of(__dev, struct tidss_device, ddev) diff --git a/drivers/gpu/drm/tidss/tidss_irq.c b/drivers/gpu/drm/tidss/tids= s_irq.c index 8af4682ba56b..5abc788781f4 100644 --- a/drivers/gpu/drm/tidss/tidss_irq.c +++ b/drivers/gpu/drm/tidss/tidss_irq.c @@ -15,10 +15,9 @@ #include "tidss_irq.h" #include "tidss_plane.h" =20 -/* call with wait_lock and dispc runtime held */ static void tidss_irq_update(struct tidss_device *tidss) { - assert_spin_locked(&tidss->wait_lock); + assert_spin_locked(&tidss->irq_lock); =20 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); } @@ -31,11 +30,11 @@ void tidss_irq_enable_vblank(struct drm_crtc *crtc) u32 hw_videoport =3D tcrtc->hw_videoport; unsigned long flags; =20 - spin_lock_irqsave(&tidss->wait_lock, flags); + spin_lock_irqsave(&tidss->irq_lock, flags); tidss->irq_mask |=3D DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) | DSS_IRQ_VP_VSYNC_ODD(hw_videoport); tidss_irq_update(tidss); - spin_unlock_irqrestore(&tidss->wait_lock, flags); + spin_unlock_irqrestore(&tidss->irq_lock, flags); } =20 void tidss_irq_disable_vblank(struct drm_crtc *crtc) @@ -46,11 +45,11 @@ void tidss_irq_disable_vblank(struct drm_crtc *crtc) u32 hw_videoport =3D tcrtc->hw_videoport; unsigned long flags; =20 - spin_lock_irqsave(&tidss->wait_lock, flags); + spin_lock_irqsave(&tidss->irq_lock, flags); tidss->irq_mask &=3D ~(DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) | DSS_IRQ_VP_VSYNC_ODD(hw_videoport)); tidss_irq_update(tidss); - spin_unlock_irqrestore(&tidss->wait_lock, flags); + spin_unlock_irqrestore(&tidss->irq_lock, flags); } =20 static irqreturn_t tidss_irq_handler(int irq, void *arg) @@ -60,9 +59,9 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg) unsigned int id; dispc_irq_t irqstatus; =20 - spin_lock(&tidss->wait_lock); + spin_lock(&tidss->irq_lock); irqstatus =3D dispc_read_and_clear_irqstatus(tidss->dispc); - spin_unlock(&tidss->wait_lock); + spin_unlock(&tidss->irq_lock); =20 for (id =3D 0; id < tidss->num_crtcs; id++) { struct drm_crtc *crtc =3D tidss->crtcs[id]; @@ -95,9 +94,9 @@ void tidss_irq_resume(struct tidss_device *tidss) { unsigned long flags; =20 - spin_lock_irqsave(&tidss->wait_lock, flags); + spin_lock_irqsave(&tidss->irq_lock, flags); tidss_irq_update(tidss); - spin_unlock_irqrestore(&tidss->wait_lock, flags); + spin_unlock_irqrestore(&tidss->irq_lock, flags); } =20 int tidss_irq_install(struct drm_device *ddev, unsigned int irq) --=20 2.43.0