From nobody Tue Nov 26 06:24:40 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49E2B8479; Mon, 21 Oct 2024 14:00:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729519217; cv=none; b=B7PTvPvhRRMl87UGAyJOLU+ryqIDOoQxllRF1XRTBryXr1MhbartCAY4GEcSvfXVaecZaA3wDvPq/5tlAmLNlGjbaOZwmJ/OSaNNkVnd/Q3ET1bBsAXlhYl+9rrMqvgRNcC+e7d6Wavn4xAoDmgoh0LqEldRt5EM5B8Avvu9l/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729519217; c=relaxed/simple; bh=pYol46mg6UJQJyh2+og/qVGN4XnTuv+gs2R8oiilP8s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=pqZnP+4nyROlioFlGoELdthqgxL2LSwU7EkErhjbucqxBDSNyxw4s4vIeKqsCnfOFb+FLrDhSrZ0omUM13vEyW2hCsBfRhiBRHruErv9V1QPxKY6zPYb9D3S7OcGOk6/cSughoE8oKYsgapezrWJsSE1NGQwhsROhfF7s1m6Iz0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=qb7UkSuK; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="qb7UkSuK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1729519215; x=1761055215; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=pYol46mg6UJQJyh2+og/qVGN4XnTuv+gs2R8oiilP8s=; b=qb7UkSuKUWrL6vvmgCBU6zK10Kty/VfQEKTFrtIR86qx+fjrv69cxou7 tzyMoeRNIGYP5TETtfHuGimducXX+th92KvkJvhLwjDwc2mJoJ67zxLFL yLpknEBlAQ92ir7Y0Eg+shLDy5VG9MagEL6Gw7/zGo1wiNakjmghSt042 pZdmHNmmBqHh/lDeE1I+zm82aKg5D3O55gDrLdTpVzXSEdXuCb2yUB1nQ yqtZBA0M6FMh2vSozEIBJnu/u2AyqKILgCmEYBrjRTtdCyaIGDooYfn7I Ckl8KA0tB63mtRB9R8tNsXJeFihiq1qw4jHErjhDdEI0UgVgwcdRTEKxj Q==; X-CSE-ConnectionGUID: wjlJ/ymcRaqntxTcHXMHhA== X-CSE-MsgGUID: rM5Y68L1RCeQ54dZq/WYaQ== X-IronPort-AV: E=Sophos;i="6.11,221,1725346800"; d="scan'208";a="33285733" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Oct 2024 07:00:13 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 21 Oct 2024 06:59:51 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 21 Oct 2024 06:59:48 -0700 From: Daniel Machon Date: Mon, 21 Oct 2024 15:58:51 +0200 Subject: [PATCH net-next 14/15] net: sparx5: add compatible strings for lan969x and verify the target Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241021-sparx5-lan969x-switch-driver-2-v1-14-c8c49ef21e0f@microchip.com> References: <20241021-sparx5-lan969x-switch-driver-2-v1-0-c8c49ef21e0f@microchip.com> In-Reply-To: <20241021-sparx5-lan969x-switch-driver-2-v1-0-c8c49ef21e0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Add compatible strings for the twelve lan969x SKU's (Stock Keeping Unit) that we support, and verify that the devicetree target is supported by the chip target. Each SKU supports different bandwidths and features (see [1] for details). We want to be able to run a SKU with a lower bandwidth and/or feature set, than what is supported by the actual chip. In order to accomplish this we: - add new field sparx5->target_dt that reflects the target from the devicetree (compatible string). - compare the devicetree target with the actual chip target. If the bandwidth and features provided by the devicetree target is supported by the chip, we approve - otherwise reject. - set the core clock and features based on the devicetree target [1] https://www.microchip.com/en-us/product/lan9698 Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/Makefile | 1 + .../net/ethernet/microchip/sparx5/sparx5_main.c | 194 +++++++++++++++++= +++- .../net/ethernet/microchip/sparx5/sparx5_main.h | 1 + 3 files changed, 193 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/Makefile b/drivers/net/e= thernet/microchip/sparx5/Makefile index 3435ca86dd70..8fe302415563 100644 --- a/drivers/net/ethernet/microchip/sparx5/Makefile +++ b/drivers/net/ethernet/microchip/sparx5/Makefile @@ -19,3 +19,4 @@ sparx5-switch-$(CONFIG_DEBUG_FS) +=3D sparx5_vcap_debugfs= .o # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/vcap ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/fdma +ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/lan969x diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.c index 5c986c373b3e..edbe639d98c5 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -24,6 +24,8 @@ #include #include =20 +#include "lan969x.h" /* lan969x_desc */ + #include "sparx5_main_regs.h" #include "sparx5_main.h" #include "sparx5_port.h" @@ -227,6 +229,168 @@ bool is_sparx5(struct sparx5 *sparx5) } } =20 +/* Set the devicetree target based on the compatible string */ +static int sparx5_set_target_dt(struct sparx5 *sparx5) +{ + struct device_node *node =3D sparx5->pdev->dev.of_node; + + if (is_sparx5(sparx5)) + /* For Sparx5 the devicetree target is always the chip target */ + sparx5->target_dt =3D sparx5->target_ct; + else if (of_device_is_compatible(node, "microchip,lan9691-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9691VAO; + else if (of_device_is_compatible(node, "microchip,lan9692-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9692VAO; + else if (of_device_is_compatible(node, "microchip,lan9693-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9693VAO; + else if (of_device_is_compatible(node, "microchip,lan9694-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9694; + else if (of_device_is_compatible(node, "microchip,lan9695-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9694TSN; + else if (of_device_is_compatible(node, "microchip,lan9696-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9696; + else if (of_device_is_compatible(node, "microchip,lan9697-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9696TSN; + else if (of_device_is_compatible(node, "microchip,lan9698-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9698; + else if (of_device_is_compatible(node, "microchip,lan9699-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9698TSN; + else if (of_device_is_compatible(node, "microchip,lan969a-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9694RED; + else if (of_device_is_compatible(node, "microchip,lan969b-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9696RED; + else if (of_device_is_compatible(node, "microchip,lan969c-switch")) + sparx5->target_dt =3D SPX5_TARGET_CT_LAN9698RED; + else + return -EINVAL; + + return 0; +} + +/* Compare the devicetree target with the chip target. + * Make sure the chip target supports the features and bandwidth requested + * from the devicetree target. + */ +static int sparx5_verify_target(struct sparx5 *sparx5) +{ + switch (sparx5->target_dt) { + case SPX5_TARGET_CT_7546: + case SPX5_TARGET_CT_7549: + case SPX5_TARGET_CT_7552: + case SPX5_TARGET_CT_7556: + case SPX5_TARGET_CT_7558: + case SPX5_TARGET_CT_7546TSN: + case SPX5_TARGET_CT_7549TSN: + case SPX5_TARGET_CT_7552TSN: + case SPX5_TARGET_CT_7556TSN: + case SPX5_TARGET_CT_7558TSN: + return 0; + case SPX5_TARGET_CT_LAN9698RED: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED) + return 0; + break; + + case SPX5_TARGET_CT_LAN9696RED: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED) + return 0; + break; + + case SPX5_TARGET_CT_LAN9694RED: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9694RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED) + return 0; + break; + + case SPX5_TARGET_CT_LAN9698TSN: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED) + return 0; + break; + + case SPX5_TARGET_CT_LAN9696TSN: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED) + return 0; + break; + + case SPX5_TARGET_CT_LAN9694TSN: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9694TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9694RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED) + return 0; + break; + + case SPX5_TARGET_CT_LAN9693VAO: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9693VAO || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698TSN) + return 0; + break; + + case SPX5_TARGET_CT_LAN9692VAO: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9692VAO || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9693VAO || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698TSN) + return 0; + break; + + case SPX5_TARGET_CT_LAN9691VAO: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9691VAO || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9692VAO || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9693VAO || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9694TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9694RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED) + return 0; + break; + + case SPX5_TARGET_CT_LAN9698: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698 || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9693VAO || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698TSN) + return 0; + break; + + case SPX5_TARGET_CT_LAN9696: + if (sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696 || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698 || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9692VAO || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9693VAO || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698RED || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9696TSN || + sparx5->target_ct =3D=3D SPX5_TARGET_CT_LAN9698TSN) + return 0; + break; + + case SPX5_TARGET_CT_LAN9694: + return 0; + + default: + pr_err("Unknown target: %x", sparx5->target_dt); + return -EINVAL; + } + + pr_err("Chip target: %x does not support the target: %x", + sparx5->target_ct, sparx5->target_dt); + + return -EINVAL; +} + static int sparx5_create_targets(struct sparx5 *sparx5) { const struct sparx5_main_io_resource *iomap =3D sparx5->data->iomap; @@ -441,7 +605,7 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5) * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported * freq. is used */ - switch (sparx5->target_ct) { + switch (sparx5->target_dt) { case SPX5_TARGET_CT_7546: if (sparx5->coreclock =3D=3D SPX5_CORE_CLOCK_DEFAULT) freq =3D SPX5_CORE_CLOCK_250MHZ; @@ -491,7 +655,7 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5) break; default: dev_err(sparx5->dev, "Target (%#04x) not supported\n", - sparx5->target_ct); + sparx5->target_dt); return -ENODEV; } =20 @@ -512,7 +676,7 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5) default: dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n", - sparx5->coreclock, sparx5->target_ct); + sparx5->coreclock, sparx5->target_dt); return -EINVAL; } =20 @@ -914,6 +1078,16 @@ static int mchp_sparx5_probe(struct platform_device *= pdev) sparx5->target_ct =3D (enum spx5_target_chiptype) GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); =20 + /* Set the devicetree target based on the compatible string. */ + err =3D sparx5_set_target_dt(sparx5); + if (err) + goto cleanup_config; + + /* Verify that the chip target supports the devicetree target */ + err =3D sparx5_verify_target(sparx5); + if (err) + goto cleanup_config; + /* Initialize Switchcore and internal RAMs */ err =3D sparx5_init_switchcore(sparx5); if (err) { @@ -1051,6 +1225,20 @@ static const struct sparx5_match_data sparx5_desc = =3D { =20 static const struct of_device_id mchp_sparx5_match[] =3D { { .compatible =3D "microchip,sparx5-switch", .data =3D &sparx5_desc }, +#ifdef CONFIG_LAN969X_SWITCH + { .compatible =3D "microchip,lan9691-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan9692-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan9693-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan9694-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan9695-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan9696-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan9697-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan9698-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan9699-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan969a-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan969b-switch", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan969c-switch", .data =3D &lan969x_desc }, +#endif { } }; MODULE_DEVICE_TABLE(of, mchp_sparx5_match); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index 1828e2a7d610..8a2b74d0bd35 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -337,6 +337,7 @@ struct sparx5 { struct device *dev; u32 chip_id; enum spx5_target_chiptype target_ct; + enum spx5_target_chiptype target_dt; /* target from devicetree */ void __iomem *regs[NUM_TARGETS]; int port_count; struct mutex lock; /* MAC reg lock */ --=20 2.34.1