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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2fb9ae1217bsm4522711fa.112.2024.10.21.03.30.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 03:30:56 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 21 Oct 2024 13:30:35 +0300 Subject: [PATCH v2 07/11] clk: qcom: rpmh: add support for SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-sar2130p-clocks-v2-7-383e5eb123a2@linaro.org> References: <20241021-sar2130p-clocks-v2-0-383e5eb123a2@linaro.org> In-Reply-To: <20241021-sar2130p-clocks-v2-0-383e5eb123a2@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1697; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=LnoCXGHzd5t7+0pN06MF228za9Lu0FM1Oe64mRLrAEg=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnFi1MbkWvYiZofhgCqZ4ggNTsip56ovOEn1CSN cuI/felXXiJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxYtTAAKCRAU23LtvoBl uE4SD/9ZtaF7M0grDGlmhdJonGZSBLSd5cuwulIlqIkLAAnV7pCdtXbckraOuGKAO5UDTpCpaKQ /1CkHFWbcIc83zihwDUy7AINVbgoJpznGO1Nqby9SysBfubk6EqXjIG6ayKZTB5nQ3W1nUYtAp7 IFBEsCY9iJFmpabThGjwS678MkCD7Nh4nOBWm2nhue1konA9XxbHYcyNymgciPN1aGI2qSlx4ns eQBkqFJsF987q9lX8mWV4JnFJFMgqNCMbPb9VvNE/jF/kC6MylmK/rKKzNYe7hxYbARqJyU7XQl 4Uk1DUIFh1JWeI01HYQVgT2EuHMbtDxrVe+ytsj4PLv1AjcDQ40zTbHb4HUrOhJIpAyiKgGqVC+ 86o2Fj2jgvwMxrrB7gvlawuzW25NyF5TM3P5pJVrcIot2ZcYD4p2l0/5LlzeSo923pgEp8lNDFI enre8wQzT3/EF1hQVoM/FUdY8zB5/+hcnfvLK98m2Un9NlMr5SOU9fdVO9ZfrCDVoEiWKWmALx+ xSMxO0pgAdtQtbYQDXHPhu0ohNnLnmAOf/rnw8HmhCoaKQgJf0btaYVKhXgd3unCI1vcQRXct7u EDSgF8KeoWRPaG1GyAPvnLYLkcCAja8ImNVpGn330gsV6PBuI4X2NVP64GAcsUV+zZJfJ8Jh2/m RWSi2weD9qSc5Rw== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Define clocks as supported by the RPMh on the SAR2130P platform. It seems that on this platform RPMh models only CXO clock. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpmh.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 4acde937114af3d7fdc15f3d125a72d42d0fde21..8cb15430d0171a8ed6b05e51d19= 01af63a4564c4 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -389,6 +389,16 @@ DEFINE_CLK_RPMH_BCM(ipa, "IP0"); DEFINE_CLK_RPMH_BCM(pka, "PKA0"); DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); =20 +static struct clk_hw *sar2130p_rpmh_clocks[] =3D { + [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div1.hw, + [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div1_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sar2130p =3D { + .clks =3D sar2130p_rpmh_clocks, + .num_clks =3D ARRAY_SIZE(sar2130p_rpmh_clocks), +}; + static struct clk_hw *sdm845_rpmh_clocks[] =3D { [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, @@ -880,6 +890,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) static const struct of_device_id clk_rpmh_match_table[] =3D { { .compatible =3D "qcom,qdu1000-rpmh-clk", .data =3D &clk_rpmh_qdu1000}, { .compatible =3D "qcom,sa8775p-rpmh-clk", .data =3D &clk_rpmh_sa8775p}, + { .compatible =3D "qcom,sar2130p-rpmh-clk", .data =3D &clk_rpmh_sar2130p}, { .compatible =3D "qcom,sc7180-rpmh-clk", .data =3D &clk_rpmh_sc7180}, { .compatible =3D "qcom,sc8180x-rpmh-clk", .data =3D &clk_rpmh_sc8180x}, { .compatible =3D "qcom,sc8280xp-rpmh-clk", .data =3D &clk_rpmh_sc8280xp}, --=20 2.39.5