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On i.MX8Q platforms, the PCI bus addresses differ from the CPU addresses. The DesignWare (DWC) driver already handles this in the common code. Reviewed-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- change from v2 to v3 - add Mani's review tag - Add pci->using_dtbus_info =3D true; --- drivers/pci/controller/dwc/pci-imx6.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index bdc2b372e6c13..5be9bac6206a7 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -70,6 +70,7 @@ enum imx_pcie_variants { IMX8MQ_EP, IMX8MM_EP, IMX8MP_EP, + IMX8Q_EP, IMX95_EP, }; =20 @@ -1079,6 +1080,16 @@ static const struct pci_epc_features imx8m_pcie_epc_= features =3D { .align =3D SZ_64K, }; =20 +static const struct pci_epc_features imx8q_pcie_epc_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D false, + .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, + .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, + .bar[BAR_5] =3D { .type =3D BAR_RESERVED, }, + .align =3D SZ_64K, +}; + /* * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR S= izing Scheme * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -1448,6 +1459,8 @@ static int imx_pcie_probe(struct platform_device *pde= v) if (ret) return ret; =20 + pci->using_dtbus_info =3D true; + if (imx_pcie->drvdata->mode =3D=3D DW_PCIE_EP_TYPE) { ret =3D imx_add_pcie_ep(imx_pcie, pdev); if (ret < 0) @@ -1645,6 +1658,14 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .epc_features =3D &imx8m_pcie_epc_features, .enable_ref_clk =3D imx8mm_pcie_enable_ref_clk, }, + [IMX8Q_EP] =3D { + .variant =3D IMX8Q_EP, + .flags =3D IMX_PCIE_FLAG_HAS_PHYDRV, + .mode =3D DW_PCIE_EP_TYPE, + .epc_features =3D &imx8q_pcie_epc_features, + .clk_names =3D imx8q_clks, + .clks_cnt =3D ARRAY_SIZE(imx8q_clks), + }, [IMX95_EP] =3D { .variant =3D IMX95_EP, .flags =3D IMX_PCIE_FLAG_HAS_SERDES | @@ -1674,6 +1695,7 @@ static const struct of_device_id imx_pcie_of_match[] = =3D { { .compatible =3D "fsl,imx8mq-pcie-ep", .data =3D &drvdata[IMX8MQ_EP], }, { .compatible =3D "fsl,imx8mm-pcie-ep", .data =3D &drvdata[IMX8MM_EP], }, { .compatible =3D "fsl,imx8mp-pcie-ep", .data =3D &drvdata[IMX8MP_EP], }, + { .compatible =3D "fsl,imx8q-pcie-ep", .data =3D &drvdata[IMX8Q_EP], }, { .compatible =3D "fsl,imx95-pcie-ep", .data =3D &drvdata[IMX95_EP], }, {}, }; --=20 2.34.1