From nobody Tue Nov 26 06:40:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2036B197A81; Sun, 20 Oct 2024 22:14:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; cv=none; b=a7RyA+ZQo3f9zbBrIwZw0cxRcmjOOASgXi+WVrQu9NDZfqMqnebklGeM84QUhVs9s1lpgh5RMjPR3Bby+5YbH6BEtZg7zCojNYPEhbAViO1FuuXcIxzwYRVDTbGPpcbmcYbFTwKFF6mGeXzL4HiJTunNJ13H45CJ9FrRE+I9v4Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; c=relaxed/simple; bh=S8FfBXPNjjhlCI/HFOT2nHb83ABvho1ixjaatY2LUpc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Tt8cJ1Pf/S0lBhPZBxIXWwLlrDyUTTlN+ysj21mO40y/M++cNDDzu5RNSebD4FIbfR+c/FpT1hgXS82LXU8cIVUXtogAyfBkuWDtbV4kVgJ3lGsUcx3cEt8pbmWX312IMd1/nl1CdQrDftoR/e6jGfW6wl3Esn5se7l3vzho6d8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TIQFpZyR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TIQFpZyR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9930AC4CECD; Sun, 20 Oct 2024 22:14:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729462451; bh=S8FfBXPNjjhlCI/HFOT2nHb83ABvho1ixjaatY2LUpc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TIQFpZyRPt+QsAbzdlJg+8UlTWm4iXFQeZXbWQslyh42AcsIYh/NAgTbU6z/I8x9f 3UHn7/ybQEOcMj5HUTTY5XWQU0BVC2+0RmvRvVgUAH79z0FU1IxuJO26jgh72oBGhl 7ZQydrFrOZre+nGobqkcVcFfj96ZZovqWwqbveP0nXy6T135OWFkMCpT4VplRPA6Dr ciXIjo2/oyA3jlcpiy0nWrGP9zYjQ2WqA9Xuss6I6WpYPHdom+7F24+8jZ4wFTm4X4 3LU8sR26+5gHz/Z/Rb8lfBHqdsGm2JZkcGPcyic5adHL/uuok7NcKYvp4rwxU2jGqD xE+xxIg6db65w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86B79D3C92D; Sun, 20 Oct 2024 22:14:11 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Mon, 21 Oct 2024 00:13:21 +0200 Subject: [PATCH v2 01/13] media: i2c: imx214: Fix link frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-1-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=1541; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=NluvLjOk7zpWEGYYj4MVNV0Nec5J7Y/DcA8dZZTRiIo=; b=BrgCerZaFunRpJUctNvXFFArnADMv/vNjc/D3ZpQZveBIg/+nfL1ilwXeiid0JffRzm2c8MWS EaPTRw8w1xRAj+9h6jXE0GW+1fhu/BSkI4Ia6q/hZAdIl81GSvWB1sI X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch The driver defines IMX214_DEFAULT_LINK_FREQ 480000000, and then IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10), which works out as 384MPix/s. (The 8 is 4 lanes and DDR.) Parsing the PLL registers with the defined 24MHz input. We're in single PLL mode, so MIPI frequency is directly linked to pixel rate. VTCK ends up being 1200MHz, and VTPXCK and OPPXCK both are 120MHz. Section 5.3 "Frame rate calculation formula" says "Pixel rate [pixels/s] =3D VTPXCK [MHz] * 4", so 120 * 4 =3D 480MPix/s, which basically agrees with my number above. 3.1.4. MIPI global timing setting says "Output bitrate =3D OPPXCK * reg 0x113[7:0]", so 120MHz * 10, or 1200Mbit/s. That would be a link frequency of 600MHz due to DDR. That also matches to 480MPix/s * 10bpp / 4 lanes / 2 for DDR. Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 4962cfe7c83d62425aeccb46a400fa93146f14ea..5d411452d342fdb177619cd1c9f= d9650d31089bb 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -24,7 +24,7 @@ #define IMX214_MODE_STREAMING 0x01 =20 #define IMX214_DEFAULT_CLK_FREQ 24000000 -#define IMX214_DEFAULT_LINK_FREQ 480000000 +#define IMX214_DEFAULT_LINK_FREQ 600000000 #define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10) #define IMX214_FPS 30 #define IMX214_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10 --=20 2.47.0 From nobody Tue Nov 26 06:40:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C68E198A01; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; cv=none; b=bS9UYcW+lMrTEJjoxPiyHGcQzIvhKsZ1x6np1qfP5OM8Sp3e9HwYre0xxSz4KCaOsoF/uWkk1QWAVvM1zgQZD9KtOxjLNGeegVHFAvhXBS4ONbOwzDOvifhqvECm1LEERSVAUaQiXpxvTst2xqerELEj8RYIc0Gy7qgpbRxNLKo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; c=relaxed/simple; bh=xa1sgEURAOgMq87x3qoMHqcD6v/zC7w+re02aI0wGmY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=seRiwvmu6YONLFO7TN1vimzo86Yx0GAQ46S4a+QH+8RyoHQPv6mXcD2CTteaTNS7/6mnHHGsRRURiN8Qz7sl6OVQZ0AdzKgO06c3vvK0iNUx8pJ0rb2Hrov5uw/XUqLjm/yHBj/+aUw4yDmceqX5/EV45NWQzZlR4NpgzzsQuC8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hrI32xXj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hrI32xXj" Received: by smtp.kernel.org (Postfix) with ESMTPS id B3A5BC4CEE4; Sun, 20 Oct 2024 22:14:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729462451; bh=xa1sgEURAOgMq87x3qoMHqcD6v/zC7w+re02aI0wGmY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hrI32xXjSk5XuojCEd4FM17+nFbH6xvXj9Dtos40e33l/SsAc877hydVUPqJrE0ma HmYVMz40ZgFX15tDKLPiuCu3kfXmplFHdp7gS7nNN4SrymSyebPbLdAnzT+GgzemEN 1BVuGVnSDxigkijmrgMaXWHCUrVEJC8IcvOxGdywUYteWR0iW5uiqrVNukpizHr6G5 1RsG3UZz+fc+1odNMN8cTMIcZxpXASa39yVq3YFMlmXQg7DDLk6jcDK2fCABjDpc5J /p2ToaH73MApRTl8MhoDw/w9uUaAAglLaVvv45RYI58J7/jmbqjuyLlC1EIEQ273dc zDXeVCuCObHtA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94892D3C937; Sun, 20 Oct 2024 22:14:11 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Mon, 21 Oct 2024 00:13:22 +0200 Subject: [PATCH v2 02/13] media: i2c: imx214: Use subdev active state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-2-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=9880; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=3Ogqz6xhYtaFpj23LZAM7G3KNGD+LbuN38q1TyeyTss=; b=x5HSQM76HkIOF1wPpx4/cGa0+ZdU6A+SLFy9021Y/BaX+sO/o8r1xWBRYepi1gQZnIDt3bdVr j3dWTzPL7ztC9ir7KRIHFbWUeyCy2glTO07tHaTgo1srkgaNvaMu+rq X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch Port the imx214 sensor driver to use the subdev active state. Move all the format configuration to the subdevice state and simplify the format handling, locking and initialization. While at it, simplify imx214_start_streaming() by removing unneeded goto statements and the corresponding error label. Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 159 +++++++++++++++--------------------------= ---- 1 file changed, 53 insertions(+), 106 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 5d411452d342fdb177619cd1c9fd9650d31089bb..990fd0811904fc478c05d640540= 89fc2879cae94 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -59,8 +59,6 @@ struct imx214 { =20 struct v4l2_subdev sd; struct media_pad pad; - struct v4l2_mbus_framefmt fmt; - struct v4l2_rect crop; =20 struct v4l2_ctrl_handler ctrls; struct v4l2_ctrl *pixel_rate; @@ -68,15 +66,11 @@ struct imx214 { struct v4l2_ctrl *exposure; struct v4l2_ctrl *unit_size; =20 + const struct imx214_mode *cur_mode; + struct regulator_bulk_data supplies[IMX214_NUM_SUPPLIES]; =20 struct gpio_desc *enable_gpio; - - /* - * Serialize control access, get/set format, get selection - * and start streaming. - */ - struct mutex mutex; }; =20 struct reg_8 { @@ -490,6 +484,22 @@ static int __maybe_unused imx214_power_off(struct devi= ce *dev) return 0; } =20 +static void imx214_update_pad_format(struct imx214 *imx214, + const struct imx214_mode *mode, + struct v4l2_mbus_framefmt *fmt, u32 code) +{ + fmt->code =3D IMX214_MBUS_CODE; + fmt->width =3D mode->width; + fmt->height =3D mode->height; + fmt->field =3D V4L2_FIELD_NONE; + fmt->colorspace =3D V4L2_COLORSPACE_SRGB; + fmt->ycbcr_enc =3D V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace); + fmt->quantization =3D V4L2_MAP_QUANTIZATION_DEFAULT(true, + fmt->colorspace, + fmt->ycbcr_enc); + fmt->xfer_func =3D V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace); +} + static int imx214_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) @@ -549,52 +559,6 @@ static const struct v4l2_subdev_core_ops imx214_core_o= ps =3D { #endif }; =20 -static struct v4l2_mbus_framefmt * -__imx214_get_pad_format(struct imx214 *imx214, - struct v4l2_subdev_state *sd_state, - unsigned int pad, - enum v4l2_subdev_format_whence which) -{ - switch (which) { - case V4L2_SUBDEV_FORMAT_TRY: - return v4l2_subdev_state_get_format(sd_state, pad); - case V4L2_SUBDEV_FORMAT_ACTIVE: - return &imx214->fmt; - default: - return NULL; - } -} - -static int imx214_get_format(struct v4l2_subdev *sd, - struct v4l2_subdev_state *sd_state, - struct v4l2_subdev_format *format) -{ - struct imx214 *imx214 =3D to_imx214(sd); - - mutex_lock(&imx214->mutex); - format->format =3D *__imx214_get_pad_format(imx214, sd_state, - format->pad, - format->which); - mutex_unlock(&imx214->mutex); - - return 0; -} - -static struct v4l2_rect * -__imx214_get_pad_crop(struct imx214 *imx214, - struct v4l2_subdev_state *sd_state, - unsigned int pad, enum v4l2_subdev_format_whence which) -{ - switch (which) { - case V4L2_SUBDEV_FORMAT_TRY: - return v4l2_subdev_state_get_crop(sd_state, pad); - case V4L2_SUBDEV_FORMAT_ACTIVE: - return &imx214->crop; - default: - return NULL; - } -} - static int imx214_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *format) @@ -604,34 +568,25 @@ static int imx214_set_format(struct v4l2_subdev *sd, struct v4l2_rect *__crop; const struct imx214_mode *mode; =20 - mutex_lock(&imx214->mutex); - - __crop =3D __imx214_get_pad_crop(imx214, sd_state, format->pad, - format->which); - mode =3D v4l2_find_nearest_size(imx214_modes, ARRAY_SIZE(imx214_modes), width, height, format->format.width, format->format.height); =20 - __crop->width =3D mode->width; - __crop->height =3D mode->height; + imx214_update_pad_format(imx214, mode, &format->format, format->format.co= de); + __format =3D v4l2_subdev_state_get_format(sd_state, 0); =20 - __format =3D __imx214_get_pad_format(imx214, sd_state, format->pad, - format->which); - __format->width =3D __crop->width; - __format->height =3D __crop->height; - __format->code =3D IMX214_MBUS_CODE; - __format->field =3D V4L2_FIELD_NONE; - __format->colorspace =3D V4L2_COLORSPACE_SRGB; - __format->ycbcr_enc =3D V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace); - __format->quantization =3D V4L2_MAP_QUANTIZATION_DEFAULT(true, - __format->colorspace, __format->ycbcr_enc); - __format->xfer_func =3D V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace); + if (imx214->cur_mode =3D=3D mode && __format->code =3D=3D format->format.= code) + return 0; =20 - format->format =3D *__format; + *__format =3D format->format; =20 - mutex_unlock(&imx214->mutex); + __crop =3D v4l2_subdev_state_get_crop(sd_state, 0); + __crop->width =3D mode->width; + __crop->height =3D mode->height; + + if (format->which =3D=3D V4L2_SUBDEV_FORMAT_ACTIVE) + imx214->cur_mode =3D mode; =20 return 0; } @@ -640,14 +595,9 @@ static int imx214_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_selection *sel) { - struct imx214 *imx214 =3D to_imx214(sd); - switch (sel->target) { case V4L2_SEL_TGT_CROP: - mutex_lock(&imx214->mutex); - sel->r =3D *__imx214_get_pad_crop(imx214, sd_state, sel->pad, - sel->which); - mutex_unlock(&imx214->mutex); + sel->r =3D *v4l2_subdev_state_get_crop(sd_state, 0); return 0; =20 case V4L2_SEL_TGT_NATIVE_SIZE: @@ -826,40 +776,28 @@ static int imx214_write_table(struct imx214 *imx214, =20 static int imx214_start_streaming(struct imx214 *imx214) { - const struct imx214_mode *mode; int ret; =20 - mutex_lock(&imx214->mutex); ret =3D imx214_write_table(imx214, mode_table_common); if (ret < 0) { dev_err(imx214->dev, "could not sent common table %d\n", ret); - goto error; + return ret; } =20 - mode =3D v4l2_find_nearest_size(imx214_modes, - ARRAY_SIZE(imx214_modes), width, height, - imx214->fmt.width, imx214->fmt.height); - ret =3D imx214_write_table(imx214, mode->reg_table); + ret =3D imx214_write_table(imx214, imx214->cur_mode->reg_table); if (ret < 0) { dev_err(imx214->dev, "could not sent mode table %d\n", ret); - goto error; + return ret; } ret =3D __v4l2_ctrl_handler_setup(&imx214->ctrls); if (ret < 0) { dev_err(imx214->dev, "could not sync v4l2 controls\n"); - goto error; + return ret; } ret =3D regmap_write(imx214->regmap, IMX214_REG_MODE_SELECT, IMX214_MODE_= STREAMING); - if (ret < 0) { + if (ret < 0) dev_err(imx214->dev, "could not sent start table %d\n", ret); - goto error; - } =20 - mutex_unlock(&imx214->mutex); - return 0; - -error: - mutex_unlock(&imx214->mutex); return ret; } =20 @@ -877,6 +815,7 @@ static int imx214_stop_streaming(struct imx214 *imx214) static int imx214_s_stream(struct v4l2_subdev *subdev, int enable) { struct imx214 *imx214 =3D to_imx214(subdev); + struct v4l2_subdev_state *state; int ret; =20 if (enable) { @@ -884,7 +823,9 @@ static int imx214_s_stream(struct v4l2_subdev *subdev, = int enable) if (ret < 0) return ret; =20 + state =3D v4l2_subdev_lock_and_get_active_state(subdev); ret =3D imx214_start_streaming(imx214); + v4l2_subdev_unlock_state(state); if (ret < 0) goto err_rpm_put; } else { @@ -948,7 +889,7 @@ static const struct v4l2_subdev_pad_ops imx214_subdev_p= ad_ops =3D { .enum_mbus_code =3D imx214_enum_mbus_code, .enum_frame_size =3D imx214_enum_frame_size, .enum_frame_interval =3D imx214_enum_frame_interval, - .get_fmt =3D imx214_get_format, + .get_fmt =3D v4l2_subdev_get_fmt, .set_fmt =3D imx214_set_format, .get_selection =3D imx214_get_selection, .get_frame_interval =3D imx214_get_frame_interval, @@ -1079,13 +1020,13 @@ static int imx214_probe(struct i2c_client *client) pm_runtime_enable(imx214->dev); pm_runtime_idle(imx214->dev); =20 + /* Set default mode to max resolution */ + imx214->cur_mode =3D &imx214_modes[0]; + ret =3D imx214_ctrls_init(imx214); if (ret < 0) goto error_power_off; =20 - mutex_init(&imx214->mutex); - imx214->ctrls.lock =3D &imx214->mutex; - imx214->sd.flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE; imx214->pad.flags =3D MEDIA_PAD_FL_SOURCE; imx214->sd.dev =3D &client->dev; @@ -1097,20 +1038,27 @@ static int imx214_probe(struct i2c_client *client) goto free_ctrl; } =20 - imx214_entity_init_state(&imx214->sd, NULL); + imx214->sd.state_lock =3D imx214->ctrls.lock; + ret =3D v4l2_subdev_init_finalize(&imx214->sd); + if (ret < 0) { + dev_err(dev, "subdev init error: %d\n", ret); + goto free_entity; + } =20 ret =3D v4l2_async_register_subdev_sensor(&imx214->sd); if (ret < 0) { dev_err(dev, "could not register v4l2 device\n"); - goto free_entity; + goto error_subdev_cleanup; } =20 return 0; =20 +error_subdev_cleanup: + v4l2_subdev_cleanup(&imx214->sd); + free_entity: media_entity_cleanup(&imx214->sd.entity); free_ctrl: - mutex_destroy(&imx214->mutex); v4l2_ctrl_handler_free(&imx214->ctrls); error_power_off: pm_runtime_disable(imx214->dev); @@ -1125,13 +1073,12 @@ static void imx214_remove(struct i2c_client *client) struct imx214 *imx214 =3D to_imx214(sd); =20 v4l2_async_unregister_subdev(&imx214->sd); + v4l2_subdev_cleanup(sd); media_entity_cleanup(&imx214->sd.entity); v4l2_ctrl_handler_free(&imx214->ctrls); =20 pm_runtime_disable(&client->dev); pm_runtime_set_suspended(&client->dev); - - mutex_destroy(&imx214->mutex); } =20 static const struct of_device_id imx214_of_match[] =3D { --=20 2.47.0 From nobody Tue Nov 26 06:40:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C63519882B; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-3-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= , Ricardo Ribalda X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=3934; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=NPwSySA3gPKU4+Xr8HEmeYKsL8OgAT888MNkYNh/7tw=; b=deylbW2v+Eo3UW4C1DjzUs5xfgfRlVxu1OWqkoaD/z5T+x7ftQcfzT0GvhKvtloSdxgO+x+0w M8MtWWdI57xAQLXR2y8unW1RybKcKXfZlZKjWluOBkEZHuFZUwTRfEc X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch Error handling in probe() can be a bit simpler with dev_err_probe(). Acked-by: Ricardo Ribalda Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 52 ++++++++++++++++++++----------------------= ---- 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 990fd0811904fc478c05d64054089fc2879cae94..fc734a162e655228d412ebe0646= d64dc0c94f92a 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -933,14 +933,12 @@ static int imx214_parse_fwnode(struct device *dev) int ret; =20 endpoint =3D fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); - if (!endpoint) { - dev_err(dev, "endpoint node not found\n"); - return -EINVAL; - } + if (!endpoint) + return dev_err_probe(dev, -EINVAL, "endpoint node not found\n"); =20 ret =3D v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg); if (ret) { - dev_err(dev, "parsing endpoint node failed\n"); + dev_err_probe(dev, ret, "parsing endpoint node failed\n"); goto done; } =20 @@ -949,8 +947,9 @@ static int imx214_parse_fwnode(struct device *dev) break; =20 if (i =3D=3D bus_cfg.nr_of_link_frequencies) { - dev_err(dev, "link-frequencies %d not supported, Please review your DT\n= ", - IMX214_DEFAULT_LINK_FREQ); + dev_err_probe(dev, -EINVAL, + "link-frequencies %d not supported, Please review your DT\n", + IMX214_DEFAULT_LINK_FREQ); ret =3D -EINVAL; goto done; } @@ -978,34 +977,27 @@ static int imx214_probe(struct i2c_client *client) imx214->dev =3D dev; =20 imx214->xclk =3D devm_clk_get(dev, NULL); - if (IS_ERR(imx214->xclk)) { - dev_err(dev, "could not get xclk"); - return PTR_ERR(imx214->xclk); - } + if (IS_ERR(imx214->xclk)) + return dev_err_probe(dev, PTR_ERR(imx214->xclk), + "failed to get xclk\n"); =20 ret =3D clk_set_rate(imx214->xclk, IMX214_DEFAULT_CLK_FREQ); - if (ret) { - dev_err(dev, "could not set xclk frequency\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to set xclk frequency\n"); =20 ret =3D imx214_get_regulators(dev, imx214); - if (ret < 0) { - dev_err(dev, "cannot get regulators\n"); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get regulators\n"); =20 imx214->enable_gpio =3D devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); - if (IS_ERR(imx214->enable_gpio)) { - dev_err(dev, "cannot get enable gpio\n"); - return PTR_ERR(imx214->enable_gpio); - } + if (IS_ERR(imx214->enable_gpio)) + return dev_err_probe(dev, PTR_ERR(imx214->enable_gpio), + "failed to get enable gpio\n"); =20 imx214->regmap =3D devm_regmap_init_i2c(client, &sensor_regmap_config); - if (IS_ERR(imx214->regmap)) { - dev_err(dev, "regmap init failed\n"); - return PTR_ERR(imx214->regmap); - } + if (IS_ERR(imx214->regmap)) + return dev_err_probe(dev, PTR_ERR(imx214->regmap), + "regmap init failed\n"); =20 v4l2_i2c_subdev_init(&imx214->sd, client, &imx214_subdev_ops); imx214->sd.internal_ops =3D &imx214_internal_ops; @@ -1034,20 +1026,20 @@ static int imx214_probe(struct i2c_client *client) =20 ret =3D media_entity_pads_init(&imx214->sd.entity, 1, &imx214->pad); if (ret < 0) { - dev_err(dev, "could not register media entity\n"); + dev_err_probe(dev, ret, "failed to init entity pads\n"); goto free_ctrl; } =20 imx214->sd.state_lock =3D imx214->ctrls.lock; ret =3D v4l2_subdev_init_finalize(&imx214->sd); if (ret < 0) { - dev_err(dev, "subdev init error: %d\n", ret); + dev_err_probe(dev, ret, "subdev init error\n"); goto free_entity; } =20 ret =3D v4l2_async_register_subdev_sensor(&imx214->sd); if (ret < 0) { - dev_err(dev, "could not register v4l2 device\n"); + dev_err_probe(dev, ret, "failed to register sensor sub-device\n"); goto error_subdev_cleanup; } =20 --=20 2.47.0 From nobody Tue Nov 26 06:40:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52C5F198A0E; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-4-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= , Ricardo Ribalda X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=20767; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=DzAVLX6vxykGkz+i8HPrWgeKM1naMeJGthoH7A+iHF8=; b=a7Wk2CA9DSg569EhE5AyiTPBK9fDck0zrFQPTuam/pMA4r1XAzFVE8V+5752a8vakuaPbH6iN JfI9/GOmRUpCuer0cB5vZHJjaYXj2mrx9gpWFrpQkqI5+HdrPO2IXe9 X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch Use the new common CCI register access helpers to replace the private register access helpers in the imx214 driver. This simplifies the driver by reducing the amount of code. Acked-by: Ricardo Ribalda Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/Kconfig | 1 + drivers/media/i2c/imx214.c | 672 +++++++++++++++++++++--------------------= ---- 2 files changed, 310 insertions(+), 363 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 8ba096b8ebca241239a327ab3af0d9bce3ee9962..85ecb2aeefdbfff744c8de86866= 560518abeace1 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -140,6 +140,7 @@ config VIDEO_IMX214 tristate "Sony IMX214 sensor support" depends on GPIOLIB select REGMAP_I2C + select V4L2_CCI_I2C help This is a Video4Linux2 sensor driver for the Sony IMX214 camera. diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index fc734a162e655228d412ebe0646d64dc0c94f92a..d505c3df33989b78db6af269e86= 0d42a7a0b2f24 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -15,11 +15,12 @@ #include #include #include +#include #include #include #include =20 -#define IMX214_REG_MODE_SELECT 0x0100 +#define IMX214_REG_MODE_SELECT CCI_REG8(0x0100) #define IMX214_MODE_STANDBY 0x00 #define IMX214_MODE_STREAMING 0x01 =20 @@ -30,7 +31,7 @@ #define IMX214_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10 =20 /* Exposure control */ -#define IMX214_REG_EXPOSURE 0x0202 +#define IMX214_REG_EXPOSURE CCI_REG16(0x0202) #define IMX214_EXPOSURE_MIN 0 #define IMX214_EXPOSURE_MAX 3184 #define IMX214_EXPOSURE_STEP 1 @@ -73,345 +74,324 @@ struct imx214 { struct gpio_desc *enable_gpio; }; =20 -struct reg_8 { - u16 addr; - u8 val; -}; - -enum { - IMX214_TABLE_WAIT_MS =3D 0, - IMX214_TABLE_END, - IMX214_MAX_RETRIES, - IMX214_WAIT_MS -}; - /*From imx214_mode_tbls.h*/ -static const struct reg_8 mode_4096x2304[] =3D { - {0x0114, 0x03}, - {0x0220, 0x00}, - {0x0221, 0x11}, - {0x0222, 0x01}, - {0x0340, 0x0C}, - {0x0341, 0x7A}, - {0x0342, 0x13}, - {0x0343, 0x90}, - {0x0344, 0x00}, - {0x0345, 0x38}, - {0x0346, 0x01}, - {0x0347, 0x98}, - {0x0348, 0x10}, - {0x0349, 0x37}, - {0x034A, 0x0A}, - {0x034B, 0x97}, - {0x0381, 0x01}, - {0x0383, 0x01}, - {0x0385, 0x01}, - {0x0387, 0x01}, - {0x0900, 0x00}, - {0x0901, 0x00}, - {0x0902, 0x00}, - {0x3000, 0x35}, - {0x3054, 0x01}, - {0x305C, 0x11}, - - {0x0112, 0x0A}, - {0x0113, 0x0A}, - {0x034C, 0x10}, - {0x034D, 0x00}, - {0x034E, 0x09}, - {0x034F, 0x00}, - {0x0401, 0x00}, - {0x0404, 0x00}, - {0x0405, 0x10}, - {0x0408, 0x00}, - {0x0409, 0x00}, - {0x040A, 0x00}, - {0x040B, 0x00}, - {0x040C, 0x10}, - {0x040D, 0x00}, - {0x040E, 0x09}, - {0x040F, 0x00}, - - {0x0301, 0x05}, - {0x0303, 0x02}, - {0x0305, 0x03}, - {0x0306, 0x00}, - {0x0307, 0x96}, - {0x0309, 0x0A}, - {0x030B, 0x01}, - {0x0310, 0x00}, - - {0x0820, 0x12}, - {0x0821, 0xC0}, - {0x0822, 0x00}, - {0x0823, 0x00}, - - {0x3A03, 0x09}, - {0x3A04, 0x50}, - {0x3A05, 0x01}, - - {0x0B06, 0x01}, - {0x30A2, 0x00}, - - {0x30B4, 0x00}, - - {0x3A02, 0xFF}, - - {0x3011, 0x00}, - {0x3013, 0x01}, - - {0x0202, 0x0C}, - {0x0203, 0x70}, - {0x0224, 0x01}, - {0x0225, 0xF4}, - - {0x0204, 0x00}, - {0x0205, 0x00}, - {0x020E, 0x01}, - {0x020F, 0x00}, - {0x0210, 0x01}, - {0x0211, 0x00}, - {0x0212, 0x01}, - {0x0213, 0x00}, - {0x0214, 0x01}, - {0x0215, 0x00}, - {0x0216, 0x00}, - {0x0217, 0x00}, - - {0x4170, 0x00}, - {0x4171, 0x10}, - {0x4176, 0x00}, - {0x4177, 0x3C}, - {0xAE20, 0x04}, - {0xAE21, 0x5C}, - - {IMX214_TABLE_WAIT_MS, 10}, - {0x0138, 0x01}, - {IMX214_TABLE_END, 0x00} +static const struct cci_reg_sequence mode_4096x2304[] =3D { + { CCI_REG8(0x0114), 0x03 }, + { CCI_REG8(0x0220), 0x00 }, + { CCI_REG8(0x0221), 0x11 }, + { CCI_REG8(0x0222), 0x01 }, + { CCI_REG8(0x0340), 0x0C }, + { CCI_REG8(0x0341), 0x7A }, + { CCI_REG8(0x0342), 0x13 }, + { CCI_REG8(0x0343), 0x90 }, + { CCI_REG8(0x0344), 0x00 }, + { CCI_REG8(0x0345), 0x38 }, + { CCI_REG8(0x0346), 0x01 }, + { CCI_REG8(0x0347), 0x98 }, + { CCI_REG8(0x0348), 0x10 }, + { CCI_REG8(0x0349), 0x37 }, + { CCI_REG8(0x034A), 0x0A }, + { CCI_REG8(0x034B), 0x97 }, + { CCI_REG8(0x0381), 0x01 }, + { CCI_REG8(0x0383), 0x01 }, + { CCI_REG8(0x0385), 0x01 }, + { CCI_REG8(0x0387), 0x01 }, + { CCI_REG8(0x0900), 0x00 }, + { CCI_REG8(0x0901), 0x00 }, + { CCI_REG8(0x0902), 0x00 }, + { CCI_REG8(0x3000), 0x35 }, + { CCI_REG8(0x3054), 0x01 }, + { CCI_REG8(0x305C), 0x11 }, + + { CCI_REG8(0x0112), 0x0A }, + { CCI_REG8(0x0113), 0x0A }, + { CCI_REG8(0x034C), 0x10 }, + { CCI_REG8(0x034D), 0x00 }, + { CCI_REG8(0x034E), 0x09 }, + { CCI_REG8(0x034F), 0x00 }, + { CCI_REG8(0x0401), 0x00 }, + { CCI_REG8(0x0404), 0x00 }, + { CCI_REG8(0x0405), 0x10 }, + { CCI_REG8(0x0408), 0x00 }, + { CCI_REG8(0x0409), 0x00 }, + { CCI_REG8(0x040A), 0x00 }, + { CCI_REG8(0x040B), 0x00 }, + { CCI_REG8(0x040C), 0x10 }, + { CCI_REG8(0x040D), 0x00 }, + { CCI_REG8(0x040E), 0x09 }, + { CCI_REG8(0x040F), 0x00 }, + + { CCI_REG8(0x0301), 0x05 }, + { CCI_REG8(0x0303), 0x02 }, + { CCI_REG8(0x0305), 0x03 }, + { CCI_REG8(0x0306), 0x00 }, + { CCI_REG8(0x0307), 0x96 }, + { CCI_REG8(0x0309), 0x0A }, + { CCI_REG8(0x030B), 0x01 }, + { CCI_REG8(0x0310), 0x00 }, + + { CCI_REG8(0x0820), 0x12 }, + { CCI_REG8(0x0821), 0xC0 }, + { CCI_REG8(0x0822), 0x00 }, + { CCI_REG8(0x0823), 0x00 }, + + { CCI_REG8(0x3A03), 0x09 }, + { CCI_REG8(0x3A04), 0x50 }, + { CCI_REG8(0x3A05), 0x01 }, + + { CCI_REG8(0x0B06), 0x01 }, + { CCI_REG8(0x30A2), 0x00 }, + + { CCI_REG8(0x30B4), 0x00 }, + + { CCI_REG8(0x3A02), 0xFF }, + + { CCI_REG8(0x3011), 0x00 }, + { CCI_REG8(0x3013), 0x01 }, + + { CCI_REG8(0x0202), 0x0C }, + { CCI_REG8(0x0203), 0x70 }, + { CCI_REG8(0x0224), 0x01 }, + { CCI_REG8(0x0225), 0xF4 }, + + { CCI_REG8(0x0204), 0x00 }, + { CCI_REG8(0x0205), 0x00 }, + { CCI_REG8(0x020E), 0x01 }, + { CCI_REG8(0x020F), 0x00 }, + { CCI_REG8(0x0210), 0x01 }, + { CCI_REG8(0x0211), 0x00 }, + { CCI_REG8(0x0212), 0x01 }, + { CCI_REG8(0x0213), 0x00 }, + { CCI_REG8(0x0214), 0x01 }, + { CCI_REG8(0x0215), 0x00 }, + { CCI_REG8(0x0216), 0x00 }, + { CCI_REG8(0x0217), 0x00 }, + + { CCI_REG8(0x4170), 0x00 }, + { CCI_REG8(0x4171), 0x10 }, + { CCI_REG8(0x4176), 0x00 }, + { CCI_REG8(0x4177), 0x3C }, + { CCI_REG8(0xAE20), 0x04 }, + { CCI_REG8(0xAE21), 0x5C }, }; =20 -static const struct reg_8 mode_1920x1080[] =3D { - {0x0114, 0x03}, - {0x0220, 0x00}, - {0x0221, 0x11}, - {0x0222, 0x01}, - {0x0340, 0x0C}, - {0x0341, 0x7A}, - {0x0342, 0x13}, - {0x0343, 0x90}, - {0x0344, 0x04}, - {0x0345, 0x78}, - {0x0346, 0x03}, - {0x0347, 0xFC}, - {0x0348, 0x0B}, - {0x0349, 0xF7}, - {0x034A, 0x08}, - {0x034B, 0x33}, - {0x0381, 0x01}, - {0x0383, 0x01}, - {0x0385, 0x01}, - {0x0387, 0x01}, - {0x0900, 0x00}, - {0x0901, 0x00}, - {0x0902, 0x00}, - {0x3000, 0x35}, - {0x3054, 0x01}, - {0x305C, 0x11}, - - {0x0112, 0x0A}, - {0x0113, 0x0A}, - {0x034C, 0x07}, - {0x034D, 0x80}, - {0x034E, 0x04}, - {0x034F, 0x38}, - {0x0401, 0x00}, - {0x0404, 0x00}, - {0x0405, 0x10}, - {0x0408, 0x00}, - {0x0409, 0x00}, - {0x040A, 0x00}, - {0x040B, 0x00}, - {0x040C, 0x07}, - {0x040D, 0x80}, - {0x040E, 0x04}, - {0x040F, 0x38}, - - {0x0301, 0x05}, - {0x0303, 0x02}, - {0x0305, 0x03}, - {0x0306, 0x00}, - {0x0307, 0x96}, - {0x0309, 0x0A}, - {0x030B, 0x01}, - {0x0310, 0x00}, - - {0x0820, 0x12}, - {0x0821, 0xC0}, - {0x0822, 0x00}, - {0x0823, 0x00}, - - {0x3A03, 0x04}, - {0x3A04, 0xF8}, - {0x3A05, 0x02}, - - {0x0B06, 0x01}, - {0x30A2, 0x00}, - - {0x30B4, 0x00}, - - {0x3A02, 0xFF}, - - {0x3011, 0x00}, - {0x3013, 0x01}, - - {0x0202, 0x0C}, - {0x0203, 0x70}, - {0x0224, 0x01}, - {0x0225, 0xF4}, - - {0x0204, 0x00}, - {0x0205, 0x00}, - {0x020E, 0x01}, - {0x020F, 0x00}, - {0x0210, 0x01}, - {0x0211, 0x00}, - {0x0212, 0x01}, - {0x0213, 0x00}, - {0x0214, 0x01}, - {0x0215, 0x00}, - {0x0216, 0x00}, - {0x0217, 0x00}, - - {0x4170, 0x00}, - {0x4171, 0x10}, - {0x4176, 0x00}, - {0x4177, 0x3C}, - {0xAE20, 0x04}, - {0xAE21, 0x5C}, - - {IMX214_TABLE_WAIT_MS, 10}, - {0x0138, 0x01}, - {IMX214_TABLE_END, 0x00} +static const struct cci_reg_sequence mode_1920x1080[] =3D { + { CCI_REG8(0x0114), 0x03 }, + { CCI_REG8(0x0220), 0x00 }, + { CCI_REG8(0x0221), 0x11 }, + { CCI_REG8(0x0222), 0x01 }, + { CCI_REG8(0x0340), 0x0C }, + { CCI_REG8(0x0341), 0x7A }, + { CCI_REG8(0x0342), 0x13 }, + { CCI_REG8(0x0343), 0x90 }, + { CCI_REG8(0x0344), 0x04 }, + { CCI_REG8(0x0345), 0x78 }, + { CCI_REG8(0x0346), 0x03 }, + { CCI_REG8(0x0347), 0xFC }, + { CCI_REG8(0x0348), 0x0B }, + { CCI_REG8(0x0349), 0xF7 }, + { CCI_REG8(0x034A), 0x08 }, + { CCI_REG8(0x034B), 0x33 }, + { CCI_REG8(0x0381), 0x01 }, + { CCI_REG8(0x0383), 0x01 }, + { CCI_REG8(0x0385), 0x01 }, + { CCI_REG8(0x0387), 0x01 }, + { CCI_REG8(0x0900), 0x00 }, + { CCI_REG8(0x0901), 0x00 }, + { CCI_REG8(0x0902), 0x00 }, + { CCI_REG8(0x3000), 0x35 }, + { CCI_REG8(0x3054), 0x01 }, + { CCI_REG8(0x305C), 0x11 }, + + { CCI_REG8(0x0112), 0x0A }, + { CCI_REG8(0x0113), 0x0A }, + { CCI_REG8(0x034C), 0x07 }, + { CCI_REG8(0x034D), 0x80 }, + { CCI_REG8(0x034E), 0x04 }, + { CCI_REG8(0x034F), 0x38 }, + { CCI_REG8(0x0401), 0x00 }, + { CCI_REG8(0x0404), 0x00 }, + { CCI_REG8(0x0405), 0x10 }, + { CCI_REG8(0x0408), 0x00 }, + { CCI_REG8(0x0409), 0x00 }, + { CCI_REG8(0x040A), 0x00 }, + { CCI_REG8(0x040B), 0x00 }, + { CCI_REG8(0x040C), 0x07 }, + { CCI_REG8(0x040D), 0x80 }, + { CCI_REG8(0x040E), 0x04 }, + { CCI_REG8(0x040F), 0x38 }, + + { CCI_REG8(0x0301), 0x05 }, + { CCI_REG8(0x0303), 0x02 }, + { CCI_REG8(0x0305), 0x03 }, + { CCI_REG8(0x0306), 0x00 }, + { CCI_REG8(0x0307), 0x96 }, + { CCI_REG8(0x0309), 0x0A }, + { CCI_REG8(0x030B), 0x01 }, + { CCI_REG8(0x0310), 0x00 }, + + { CCI_REG8(0x0820), 0x12 }, + { CCI_REG8(0x0821), 0xC0 }, + { CCI_REG8(0x0822), 0x00 }, + { CCI_REG8(0x0823), 0x00 }, + + { CCI_REG8(0x3A03), 0x04 }, + { CCI_REG8(0x3A04), 0xF8 }, + { CCI_REG8(0x3A05), 0x02 }, + + { CCI_REG8(0x0B06), 0x01 }, + { CCI_REG8(0x30A2), 0x00 }, + + { CCI_REG8(0x30B4), 0x00 }, + + { CCI_REG8(0x3A02), 0xFF }, + + { CCI_REG8(0x3011), 0x00 }, + { CCI_REG8(0x3013), 0x01 }, + + { CCI_REG8(0x0202), 0x0C }, + { CCI_REG8(0x0203), 0x70 }, + { CCI_REG8(0x0224), 0x01 }, + { CCI_REG8(0x0225), 0xF4 }, + + { CCI_REG8(0x0204), 0x00 }, + { CCI_REG8(0x0205), 0x00 }, + { CCI_REG8(0x020E), 0x01 }, + { CCI_REG8(0x020F), 0x00 }, + { CCI_REG8(0x0210), 0x01 }, + { CCI_REG8(0x0211), 0x00 }, + { CCI_REG8(0x0212), 0x01 }, + { CCI_REG8(0x0213), 0x00 }, + { CCI_REG8(0x0214), 0x01 }, + { CCI_REG8(0x0215), 0x00 }, + { CCI_REG8(0x0216), 0x00 }, + { CCI_REG8(0x0217), 0x00 }, + + { CCI_REG8(0x4170), 0x00 }, + { CCI_REG8(0x4171), 0x10 }, + { CCI_REG8(0x4176), 0x00 }, + { CCI_REG8(0x4177), 0x3C }, + { CCI_REG8(0xAE20), 0x04 }, + { CCI_REG8(0xAE21), 0x5C }, }; =20 -static const struct reg_8 mode_table_common[] =3D { +static const struct cci_reg_sequence mode_table_common[] =3D { /* software reset */ =20 /* software standby settings */ - {0x0100, 0x00}, + { CCI_REG8(0x0100), 0x00 }, =20 /* ATR setting */ - {0x9300, 0x02}, + { CCI_REG8(0x9300), 0x02 }, =20 /* external clock setting */ - {0x0136, 0x18}, - {0x0137, 0x00}, + { CCI_REG8(0x0136), 0x18 }, + { CCI_REG8(0x0137), 0x00 }, =20 /* global setting */ /* basic config */ - {0x0101, 0x00}, - {0x0105, 0x01}, - {0x0106, 0x01}, - {0x4550, 0x02}, - {0x4601, 0x00}, - {0x4642, 0x05}, - {0x6227, 0x11}, - {0x6276, 0x00}, - {0x900E, 0x06}, - {0xA802, 0x90}, - {0xA803, 0x11}, - {0xA804, 0x62}, - {0xA805, 0x77}, - {0xA806, 0xAE}, - {0xA807, 0x34}, - {0xA808, 0xAE}, - {0xA809, 0x35}, - {0xA80A, 0x62}, - {0xA80B, 0x83}, - {0xAE33, 0x00}, + { CCI_REG8(0x0101), 0x00 }, + { CCI_REG8(0x0105), 0x01 }, + { CCI_REG8(0x0106), 0x01 }, + { CCI_REG8(0x4550), 0x02 }, + { CCI_REG8(0x4601), 0x00 }, + { CCI_REG8(0x4642), 0x05 }, + { CCI_REG8(0x6227), 0x11 }, + { CCI_REG8(0x6276), 0x00 }, + { CCI_REG8(0x900E), 0x06 }, + { CCI_REG8(0xA802), 0x90 }, + { CCI_REG8(0xA803), 0x11 }, + { CCI_REG8(0xA804), 0x62 }, + { CCI_REG8(0xA805), 0x77 }, + { CCI_REG8(0xA806), 0xAE }, + { CCI_REG8(0xA807), 0x34 }, + { CCI_REG8(0xA808), 0xAE }, + { CCI_REG8(0xA809), 0x35 }, + { CCI_REG8(0xA80A), 0x62 }, + { CCI_REG8(0xA80B), 0x83 }, + { CCI_REG8(0xAE33), 0x00 }, =20 /* analog setting */ - {0x4174, 0x00}, - {0x4175, 0x11}, - {0x4612, 0x29}, - {0x461B, 0x12}, - {0x461F, 0x06}, - {0x4635, 0x07}, - {0x4637, 0x30}, - {0x463F, 0x18}, - {0x4641, 0x0D}, - {0x465B, 0x12}, - {0x465F, 0x11}, - {0x4663, 0x11}, - {0x4667, 0x0F}, - {0x466F, 0x0F}, - {0x470E, 0x09}, - {0x4909, 0xAB}, - {0x490B, 0x95}, - {0x4915, 0x5D}, - {0x4A5F, 0xFF}, - {0x4A61, 0xFF}, - {0x4A73, 0x62}, - {0x4A85, 0x00}, - {0x4A87, 0xFF}, + { CCI_REG8(0x4174), 0x00 }, + { CCI_REG8(0x4175), 0x11 }, + { CCI_REG8(0x4612), 0x29 }, + { CCI_REG8(0x461B), 0x12 }, + { CCI_REG8(0x461F), 0x06 }, + { CCI_REG8(0x4635), 0x07 }, + { CCI_REG8(0x4637), 0x30 }, + { CCI_REG8(0x463F), 0x18 }, + { CCI_REG8(0x4641), 0x0D }, + { CCI_REG8(0x465B), 0x12 }, + { CCI_REG8(0x465F), 0x11 }, + { CCI_REG8(0x4663), 0x11 }, + { CCI_REG8(0x4667), 0x0F }, + { CCI_REG8(0x466F), 0x0F }, + { CCI_REG8(0x470E), 0x09 }, + { CCI_REG8(0x4909), 0xAB }, + { CCI_REG8(0x490B), 0x95 }, + { CCI_REG8(0x4915), 0x5D }, + { CCI_REG8(0x4A5F), 0xFF }, + { CCI_REG8(0x4A61), 0xFF }, + { CCI_REG8(0x4A73), 0x62 }, + { CCI_REG8(0x4A85), 0x00 }, + { CCI_REG8(0x4A87), 0xFF }, =20 /* embedded data */ - {0x5041, 0x04}, - {0x583C, 0x04}, - {0x620E, 0x04}, - {0x6EB2, 0x01}, - {0x6EB3, 0x00}, - {0x9300, 0x02}, + { CCI_REG8(0x5041), 0x04 }, + { CCI_REG8(0x583C), 0x04 }, + { CCI_REG8(0x620E), 0x04 }, + { CCI_REG8(0x6EB2), 0x01 }, + { CCI_REG8(0x6EB3), 0x00 }, + { CCI_REG8(0x9300), 0x02 }, =20 /* imagequality */ /* HDR setting */ - {0x3001, 0x07}, - {0x6D12, 0x3F}, - {0x6D13, 0xFF}, - {0x9344, 0x03}, - {0x9706, 0x10}, - {0x9707, 0x03}, - {0x9708, 0x03}, - {0x9E04, 0x01}, - {0x9E05, 0x00}, - {0x9E0C, 0x01}, - {0x9E0D, 0x02}, - {0x9E24, 0x00}, - {0x9E25, 0x8C}, - {0x9E26, 0x00}, - {0x9E27, 0x94}, - {0x9E28, 0x00}, - {0x9E29, 0x96}, + { CCI_REG8(0x3001), 0x07 }, + { CCI_REG8(0x6D12), 0x3F }, + { CCI_REG8(0x6D13), 0xFF }, + { CCI_REG8(0x9344), 0x03 }, + { CCI_REG8(0x9706), 0x10 }, + { CCI_REG8(0x9707), 0x03 }, + { CCI_REG8(0x9708), 0x03 }, + { CCI_REG8(0x9E04), 0x01 }, + { CCI_REG8(0x9E05), 0x00 }, + { CCI_REG8(0x9E0C), 0x01 }, + { CCI_REG8(0x9E0D), 0x02 }, + { CCI_REG8(0x9E24), 0x00 }, + { CCI_REG8(0x9E25), 0x8C }, + { CCI_REG8(0x9E26), 0x00 }, + { CCI_REG8(0x9E27), 0x94 }, + { CCI_REG8(0x9E28), 0x00 }, + { CCI_REG8(0x9E29), 0x96 }, =20 /* CNR parameter setting */ - {0x69DB, 0x01}, + { CCI_REG8(0x69DB), 0x01 }, =20 /* Moire reduction */ - {0x6957, 0x01}, + { CCI_REG8(0x6957), 0x01 }, =20 /* image enhancement */ - {0x6987, 0x17}, - {0x698A, 0x03}, - {0x698B, 0x03}, + { CCI_REG8(0x6987), 0x17 }, + { CCI_REG8(0x698A), 0x03 }, + { CCI_REG8(0x698B), 0x03 }, =20 /* white balanace */ - {0x0B8E, 0x01}, - {0x0B8F, 0x00}, - {0x0B90, 0x01}, - {0x0B91, 0x00}, - {0x0B92, 0x01}, - {0x0B93, 0x00}, - {0x0B94, 0x01}, - {0x0B95, 0x00}, + { CCI_REG8(0x0B8E), 0x01 }, + { CCI_REG8(0x0B8F), 0x00 }, + { CCI_REG8(0x0B90), 0x01 }, + { CCI_REG8(0x0B91), 0x00 }, + { CCI_REG8(0x0B92), 0x01 }, + { CCI_REG8(0x0B93), 0x00 }, + { CCI_REG8(0x0B94), 0x01 }, + { CCI_REG8(0x0B95), 0x00 }, =20 /* ATR setting */ - {0x6E50, 0x00}, - {0x6E51, 0x32}, - {0x9340, 0x00}, - {0x9341, 0x3C}, - {0x9342, 0x03}, - {0x9343, 0xFF}, - {IMX214_TABLE_END, 0x00} + { CCI_REG8(0x6E50), 0x00 }, + { CCI_REG8(0x6E51), 0x32 }, + { CCI_REG8(0x9340), 0x00 }, + { CCI_REG8(0x9341), 0x3C }, + { CCI_REG8(0x9342), 0x03 }, + { CCI_REG8(0x9343), 0xFF }, }; =20 /* @@ -421,16 +401,19 @@ static const struct reg_8 mode_table_common[] =3D { static const struct imx214_mode { u32 width; u32 height; - const struct reg_8 *reg_table; + unsigned int num_of_regs; + const struct cci_reg_sequence *reg_table; } imx214_modes[] =3D { { .width =3D 4096, .height =3D 2304, + .num_of_regs =3D ARRAY_SIZE(mode_4096x2304), .reg_table =3D mode_4096x2304, }, { .width =3D 1920, .height =3D 1080, + .num_of_regs =3D ARRAY_SIZE(mode_1920x1080), .reg_table =3D mode_1920x1080, }, }; @@ -637,7 +620,6 @@ static int imx214_set_ctrl(struct v4l2_ctrl *ctrl) { struct imx214 *imx214 =3D container_of(ctrl->handler, struct imx214, ctrls); - u8 vals[2]; int ret; =20 /* @@ -649,12 +631,7 @@ static int imx214_set_ctrl(struct v4l2_ctrl *ctrl) =20 switch (ctrl->id) { case V4L2_CID_EXPOSURE: - vals[1] =3D ctrl->val; - vals[0] =3D ctrl->val >> 8; - ret =3D regmap_bulk_write(imx214->regmap, IMX214_REG_EXPOSURE, vals, 2); - if (ret < 0) - dev_err(imx214->dev, "Error %d\n", ret); - ret =3D 0; + cci_write(imx214->regmap, IMX214_REG_EXPOSURE, ctrl->val, &ret); break; =20 default: @@ -740,61 +717,35 @@ static int imx214_ctrls_init(struct imx214 *imx214) return 0; }; =20 -#define MAX_CMD 4 -static int imx214_write_table(struct imx214 *imx214, - const struct reg_8 table[]) -{ - u8 vals[MAX_CMD]; - int i; - int ret; - - for (; table->addr !=3D IMX214_TABLE_END ; table++) { - if (table->addr =3D=3D IMX214_TABLE_WAIT_MS) { - usleep_range(table->val * 1000, - table->val * 1000 + 500); - continue; - } - - for (i =3D 0; i < MAX_CMD; i++) { - if (table[i].addr !=3D (table[0].addr + i)) - break; - vals[i] =3D table[i].val; - } - - ret =3D regmap_bulk_write(imx214->regmap, table->addr, vals, i); - - if (ret) { - dev_err(imx214->dev, "write_table error: %d\n", ret); - return ret; - } - - table +=3D i - 1; - } - - return 0; -} - static int imx214_start_streaming(struct imx214 *imx214) { int ret; =20 - ret =3D imx214_write_table(imx214, mode_table_common); + ret =3D cci_multi_reg_write(imx214->regmap, mode_table_common, + ARRAY_SIZE(mode_table_common), NULL); if (ret < 0) { dev_err(imx214->dev, "could not sent common table %d\n", ret); return ret; } =20 - ret =3D imx214_write_table(imx214, imx214->cur_mode->reg_table); + ret =3D cci_multi_reg_write(imx214->regmap, imx214->cur_mode->reg_table, + imx214->cur_mode->num_of_regs, NULL); if (ret < 0) { dev_err(imx214->dev, "could not sent mode table %d\n", ret); return ret; } + + usleep_range(10000, 10500); + + cci_write(imx214->regmap, CCI_REG8(0x0138), 0x01, NULL); + ret =3D __v4l2_ctrl_handler_setup(&imx214->ctrls); if (ret < 0) { dev_err(imx214->dev, "could not sync v4l2 controls\n"); return ret; } - ret =3D regmap_write(imx214->regmap, IMX214_REG_MODE_SELECT, IMX214_MODE_= STREAMING); + ret =3D cci_write(imx214->regmap, IMX214_REG_MODE_SELECT, + IMX214_MODE_STREAMING, NULL); if (ret < 0) dev_err(imx214->dev, "could not sent start table %d\n", ret); =20 @@ -805,7 +756,8 @@ static int imx214_stop_streaming(struct imx214 *imx214) { int ret; =20 - ret =3D regmap_write(imx214->regmap, IMX214_REG_MODE_SELECT, IMX214_MODE_= STANDBY); + ret =3D cci_write(imx214->regmap, IMX214_REG_MODE_SELECT, + IMX214_MODE_STANDBY, NULL); if (ret < 0) dev_err(imx214->dev, "could not sent stop table %d\n", ret); =20 @@ -906,12 +858,6 @@ static const struct v4l2_subdev_internal_ops imx214_in= ternal_ops =3D { .init_state =3D imx214_entity_init_state, }; =20 -static const struct regmap_config sensor_regmap_config =3D { - .reg_bits =3D 16, - .val_bits =3D 8, - .cache_type =3D REGCACHE_MAPLE, -}; - static int imx214_get_regulators(struct device *dev, struct imx214 *imx214) { unsigned int i; @@ -994,10 +940,10 @@ static int imx214_probe(struct i2c_client *client) return dev_err_probe(dev, PTR_ERR(imx214->enable_gpio), "failed to get enable gpio\n"); =20 - imx214->regmap =3D devm_regmap_init_i2c(client, &sensor_regmap_config); + imx214->regmap =3D devm_cci_regmap_init_i2c(client, 16); if (IS_ERR(imx214->regmap)) return dev_err_probe(dev, PTR_ERR(imx214->regmap), - "regmap init failed\n"); + "failed to initialize CCI\n"); =20 v4l2_i2c_subdev_init(&imx214->sd, client, &imx214_subdev_ops); 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Sun, 20 Oct 2024 22:14:11 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Mon, 21 Oct 2024 00:13:25 +0200 Subject: [PATCH v2 05/13] media: i2c: imx214: Replace register addresses with macros Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-5-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= , Ricardo Ribalda X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=17649; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=Se8LwMOB1MKmwwLCyFCAs8ODcdbQC4H8CUkUdSVcTr0=; b=a6Dmpq2xRh499PeAaRShcbvZ+qoZOpSgrr2CUx8WNn02R2hDL5CvKtrTclh4qgkFnxq1dtNTA Qu2F786ane5AyNPLan6kmBdhtcZRrU6vyKg/b9dbGVexwcQ0ijH1f1t X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch Define macros for all the known registers used in the register arrays, and use them to replace the numerical addresses. This improves readability. Acked-by: Ricardo Ribalda Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 407 ++++++++++++++++++++++++++---------------= ---- 1 file changed, 236 insertions(+), 171 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index d505c3df33989b78db6af269e860d42a7a0b2f24..49beba5807c5dd84109fe90b745= de0484d01390c 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -24,18 +24,141 @@ #define IMX214_MODE_STANDBY 0x00 #define IMX214_MODE_STREAMING 0x01 =20 +#define IMX214_REG_FAST_STANDBY_CTRL CCI_REG8(0x0106) + #define IMX214_DEFAULT_CLK_FREQ 24000000 #define IMX214_DEFAULT_LINK_FREQ 600000000 #define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10) #define IMX214_FPS 30 #define IMX214_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10 =20 +/* V-TIMING internal */ +#define IMX214_REG_FRM_LENGTH_LINES CCI_REG16(0x0340) + /* Exposure control */ #define IMX214_REG_EXPOSURE CCI_REG16(0x0202) #define IMX214_EXPOSURE_MIN 0 #define IMX214_EXPOSURE_MAX 3184 #define IMX214_EXPOSURE_STEP 1 #define IMX214_EXPOSURE_DEFAULT 3184 +#define IMX214_REG_EXPOSURE_RATIO CCI_REG8(0x0222) +#define IMX214_REG_SHORT_EXPOSURE CCI_REG16(0x0224) + +/* Analog gain control */ +#define IMX214_REG_ANALOG_GAIN CCI_REG16(0x0204) +#define IMX214_REG_SHORT_ANALOG_GAIN CCI_REG16(0x0216) + +/* Digital gain control */ +#define IMX214_REG_DIG_GAIN_GREENR CCI_REG16(0x020e) +#define IMX214_REG_DIG_GAIN_RED CCI_REG16(0x0210) +#define IMX214_REG_DIG_GAIN_BLUE CCI_REG16(0x0212) +#define IMX214_REG_DIG_GAIN_GREENB CCI_REG16(0x0214) + +#define IMX214_REG_ORIENTATION CCI_REG8(0x0101) + +#define IMX214_REG_MASK_CORR_FRAMES CCI_REG8(0x0105) +#define IMX214_CORR_FRAMES_TRANSMIT 0 +#define IMX214_CORR_FRAMES_MASK 1 + +#define IMX214_REG_CSI_DATA_FORMAT CCI_REG16(0x0112) +#define IMX214_CSI_DATA_FORMAT_RAW8 0x0808 +#define IMX214_CSI_DATA_FORMAT_RAW10 0x0A0A +#define IMX214_CSI_DATA_FORMAT_COMP6 0x0A06 +#define IMX214_CSI_DATA_FORMAT_COMP8 0x0A08 + +#define IMX214_REG_CSI_LANE_MODE CCI_REG8(0x0114) +#define IMX214_CSI_2_LANE_MODE 1 +#define IMX214_CSI_4_LANE_MODE 3 + +#define IMX214_REG_EXCK_FREQ CCI_REG16(0x0136) +#define IMX214_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */ + +#define IMX214_REG_TEMP_SENSOR_CONTROL CCI_REG8(0x0138) + +#define IMX214_REG_HDR_MODE CCI_REG8(0x0220) +#define IMX214_HDR_MODE_OFF 0 +#define IMX214_HDR_MODE_ON 1 + +#define IMX214_REG_HDR_RES_REDUCTION CCI_REG8(0x0221) +#define IMX214_HDR_RES_REDU_THROUGH 0x11 +#define IMX214_HDR_RES_REDU_2_BINNING 0x22 + +/* PLL settings */ +#define IMX214_REG_VTPXCK_DIV CCI_REG8(0x0301) +#define IMX214_REG_VTSYCK_DIV CCI_REG8(0x0303) +#define IMX214_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305) +#define IMX214_REG_PLL_VT_MPY CCI_REG16(0x0306) +#define IMX214_REG_OPPXCK_DIV CCI_REG8(0x0309) +#define IMX214_REG_OPSYCK_DIV CCI_REG8(0x030b) +#define IMX214_REG_PLL_MULT_DRIV CCI_REG8(0x0310) +#define IMX214_PLL_SINGLE 0 +#define IMX214_PLL_DUAL 1 + +#define IMX214_REG_LINE_LENGTH_PCK CCI_REG16(0x0342) +#define IMX214_REG_X_ADD_STA CCI_REG16(0x0344) +#define IMX214_REG_Y_ADD_STA CCI_REG16(0x0346) +#define IMX214_REG_X_ADD_END CCI_REG16(0x0348) +#define IMX214_REG_Y_ADD_END CCI_REG16(0x034a) +#define IMX214_REG_X_OUTPUT_SIZE CCI_REG16(0x034c) +#define IMX214_REG_Y_OUTPUT_SIZE CCI_REG16(0x034e) +#define IMX214_REG_X_EVEN_INC CCI_REG8(0x0381) +#define IMX214_REG_X_ODD_INC CCI_REG8(0x0383) +#define IMX214_REG_Y_EVEN_INC CCI_REG8(0x0385) +#define IMX214_REG_Y_ODD_INC CCI_REG8(0x0387) + +#define IMX214_REG_SCALE_MODE CCI_REG8(0x0401) +#define IMX214_SCALE_NONE 0 +#define IMX214_SCALE_HORIZONTAL 1 +#define IMX214_SCALE_FULL 2 +#define IMX214_REG_SCALE_M CCI_REG16(0x0404) + +#define IMX214_REG_DIG_CROP_X_OFFSET CCI_REG16(0x0408) +#define IMX214_REG_DIG_CROP_Y_OFFSET CCI_REG16(0x040a) +#define IMX214_REG_DIG_CROP_WIDTH CCI_REG16(0x040c) +#define IMX214_REG_DIG_CROP_HEIGHT CCI_REG16(0x040e) + +#define IMX214_REG_REQ_LINK_BIT_RATE CCI_REG32(0x0820) +#define IMX214_LINK_BIT_RATE_MBPS(n) ((n) << 16) + +/* Binning mode */ +#define IMX214_REG_BINNING_MODE CCI_REG8(0x0900) +#define IMX214_BINNING_NONE 0 +#define IMX214_BINNING_ENABLE 1 +#define IMX214_REG_BINNING_TYPE CCI_REG8(0x0901) +#define IMX214_REG_BINNING_WEIGHTING CCI_REG8(0x0902) +#define IMX214_BINNING_AVERAGE 0x00 +#define IMX214_BINNING_SUMMED 0x01 +#define IMX214_BINNING_BAYER 0x02 + +#define IMX214_REG_SING_DEF_CORR_EN CCI_REG8(0x0b06) +#define IMX214_SING_DEF_CORR_OFF 0 +#define IMX214_SING_DEF_CORR_ON 1 + +/* AWB control */ +#define IMX214_REG_ABS_GAIN_GREENR CCI_REG16(0x0b8e) +#define IMX214_REG_ABS_GAIN_RED CCI_REG16(0x0b90) +#define IMX214_REG_ABS_GAIN_BLUE CCI_REG16(0x0b92) +#define IMX214_REG_ABS_GAIN_GREENB CCI_REG16(0x0b94) + +#define IMX214_REG_RMSC_NR_MODE CCI_REG8(0x3001) +#define IMX214_REG_STATS_OUT_EN CCI_REG8(0x3013) +#define IMX214_STATS_OUT_OFF 0 +#define IMX214_STATS_OUT_ON 1 + +/* Chroma noise reduction */ +#define IMX214_REG_NML_NR_EN CCI_REG8(0x30a2) +#define IMX214_NML_NR_OFF 0 +#define IMX214_NML_NR_ON 1 + +#define IMX214_REG_EBD_SIZE_V CCI_REG8(0x5041) +#define IMX214_EBD_NO 0 +#define IMX214_EBD_4_LINE 4 + +#define IMX214_REG_RG_STATS_LMT CCI_REG16(0x6d12) +#define IMX214_RG_STATS_LMT_10_BIT 0x03FF +#define IMX214_RG_STATS_LMT_14_BIT 0x3FFF + +#define IMX214_REG_ATR_FAST_MOVE CCI_REG8(0x9300) =20 /* IMX214 native and active pixel array size */ #define IMX214_NATIVE_WIDTH 4224U @@ -76,96 +199,70 @@ struct imx214 { =20 /*From imx214_mode_tbls.h*/ static const struct cci_reg_sequence mode_4096x2304[] =3D { - { CCI_REG8(0x0114), 0x03 }, - { CCI_REG8(0x0220), 0x00 }, - { CCI_REG8(0x0221), 0x11 }, - { CCI_REG8(0x0222), 0x01 }, - { CCI_REG8(0x0340), 0x0C }, - { CCI_REG8(0x0341), 0x7A }, - { CCI_REG8(0x0342), 0x13 }, - { CCI_REG8(0x0343), 0x90 }, - { CCI_REG8(0x0344), 0x00 }, - { CCI_REG8(0x0345), 0x38 }, - { CCI_REG8(0x0346), 0x01 }, - { CCI_REG8(0x0347), 0x98 }, - { CCI_REG8(0x0348), 0x10 }, - { CCI_REG8(0x0349), 0x37 }, - { CCI_REG8(0x034A), 0x0A }, - { CCI_REG8(0x034B), 0x97 }, - { CCI_REG8(0x0381), 0x01 }, - { CCI_REG8(0x0383), 0x01 }, - { CCI_REG8(0x0385), 0x01 }, - { CCI_REG8(0x0387), 0x01 }, - { CCI_REG8(0x0900), 0x00 }, - { CCI_REG8(0x0901), 0x00 }, - { CCI_REG8(0x0902), 0x00 }, + { IMX214_REG_CSI_LANE_MODE, IMX214_CSI_4_LANE_MODE }, + { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF }, + { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH }, + { IMX214_REG_EXPOSURE_RATIO, 1 }, + { IMX214_REG_FRM_LENGTH_LINES, 3194 }, + { IMX214_REG_LINE_LENGTH_PCK, 5008 }, + { IMX214_REG_X_ADD_STA, 56 }, + { IMX214_REG_Y_ADD_STA, 408 }, + { IMX214_REG_X_ADD_END, 4151 }, + { IMX214_REG_Y_ADD_END, 2711 }, + { IMX214_REG_X_EVEN_INC, 1 }, + { IMX214_REG_X_ODD_INC, 1 }, + { IMX214_REG_Y_EVEN_INC, 1 }, + { IMX214_REG_Y_ODD_INC, 1 }, + { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE }, + { IMX214_REG_BINNING_TYPE, 0 }, + { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE }, { CCI_REG8(0x3000), 0x35 }, { CCI_REG8(0x3054), 0x01 }, { CCI_REG8(0x305C), 0x11 }, =20 - { CCI_REG8(0x0112), 0x0A }, - { CCI_REG8(0x0113), 0x0A }, - { CCI_REG8(0x034C), 0x10 }, - { CCI_REG8(0x034D), 0x00 }, - { CCI_REG8(0x034E), 0x09 }, - { CCI_REG8(0x034F), 0x00 }, - { CCI_REG8(0x0401), 0x00 }, - { CCI_REG8(0x0404), 0x00 }, - { CCI_REG8(0x0405), 0x10 }, - { CCI_REG8(0x0408), 0x00 }, - { CCI_REG8(0x0409), 0x00 }, - { CCI_REG8(0x040A), 0x00 }, - { CCI_REG8(0x040B), 0x00 }, - { CCI_REG8(0x040C), 0x10 }, - { CCI_REG8(0x040D), 0x00 }, - { CCI_REG8(0x040E), 0x09 }, - { CCI_REG8(0x040F), 0x00 }, - - { CCI_REG8(0x0301), 0x05 }, - { CCI_REG8(0x0303), 0x02 }, - { CCI_REG8(0x0305), 0x03 }, - { CCI_REG8(0x0306), 0x00 }, - { CCI_REG8(0x0307), 0x96 }, - { CCI_REG8(0x0309), 0x0A }, - { CCI_REG8(0x030B), 0x01 }, - { CCI_REG8(0x0310), 0x00 }, - - { CCI_REG8(0x0820), 0x12 }, - { CCI_REG8(0x0821), 0xC0 }, - { CCI_REG8(0x0822), 0x00 }, - { CCI_REG8(0x0823), 0x00 }, + { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 }, + { IMX214_REG_X_OUTPUT_SIZE, 4096 }, + { IMX214_REG_Y_OUTPUT_SIZE, 2304 }, + { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE }, + { IMX214_REG_SCALE_M, 2 }, + { IMX214_REG_DIG_CROP_X_OFFSET, 0 }, + { IMX214_REG_DIG_CROP_Y_OFFSET, 0 }, + { IMX214_REG_DIG_CROP_WIDTH, 4096 }, + { IMX214_REG_DIG_CROP_HEIGHT, 2304 }, + + { IMX214_REG_VTPXCK_DIV, 5 }, + { IMX214_REG_VTSYCK_DIV, 2 }, + { IMX214_REG_PREPLLCK_VT_DIV, 3 }, + { IMX214_REG_PLL_VT_MPY, 150 }, + { IMX214_REG_OPPXCK_DIV, 10 }, + { IMX214_REG_OPSYCK_DIV, 1 }, + { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE }, + + { IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(4800) }, =20 { CCI_REG8(0x3A03), 0x09 }, { CCI_REG8(0x3A04), 0x50 }, { CCI_REG8(0x3A05), 0x01 }, =20 - { CCI_REG8(0x0B06), 0x01 }, - { CCI_REG8(0x30A2), 0x00 }, + { IMX214_REG_SING_DEF_CORR_EN, IMX214_SING_DEF_CORR_ON }, + { IMX214_REG_NML_NR_EN, IMX214_NML_NR_OFF }, =20 { CCI_REG8(0x30B4), 0x00 }, =20 { CCI_REG8(0x3A02), 0xFF }, =20 { CCI_REG8(0x3011), 0x00 }, - { CCI_REG8(0x3013), 0x01 }, - - { CCI_REG8(0x0202), 0x0C }, - { CCI_REG8(0x0203), 0x70 }, - { CCI_REG8(0x0224), 0x01 }, - { CCI_REG8(0x0225), 0xF4 }, - - { CCI_REG8(0x0204), 0x00 }, - { CCI_REG8(0x0205), 0x00 }, - { CCI_REG8(0x020E), 0x01 }, - { CCI_REG8(0x020F), 0x00 }, - { CCI_REG8(0x0210), 0x01 }, - { CCI_REG8(0x0211), 0x00 }, - { CCI_REG8(0x0212), 0x01 }, - { CCI_REG8(0x0213), 0x00 }, - { CCI_REG8(0x0214), 0x01 }, - { CCI_REG8(0x0215), 0x00 }, - { CCI_REG8(0x0216), 0x00 }, - { CCI_REG8(0x0217), 0x00 }, + { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON }, + + { IMX214_REG_EXPOSURE, IMX214_EXPOSURE_DEFAULT }, + { IMX214_REG_SHORT_EXPOSURE, 500 }, + + { IMX214_REG_ANALOG_GAIN, 0 }, + { IMX214_REG_DIG_GAIN_GREENR, 256 }, + { IMX214_REG_DIG_GAIN_RED, 256 }, + { IMX214_REG_DIG_GAIN_BLUE, 256 }, + { IMX214_REG_DIG_GAIN_GREENB, 256 }, + { IMX214_REG_SHORT_ANALOG_GAIN, 0 }, =20 { CCI_REG8(0x4170), 0x00 }, { CCI_REG8(0x4171), 0x10 }, @@ -176,96 +273,70 @@ static const struct cci_reg_sequence mode_4096x2304[]= =3D { }; =20 static const struct cci_reg_sequence mode_1920x1080[] =3D { - { CCI_REG8(0x0114), 0x03 }, - { CCI_REG8(0x0220), 0x00 }, - { CCI_REG8(0x0221), 0x11 }, - { CCI_REG8(0x0222), 0x01 }, - { CCI_REG8(0x0340), 0x0C }, - { CCI_REG8(0x0341), 0x7A }, - { CCI_REG8(0x0342), 0x13 }, - { CCI_REG8(0x0343), 0x90 }, - { CCI_REG8(0x0344), 0x04 }, - { CCI_REG8(0x0345), 0x78 }, - { CCI_REG8(0x0346), 0x03 }, - { CCI_REG8(0x0347), 0xFC }, - { CCI_REG8(0x0348), 0x0B }, - { CCI_REG8(0x0349), 0xF7 }, - { CCI_REG8(0x034A), 0x08 }, - { CCI_REG8(0x034B), 0x33 }, - { CCI_REG8(0x0381), 0x01 }, - { CCI_REG8(0x0383), 0x01 }, - { CCI_REG8(0x0385), 0x01 }, - { CCI_REG8(0x0387), 0x01 }, - { CCI_REG8(0x0900), 0x00 }, - { CCI_REG8(0x0901), 0x00 }, - { CCI_REG8(0x0902), 0x00 }, + { IMX214_REG_CSI_LANE_MODE, IMX214_CSI_4_LANE_MODE }, + { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF }, + { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH }, + { IMX214_REG_EXPOSURE_RATIO, 1 }, + { IMX214_REG_FRM_LENGTH_LINES, 3194 }, + { IMX214_REG_LINE_LENGTH_PCK, 5008 }, + { IMX214_REG_X_ADD_STA, 1144 }, + { IMX214_REG_Y_ADD_STA, 1020 }, + { IMX214_REG_X_ADD_END, 3063 }, + { IMX214_REG_Y_ADD_END, 2099 }, + { IMX214_REG_X_EVEN_INC, 1 }, + { IMX214_REG_X_ODD_INC, 1 }, + { IMX214_REG_Y_EVEN_INC, 1 }, + { IMX214_REG_Y_ODD_INC, 1 }, + { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE }, + { IMX214_REG_BINNING_TYPE, 0 }, + { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE }, { CCI_REG8(0x3000), 0x35 }, { CCI_REG8(0x3054), 0x01 }, { CCI_REG8(0x305C), 0x11 }, =20 - { CCI_REG8(0x0112), 0x0A }, - { CCI_REG8(0x0113), 0x0A }, - { CCI_REG8(0x034C), 0x07 }, - { CCI_REG8(0x034D), 0x80 }, - { CCI_REG8(0x034E), 0x04 }, - { CCI_REG8(0x034F), 0x38 }, - { CCI_REG8(0x0401), 0x00 }, - { CCI_REG8(0x0404), 0x00 }, - { CCI_REG8(0x0405), 0x10 }, - { CCI_REG8(0x0408), 0x00 }, - { CCI_REG8(0x0409), 0x00 }, - { CCI_REG8(0x040A), 0x00 }, - { CCI_REG8(0x040B), 0x00 }, - { CCI_REG8(0x040C), 0x07 }, - { CCI_REG8(0x040D), 0x80 }, - { CCI_REG8(0x040E), 0x04 }, - { CCI_REG8(0x040F), 0x38 }, - - { CCI_REG8(0x0301), 0x05 }, - { CCI_REG8(0x0303), 0x02 }, - { CCI_REG8(0x0305), 0x03 }, - { CCI_REG8(0x0306), 0x00 }, - { CCI_REG8(0x0307), 0x96 }, - { CCI_REG8(0x0309), 0x0A }, - { CCI_REG8(0x030B), 0x01 }, - { CCI_REG8(0x0310), 0x00 }, - - { CCI_REG8(0x0820), 0x12 }, - { CCI_REG8(0x0821), 0xC0 }, - { CCI_REG8(0x0822), 0x00 }, - { CCI_REG8(0x0823), 0x00 }, + { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 }, + { IMX214_REG_X_OUTPUT_SIZE, 1920 }, + { IMX214_REG_Y_OUTPUT_SIZE, 1080 }, + { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE }, + { IMX214_REG_SCALE_M, 2 }, + { IMX214_REG_DIG_CROP_X_OFFSET, 0 }, + { IMX214_REG_DIG_CROP_Y_OFFSET, 0 }, + { IMX214_REG_DIG_CROP_WIDTH, 1920 }, + { IMX214_REG_DIG_CROP_HEIGHT, 1080 }, + + { IMX214_REG_VTPXCK_DIV, 5 }, + { IMX214_REG_VTSYCK_DIV, 2 }, + { IMX214_REG_PREPLLCK_VT_DIV, 3 }, + { IMX214_REG_PLL_VT_MPY, 150 }, + { IMX214_REG_OPPXCK_DIV, 10 }, + { IMX214_REG_OPSYCK_DIV, 1 }, + { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE }, + + { IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(4800) }, =20 { CCI_REG8(0x3A03), 0x04 }, { CCI_REG8(0x3A04), 0xF8 }, { CCI_REG8(0x3A05), 0x02 }, =20 - { CCI_REG8(0x0B06), 0x01 }, - { CCI_REG8(0x30A2), 0x00 }, + { IMX214_REG_SING_DEF_CORR_EN, IMX214_SING_DEF_CORR_ON }, + { IMX214_REG_NML_NR_EN, IMX214_NML_NR_OFF }, =20 { CCI_REG8(0x30B4), 0x00 }, =20 { CCI_REG8(0x3A02), 0xFF }, =20 { CCI_REG8(0x3011), 0x00 }, - { CCI_REG8(0x3013), 0x01 }, - - { CCI_REG8(0x0202), 0x0C }, - { CCI_REG8(0x0203), 0x70 }, - { CCI_REG8(0x0224), 0x01 }, - { CCI_REG8(0x0225), 0xF4 }, - - { CCI_REG8(0x0204), 0x00 }, - { CCI_REG8(0x0205), 0x00 }, - { CCI_REG8(0x020E), 0x01 }, - { CCI_REG8(0x020F), 0x00 }, - { CCI_REG8(0x0210), 0x01 }, - { CCI_REG8(0x0211), 0x00 }, - { CCI_REG8(0x0212), 0x01 }, - { CCI_REG8(0x0213), 0x00 }, - { CCI_REG8(0x0214), 0x01 }, - { CCI_REG8(0x0215), 0x00 }, - { CCI_REG8(0x0216), 0x00 }, - { CCI_REG8(0x0217), 0x00 }, + { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON }, + + { IMX214_REG_EXPOSURE, IMX214_EXPOSURE_DEFAULT }, + { IMX214_REG_SHORT_EXPOSURE, 500 }, + + { IMX214_REG_ANALOG_GAIN, 0 }, + { IMX214_REG_DIG_GAIN_GREENR, 256 }, + { IMX214_REG_DIG_GAIN_RED, 256 }, + { IMX214_REG_DIG_GAIN_BLUE, 256 }, + { IMX214_REG_DIG_GAIN_GREENB, 256 }, + { IMX214_REG_SHORT_ANALOG_GAIN, 0 }, =20 { CCI_REG8(0x4170), 0x00 }, { CCI_REG8(0x4171), 0x10 }, @@ -279,20 +350,19 @@ static const struct cci_reg_sequence mode_table_commo= n[] =3D { /* software reset */ =20 /* software standby settings */ - { CCI_REG8(0x0100), 0x00 }, + { IMX214_REG_MODE_SELECT, IMX214_MODE_STANDBY }, =20 /* ATR setting */ - { CCI_REG8(0x9300), 0x02 }, + { IMX214_REG_ATR_FAST_MOVE, 2 }, =20 /* external clock setting */ - { CCI_REG8(0x0136), 0x18 }, - { CCI_REG8(0x0137), 0x00 }, + { IMX214_REG_EXCK_FREQ, IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 100000= 0) }, =20 /* global setting */ /* basic config */ - { CCI_REG8(0x0101), 0x00 }, - { CCI_REG8(0x0105), 0x01 }, - { CCI_REG8(0x0106), 0x01 }, + { IMX214_REG_ORIENTATION, 0 }, + { IMX214_REG_MASK_CORR_FRAMES, IMX214_CORR_FRAMES_MASK }, + { IMX214_REG_FAST_STANDBY_CTRL, 1 }, { CCI_REG8(0x4550), 0x02 }, { CCI_REG8(0x4601), 0x00 }, { CCI_REG8(0x4642), 0x05 }, @@ -337,18 +407,17 @@ static const struct cci_reg_sequence mode_table_commo= n[] =3D { { CCI_REG8(0x4A87), 0xFF }, =20 /* embedded data */ - { CCI_REG8(0x5041), 0x04 }, + { IMX214_REG_EBD_SIZE_V, IMX214_EBD_4_LINE }, { CCI_REG8(0x583C), 0x04 }, { CCI_REG8(0x620E), 0x04 }, { CCI_REG8(0x6EB2), 0x01 }, { CCI_REG8(0x6EB3), 0x00 }, - { CCI_REG8(0x9300), 0x02 }, + { IMX214_REG_ATR_FAST_MOVE, 2 }, =20 /* imagequality */ /* HDR setting */ - { CCI_REG8(0x3001), 0x07 }, - { CCI_REG8(0x6D12), 0x3F }, - { CCI_REG8(0x6D13), 0xFF }, + { IMX214_REG_RMSC_NR_MODE, 0x07 }, + { IMX214_REG_RG_STATS_LMT, IMX214_RG_STATS_LMT_14_BIT }, { CCI_REG8(0x9344), 0x03 }, { CCI_REG8(0x9706), 0x10 }, { CCI_REG8(0x9707), 0x03 }, @@ -376,14 +445,10 @@ static const struct cci_reg_sequence mode_table_commo= n[] =3D { { CCI_REG8(0x698B), 0x03 }, =20 /* white balanace */ - { CCI_REG8(0x0B8E), 0x01 }, - { CCI_REG8(0x0B8F), 0x00 }, - { CCI_REG8(0x0B90), 0x01 }, - { CCI_REG8(0x0B91), 0x00 }, - { CCI_REG8(0x0B92), 0x01 }, - { CCI_REG8(0x0B93), 0x00 }, - { CCI_REG8(0x0B94), 0x01 }, - { CCI_REG8(0x0B95), 0x00 }, + { IMX214_REG_ABS_GAIN_GREENR, 0x0100 }, + { IMX214_REG_ABS_GAIN_RED, 0x0100 }, + { IMX214_REG_ABS_GAIN_BLUE, 0x0100 }, + { IMX214_REG_ABS_GAIN_GREENB, 0x0100 }, =20 /* ATR setting */ { CCI_REG8(0x6E50), 0x00 }, @@ -737,7 +802,7 @@ static int imx214_start_streaming(struct imx214 *imx214) =20 usleep_range(10000, 10500); =20 - cci_write(imx214->regmap, CCI_REG8(0x0138), 0x01, NULL); + cci_write(imx214->regmap, IMX214_REG_TEMP_SENSOR_CONTROL, 0x01, NULL); =20 ret =3D __v4l2_ctrl_handler_setup(&imx214->ctrls); if (ret < 0) { --=20 2.47.0 From nobody Tue Nov 26 06:40:30 2024 Received: from smtp.kernel.org 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IiV4LJDzQ04Tni3MAMqh5J83MryQolRkDxskz2pKdnt5Cxh24X1HsC15W34eXCi0Gi Uo8gm2xYQSHjdF6M6ENpBcgCpoJFiKGC0DdpcE88RzwEizJ/qV5pegwUbvfKCj4QH9 0Ho0vGyF7Ihaxghs2q+U4ItDt96pYzrHi/5usCTjsQdGWhonIxve1m7BuIUhkTVLFa 2Vn7hdnN+Show== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEB37D3C92D; Sun, 20 Oct 2024 22:14:11 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Mon, 21 Oct 2024 00:13:26 +0200 Subject: [PATCH v2 06/13] media: i2c: imx214: Drop IMX214_REG_EXPOSURE from mode reg arrays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-6-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= , Ricardo Ribalda X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=1197; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=0XA/1Uf+hc8+yHy+Gkzx2R9DneNOd4QyEdjlnWihHQ4=; b=KHipMYMeEviwOtMui1x5f2V3j78qegTZ93VjWBbXHeqSJJlepzmY4buo7HDWifSxSqTYtto2x NYy+mVezsDcAIOV+uhJdKoBi2oMg+YeLzXPE0eSC2f17ycknZPTopbA X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch The IMX214_REG_EXPOSURE is configured twice, once with a hardcoded value in the mode_ registers arrays, and once via v4l2_ctrl_ops. The latter is enough, drop the former. Acked-by: Ricardo Ribalda Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 49beba5807c5dd84109fe90b745de0484d01390c..0c83149bcc3e3b833a087d26104= eb7dfaafdf904 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -254,7 +254,6 @@ static const struct cci_reg_sequence mode_4096x2304[] = =3D { { CCI_REG8(0x3011), 0x00 }, { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON }, =20 - { IMX214_REG_EXPOSURE, IMX214_EXPOSURE_DEFAULT }, { IMX214_REG_SHORT_EXPOSURE, 500 }, =20 { IMX214_REG_ANALOG_GAIN, 0 }, @@ -328,7 +327,6 @@ static const struct cci_reg_sequence mode_1920x1080[] = =3D { { CCI_REG8(0x3011), 0x00 }, { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON }, =20 - { IMX214_REG_EXPOSURE, IMX214_EXPOSURE_DEFAULT }, { IMX214_REG_SHORT_EXPOSURE, 500 }, =20 { IMX214_REG_ANALOG_GAIN, 0 }, --=20 2.47.0 From nobody Tue Nov 26 06:40:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 996631991AF; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; cv=none; b=k3P3l06hoKxxRSnlM047UAsreW7yVHcI6NYt24w2pUAsqIzvElzd3vwMvHyVsM2WrSdezzResV1ppSRq0zoCG590SODyVnyNz2HhYOit/w+X3z6R9wZbUdvVobiSCZc2llUyzlXFCreJJgbTcLjehdb1Q1ulvsgYObAX3VK/c6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; c=relaxed/simple; bh=z6YUXTxQxOlJqtYBRZspT//oAQ1nWbbRO1Qm40xIS2M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V9AYSu11nmaP0cpW/949hYYce+NyK+JslmOX4kwaOss7xcT+uedjThH3poa0cIUm7FFa2M3E42C1i50HZoqTKPKALEkyepPTZcErQfjVmy5g1LPRiRWbl6/ukFHihn5Kw0l1lX/Z/byYu4GjFxYQ9byqrMRLoylLoVqDRR21WLU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Nj3/vHV4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Nj3/vHV4" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0B01FC4CEF1; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729462452; bh=z6YUXTxQxOlJqtYBRZspT//oAQ1nWbbRO1Qm40xIS2M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Nj3/vHV4Av+mKboN9yskiN6Z+60B+GAKNFajFTtL4Jsh69cY6LUifnYpALZ/0niBO ir69/YyO5+kb09CQ8rqRFlfegqeU509Ys+CsedrAQZ5nsR0GT3sti7lau+q/Crhz1o U0PYflOUOqXDU49KNZvmp109xICOfxl0ahhwQPQLpu2nO/bycJDtwh2JLME4d5fYL/ t21Fi0nc50fn/YQbOpHzxBjlaHpnOvwg+fgN9OEga3sf+GxFycwp/rzuth4+E8CU75 BfRek8hollQre1m7AQ+3bS8BdWlv6x9c5Tnsj8HjX2/4YfCpJXgzaTycJ6vBHBe89o 3XJL+R0hV9wUQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F4028D3C937; Sun, 20 Oct 2024 22:14:11 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Mon, 21 Oct 2024 00:13:27 +0200 Subject: [PATCH v2 07/13] media: i2c: imx214: Check number of lanes from device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-7-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=2978; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=CBPDBnfB8DBiUcxll9P6I0H8kikZ+GlZj0ctfGMDhYE=; b=jJZEoSUE6ANmxYOiJY/K5XDWKlD6rnS7nx3pzhUZBzNWr6EKC6V6d4FkfE7d1WKz+VFhvqOo6 RlkNKt27XWoAbQReJr9vxbMQw7/IXvcB3HfjMfE4yH1Pxh50Bks/w39 X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch The imx214 camera is capable of either two-lane or four-lane operation. Currently only the four-lane mode is supported, as proper pixel rates and link frequences for the two-lane mode are unknown. Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 0c83149bcc3e3b833a087d26104eb7dfaafdf904..497baad616ad7374a92a3da2b7c= 1096b1d72a0c7 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -199,7 +199,6 @@ struct imx214 { =20 /*From imx214_mode_tbls.h*/ static const struct cci_reg_sequence mode_4096x2304[] =3D { - { IMX214_REG_CSI_LANE_MODE, IMX214_CSI_4_LANE_MODE }, { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF }, { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH }, { IMX214_REG_EXPOSURE_RATIO, 1 }, @@ -272,7 +271,6 @@ static const struct cci_reg_sequence mode_4096x2304[] = =3D { }; =20 static const struct cci_reg_sequence mode_1920x1080[] =3D { - { IMX214_REG_CSI_LANE_MODE, IMX214_CSI_4_LANE_MODE }, { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF }, { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH }, { IMX214_REG_EXPOSURE_RATIO, 1 }, @@ -791,6 +789,13 @@ static int imx214_start_streaming(struct imx214 *imx21= 4) return ret; } =20 + ret =3D cci_write(imx214->regmap, IMX214_REG_CSI_LANE_MODE, + IMX214_CSI_4_LANE_MODE, NULL); + if (ret) { + dev_err(imx214->dev, "%s failed to configure lanes\n", __func__); + return ret; + } + ret =3D cci_multi_reg_write(imx214->regmap, imx214->cur_mode->reg_table, imx214->cur_mode->num_of_regs, NULL); if (ret < 0) { @@ -932,7 +937,7 @@ static int imx214_get_regulators(struct device *dev, st= ruct imx214 *imx214) imx214->supplies); } =20 -static int imx214_parse_fwnode(struct device *dev) +static int imx214_parse_fwnode(struct device *dev, struct imx214 *imx214) { struct fwnode_handle *endpoint; struct v4l2_fwnode_endpoint bus_cfg =3D { @@ -951,6 +956,13 @@ static int imx214_parse_fwnode(struct device *dev) goto done; } =20 + /* Check the number of MIPI CSI2 data lanes */ + if (bus_cfg.bus.mipi_csi2.num_data_lanes !=3D 4) { + dev_err_probe(dev, -EINVAL, + "only 4 data lanes are currently supported\n"); + goto done; + } + for (i =3D 0; i < bus_cfg.nr_of_link_frequencies; i++) if (bus_cfg.link_frequencies[i] =3D=3D IMX214_DEFAULT_LINK_FREQ) break; @@ -975,14 +987,14 @@ static int imx214_probe(struct i2c_client *client) struct imx214 *imx214; int ret; =20 - ret =3D imx214_parse_fwnode(dev); - if (ret) - return ret; - imx214 =3D devm_kzalloc(dev, sizeof(*imx214), GFP_KERNEL); if (!imx214) return -ENOMEM; =20 + ret =3D imx214_parse_fwnode(dev, imx214); + if (ret) + return ret; + imx214->dev =3D dev; =20 imx214->xclk =3D devm_clk_get(dev, NULL); --=20 2.47.0 From nobody Tue Nov 26 06:40:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 995DC1991AE; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; cv=none; b=Sf0EW0JyQlizHC1PFS7CtcvwSJX2vPMCMmPtba5h9by9iipG2Mt5wywRnH247Z/5M3JXVJGvY6MLG2yMC7PPrVw2hDVwwCH6Y+AybywdANIF5Q0OA1J8Zyt2gGNLLr/+dIvnz0pXZ9YcLyin2rh981XdCbJ9I2Ocfh0pILn2Cu4= ARC-Message-Signature: i=1; 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b=kYW1APf5kRkKk7FWrXBNxl19Ym94fR0114z5Zn3qf/tFAls5cjmULT987eshH4bYp hK4l/thOOZAZ+Swr8y2gxlFwoKHHCriKGaXQFnBPJXSGVdkbkKSXppA+E2KWAGAsHc KQ50aRWwkC6/oZPPJmQ+0zRBKFRMjGBqKBcRqP/BElnGktHia8tOD0NlVpcP0VD2of EejUWCNVqO4Uw/TY3QBGu7oqONCUHJpbP9G3p12+E1t2faeu+0eSLazmPbe9QLFo/1 P8fT7oyvPnte9DV9Z806VPGuPHp2Rbk8bNtle54FJn0vLfQxH0iYvClYWELUs7/Xvm NvbiQ7dQhTMMw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D7EED3C930; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Mon, 21 Oct 2024 00:13:28 +0200 Subject: [PATCH v2 08/13] media: i2c: imx214: Add vblank and hblank controls Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-8-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=8667; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=RplBzbTpfNes4EIKFHGO0oVof5BqK3Mdu/t1OsfqH3o=; b=CJecofuZ1CLuS+5bfWeF1TNhUaPvj7MiteElO5m8rGnrv2i+S8qy92lxo5vws0CIoRuH+me+z Agdqk0XgaglC8Dx+txqhXTvcvecle5L7i81VAVD624pEUJosoW+Jglt X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch Add vblank control to allow changing the framerate / higher exposure values. The vblank and hblank controls are needed for libcamera support. While at it, fix the minimal exposure time according to the datasheet. Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 119 ++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 97 insertions(+), 22 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 497baad616ad7374a92a3da2b7c1096b1d72a0c7..cb443d8bee6fe72dc9378b2c2d3= caae09f8642c5 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -34,11 +34,18 @@ =20 /* V-TIMING internal */ #define IMX214_REG_FRM_LENGTH_LINES CCI_REG16(0x0340) +#define IMX214_VTS_MAX 0xffff + +#define IMX214_VBLANK_MIN 890 + +/* HBLANK control - read only */ +#define IMX214_PPL_DEFAULT 5008 =20 /* Exposure control */ #define IMX214_REG_EXPOSURE CCI_REG16(0x0202) -#define IMX214_EXPOSURE_MIN 0 -#define IMX214_EXPOSURE_MAX 3184 +#define IMX214_EXPOSURE_OFFSET 10 +#define IMX214_EXPOSURE_MIN 1 +#define IMX214_EXPOSURE_MAX (IMX214_VTS_MAX - IMX214_EXPOSURE_OFFSET) #define IMX214_EXPOSURE_STEP 1 #define IMX214_EXPOSURE_DEFAULT 3184 #define IMX214_REG_EXPOSURE_RATIO CCI_REG8(0x0222) @@ -187,6 +194,8 @@ struct imx214 { struct v4l2_ctrl_handler ctrls; struct v4l2_ctrl *pixel_rate; struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *hblank; struct v4l2_ctrl *exposure; struct v4l2_ctrl *unit_size; =20 @@ -202,8 +211,6 @@ static const struct cci_reg_sequence mode_4096x2304[] = =3D { { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF }, { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH }, { IMX214_REG_EXPOSURE_RATIO, 1 }, - { IMX214_REG_FRM_LENGTH_LINES, 3194 }, - { IMX214_REG_LINE_LENGTH_PCK, 5008 }, { IMX214_REG_X_ADD_STA, 56 }, { IMX214_REG_Y_ADD_STA, 408 }, { IMX214_REG_X_ADD_END, 4151 }, @@ -274,8 +281,6 @@ static const struct cci_reg_sequence mode_1920x1080[] = =3D { { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF }, { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH }, { IMX214_REG_EXPOSURE_RATIO, 1 }, - { IMX214_REG_FRM_LENGTH_LINES, 3194 }, - { IMX214_REG_LINE_LENGTH_PCK, 5008 }, { IMX214_REG_X_ADD_STA, 1144 }, { IMX214_REG_Y_ADD_STA, 1020 }, { IMX214_REG_X_ADD_END, 3063 }, @@ -359,6 +364,7 @@ static const struct cci_reg_sequence mode_table_common[= ] =3D { { IMX214_REG_ORIENTATION, 0 }, { IMX214_REG_MASK_CORR_FRAMES, IMX214_CORR_FRAMES_MASK }, { IMX214_REG_FAST_STANDBY_CTRL, 1 }, + { IMX214_REG_LINE_LENGTH_PCK, IMX214_PPL_DEFAULT }, { CCI_REG8(0x4550), 0x02 }, { CCI_REG8(0x4601), 0x00 }, { CCI_REG8(0x4642), 0x05 }, @@ -462,18 +468,24 @@ static const struct cci_reg_sequence mode_table_commo= n[] =3D { static const struct imx214_mode { u32 width; u32 height; + + /* V-timing */ + unsigned int vts_def; + unsigned int num_of_regs; const struct cci_reg_sequence *reg_table; } imx214_modes[] =3D { { .width =3D 4096, .height =3D 2304, + .vts_def =3D 3194, .num_of_regs =3D ARRAY_SIZE(mode_4096x2304), .reg_table =3D mode_4096x2304, }, { .width =3D 1920, .height =3D 1080, + .vts_def =3D 3194, .num_of_regs =3D ARRAY_SIZE(mode_1920x1080), .reg_table =3D mode_1920x1080, }, @@ -629,9 +641,39 @@ static int imx214_set_format(struct v4l2_subdev *sd, __crop->width =3D mode->width; __crop->height =3D mode->height; =20 - if (format->which =3D=3D V4L2_SUBDEV_FORMAT_ACTIVE) + if (format->which =3D=3D V4L2_SUBDEV_FORMAT_ACTIVE) { + int exposure_max; + int exposure_def; + int hblank; + imx214->cur_mode =3D mode; =20 + /* Update limits and set FPS to default */ + __v4l2_ctrl_modify_range(imx214->vblank, IMX214_VBLANK_MIN, + IMX214_VTS_MAX - mode->height, 2, + mode->vts_def - mode->height); + __v4l2_ctrl_s_ctrl(imx214->vblank, + mode->vts_def - mode->height); + + /* Update max exposure while meeting expected vblanking */ + exposure_max =3D mode->vts_def - IMX214_EXPOSURE_OFFSET; + exposure_def =3D (exposure_max < IMX214_EXPOSURE_DEFAULT) ? + exposure_max : IMX214_EXPOSURE_DEFAULT; + __v4l2_ctrl_modify_range(imx214->exposure, + imx214->exposure->minimum, + exposure_max, imx214->exposure->step, + exposure_def); + + /* + * Currently PPL is fixed to IMX214_PPL_DEFAULT, so hblank + * depends on mode->width only, and is not changeble in any + * way other than changing the mode. + */ + hblank =3D IMX214_PPL_DEFAULT - mode->width; + __v4l2_ctrl_modify_range(imx214->hblank, hblank, hblank, 1, + hblank); + } + return 0; } =20 @@ -681,8 +723,25 @@ static int imx214_set_ctrl(struct v4l2_ctrl *ctrl) { struct imx214 *imx214 =3D container_of(ctrl->handler, struct imx214, ctrls); + const struct v4l2_mbus_framefmt *format; + struct v4l2_subdev_state *state; int ret; =20 + state =3D v4l2_subdev_get_locked_active_state(&imx214->sd); + format =3D v4l2_subdev_state_get_format(state, 0); + + if (ctrl->id =3D=3D V4L2_CID_VBLANK) { + int exposure_max, exposure_def; + + /* Update max exposure while meeting expected vblanking */ + exposure_max =3D format->height + ctrl->val - IMX214_EXPOSURE_OFFSET; + exposure_def =3D min(exposure_max, IMX214_EXPOSURE_DEFAULT); + __v4l2_ctrl_modify_range(imx214->exposure, + imx214->exposure->minimum, + exposure_max, imx214->exposure->step, + exposure_def); + } + /* * Applying V4L2 control value only happens * when power is up for streaming @@ -694,7 +753,10 @@ static int imx214_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_EXPOSURE: cci_write(imx214->regmap, IMX214_REG_EXPOSURE, ctrl->val, &ret); break; - + case V4L2_CID_VBLANK: + cci_write(imx214->regmap, IMX214_REG_FRM_LENGTH_LINES, + format->height + ctrl->val, &ret); + break; default: ret =3D -EINVAL; } @@ -717,8 +779,11 @@ static int imx214_ctrls_init(struct imx214 *imx214) .width =3D 1120, .height =3D 1120, }; + const struct imx214_mode *mode =3D &imx214_modes[0]; struct v4l2_fwnode_device_properties props; struct v4l2_ctrl_handler *ctrl_hdlr; + int exposure_max, exposure_def; + int hblank; int ret; =20 ret =3D v4l2_fwnode_device_parse(imx214->dev, &props); @@ -726,7 +791,7 @@ static int imx214_ctrls_init(struct imx214 *imx214) return ret; =20 ctrl_hdlr =3D &imx214->ctrls; - ret =3D v4l2_ctrl_handler_init(&imx214->ctrls, 6); + ret =3D v4l2_ctrl_handler_init(&imx214->ctrls, 8); if (ret) return ret; =20 @@ -742,22 +807,26 @@ static int imx214_ctrls_init(struct imx214 *imx214) if (imx214->link_freq) imx214->link_freq->flags |=3D V4L2_CTRL_FLAG_READ_ONLY; =20 - /* - * WARNING! - * Values obtained reverse engineering blobs and/or devices. - * Ranges and functionality might be wrong. - * - * Sony, please release some register set documentation for the - * device. - * - * Yours sincerely, Ricardo. - */ + /* Initial vblank/hblank/exposure parameters based on current mode */ + imx214->vblank =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, + V4L2_CID_VBLANK, IMX214_VBLANK_MIN, + IMX214_VTS_MAX - mode->height, 2, + mode->vts_def - mode->height); + + hblank =3D IMX214_PPL_DEFAULT - mode->width; + imx214->hblank =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, + V4L2_CID_HBLANK, hblank, hblank, + 1, hblank); + if (imx214->hblank) + imx214->hblank->flags |=3D V4L2_CTRL_FLAG_READ_ONLY; + + exposure_max =3D mode->vts_def - IMX214_EXPOSURE_OFFSET; + exposure_def =3D min(exposure_max, IMX214_EXPOSURE_DEFAULT); imx214->exposure =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, V4L2_CID_EXPOSURE, - IMX214_EXPOSURE_MIN, - IMX214_EXPOSURE_MAX, + IMX214_EXPOSURE_MIN, exposure_max, IMX214_EXPOSURE_STEP, - IMX214_EXPOSURE_DEFAULT); + exposure_def); =20 imx214->unit_size =3D v4l2_ctrl_new_std_compound(ctrl_hdlr, NULL, @@ -879,6 +948,12 @@ static int imx214_get_frame_interval(struct v4l2_subde= v *subdev, return 0; } =20 +/* + * Raw sensors should be using the VBLANK and HBLANK controls to determine + * the frame rate. However this driver was initially added using the + * [S|G|ENUM]_FRAME_INTERVAL ioctls with a fixed rate of 30fps. + * Retain the frame_interval ops for backwards compatibility, but they do = nothing. + */ static int imx214_enum_frame_interval(struct v4l2_subdev *subdev, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_interval_enum *fie) --=20 2.47.0 From nobody Tue Nov 26 06:40:31 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADFA71991BE; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; cv=none; b=nJhzlEh6c5ZOaqEn5k2iJKMV9ogXTrRCp70zMZ6LfL20/QHVCIpg25ZxtZjo02Y6X/iBa80cPRjOT+v2r5K78S3hxJsds94vWYZWqIbZX7QOPDNvpBqO3dtxV9ZKUHODTQ83OtY76DMLx7DQgUNRxai9hB2exZw9iQ8Ub/9hTmw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; c=relaxed/simple; bh=yk0ClJZp0r8exg54uJLYZ+QTLVTk1fuu+8aNLiSCesA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lpryWpyV0U7QU1SPTp8/g3FJMWo2tfeED60aykiHynzWyHj9gH+aF6CWhM9xVKdG659noPAhNOwVQt8wo1ORYJzZBNDmgfynm4PcBr0N/Niy2VyrafP1ZGOBiRvtCJNYSUPM7SbeFX6T1Dohh1Ib79ruqu/fVXrbi5uNpzT9aHw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XUTjSpVy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XUTjSpVy" Received: by smtp.kernel.org (Postfix) with ESMTPS id 27151C4CEF7; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729462452; bh=yk0ClJZp0r8exg54uJLYZ+QTLVTk1fuu+8aNLiSCesA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XUTjSpVyFHAg0KwGLYhCR0y5HgDukFcl/CA+pBxzHbhf8Mzk0GSi7ETkaWk4znbDa VP2wrBSYWzngAckJHmlMezfG9VMMjknoeJfavx/quZUCGqYC8Xm2BHeN0d4CYV069v YwW+CSAjAzwjh0K31dt8qnic4YWwllf3Vjnrdvzk9ryRfOMEqCt1tDNKFAKrEa9KNl FYr13DFAuwIkLYEJdgMgjoKGMGgwW8uDhKcGAMgPaLtPN4oe8pISyJ9zo20m7yffQj n7AMN9SDtl4hx+ukgweJqkSQhKZ9SkzYATn7DdAOcq1v0nbVWFQ/CGf7ZDPA2pPn5R tuQif4xO/k4DA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BC9FD3C938; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Mon, 21 Oct 2024 00:13:29 +0200 Subject: [PATCH v2 09/13] media: i2c: imx214: Extract format and crop settings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-9-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=8252; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=p6Xt8IYTKhjGLY7+IsD6FSf18HwHfmecuRaNE4HBLGo=; b=c231zhCszMGcLxejHIBpb8PUy+apsdIsRncJWUXpJa7kgv3g94A1ttBXcqYfmktjOTWGXA4nd fFnHqnj3xPjD8W4W3pR0JDrStgxAg7KLR5LDG2oRW8c79dvN9qzp7BY X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch Remove format and crop settings from register sequences and set them programmatically. Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 129 ++++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 97 insertions(+), 32 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index cb443d8bee6fe72dc9378b2c2d3caae09f8642c5..87a03e292e19ccd71f1b2dcee34= 09826b2f5cb6f 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -96,6 +96,9 @@ #define IMX214_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305) #define IMX214_REG_PLL_VT_MPY CCI_REG16(0x0306) #define IMX214_REG_OPPXCK_DIV CCI_REG8(0x0309) +#define IMX214_OPPXCK_DIV_COMP6 6 +#define IMX214_OPPXCK_DIV_COMP8 8 +#define IMX214_OPPXCK_DIV_RAW10 10 #define IMX214_REG_OPSYCK_DIV CCI_REG8(0x030b) #define IMX214_REG_PLL_MULT_DRIV CCI_REG8(0x0310) #define IMX214_PLL_SINGLE 0 @@ -132,6 +135,9 @@ #define IMX214_BINNING_NONE 0 #define IMX214_BINNING_ENABLE 1 #define IMX214_REG_BINNING_TYPE CCI_REG8(0x0901) +#define IMX214_BINNING_1X1 0 +#define IMX214_BINNING_2X2 0x22 +#define IMX214_BINNING_4X4 0x44 #define IMX214_REG_BINNING_WEIGHTING CCI_REG8(0x0902) #define IMX214_BINNING_AVERAGE 0x00 #define IMX214_BINNING_SUMMED 0x01 @@ -211,36 +217,22 @@ static const struct cci_reg_sequence mode_4096x2304[]= =3D { { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF }, { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH }, { IMX214_REG_EXPOSURE_RATIO, 1 }, - { IMX214_REG_X_ADD_STA, 56 }, - { IMX214_REG_Y_ADD_STA, 408 }, - { IMX214_REG_X_ADD_END, 4151 }, - { IMX214_REG_Y_ADD_END, 2711 }, { IMX214_REG_X_EVEN_INC, 1 }, { IMX214_REG_X_ODD_INC, 1 }, { IMX214_REG_Y_EVEN_INC, 1 }, { IMX214_REG_Y_ODD_INC, 1 }, - { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE }, - { IMX214_REG_BINNING_TYPE, 0 }, { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE }, { CCI_REG8(0x3000), 0x35 }, { CCI_REG8(0x3054), 0x01 }, { CCI_REG8(0x305C), 0x11 }, =20 - { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 }, - { IMX214_REG_X_OUTPUT_SIZE, 4096 }, - { IMX214_REG_Y_OUTPUT_SIZE, 2304 }, { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE }, { IMX214_REG_SCALE_M, 2 }, - { IMX214_REG_DIG_CROP_X_OFFSET, 0 }, - { IMX214_REG_DIG_CROP_Y_OFFSET, 0 }, - { IMX214_REG_DIG_CROP_WIDTH, 4096 }, - { IMX214_REG_DIG_CROP_HEIGHT, 2304 }, =20 { IMX214_REG_VTPXCK_DIV, 5 }, { IMX214_REG_VTSYCK_DIV, 2 }, { IMX214_REG_PREPLLCK_VT_DIV, 3 }, { IMX214_REG_PLL_VT_MPY, 150 }, - { IMX214_REG_OPPXCK_DIV, 10 }, { IMX214_REG_OPSYCK_DIV, 1 }, { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE }, =20 @@ -281,36 +273,22 @@ static const struct cci_reg_sequence mode_1920x1080[]= =3D { { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF }, { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH }, { IMX214_REG_EXPOSURE_RATIO, 1 }, - { IMX214_REG_X_ADD_STA, 1144 }, - { IMX214_REG_Y_ADD_STA, 1020 }, - { IMX214_REG_X_ADD_END, 3063 }, - { IMX214_REG_Y_ADD_END, 2099 }, { IMX214_REG_X_EVEN_INC, 1 }, { IMX214_REG_X_ODD_INC, 1 }, { IMX214_REG_Y_EVEN_INC, 1 }, { IMX214_REG_Y_ODD_INC, 1 }, - { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE }, - { IMX214_REG_BINNING_TYPE, 0 }, { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE }, { CCI_REG8(0x3000), 0x35 }, { CCI_REG8(0x3054), 0x01 }, { CCI_REG8(0x305C), 0x11 }, =20 - { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 }, - { IMX214_REG_X_OUTPUT_SIZE, 1920 }, - { IMX214_REG_Y_OUTPUT_SIZE, 1080 }, { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE }, { IMX214_REG_SCALE_M, 2 }, - { IMX214_REG_DIG_CROP_X_OFFSET, 0 }, - { IMX214_REG_DIG_CROP_Y_OFFSET, 0 }, - { IMX214_REG_DIG_CROP_WIDTH, 1920 }, - { IMX214_REG_DIG_CROP_HEIGHT, 1080 }, =20 { IMX214_REG_VTPXCK_DIV, 5 }, { IMX214_REG_VTSYCK_DIV, 2 }, { IMX214_REG_PREPLLCK_VT_DIV, 3 }, { IMX214_REG_PLL_VT_MPY, 150 }, - { IMX214_REG_OPPXCK_DIV, 10 }, { IMX214_REG_OPSYCK_DIV, 1 }, { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE }, =20 @@ -623,6 +601,7 @@ static int imx214_set_format(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *__format; struct v4l2_rect *__crop; const struct imx214_mode *mode; + unsigned int bin_h, bin_v, bin; =20 mode =3D v4l2_find_nearest_size(imx214_modes, ARRAY_SIZE(imx214_modes), width, height, @@ -637,9 +616,32 @@ static int imx214_set_format(struct v4l2_subdev *sd, =20 *__format =3D format->format; =20 + /* + * Use binning to maximize the crop rectangle size, and centre it in the + * sensor. + */ + bin_h =3D IMX214_PIXEL_ARRAY_WIDTH / __format->width; + bin_v =3D IMX214_PIXEL_ARRAY_HEIGHT / __format->height; + + switch (min(bin_h, bin_v)) { + case 1: + bin =3D 1; + break; + case 2: + case 3: + bin =3D 2; + break; + case 4: + default: + bin =3D 4; + break; + } + __crop =3D v4l2_subdev_state_get_crop(sd_state, 0); - __crop->width =3D mode->width; - __crop->height =3D mode->height; + __crop->width =3D __format->width * bin; + __crop->height =3D __format->height * bin; + __crop->left =3D (IMX214_NATIVE_WIDTH - __crop->width) / 2; + __crop->top =3D (IMX214_NATIVE_HEIGHT - __crop->height) / 2; =20 if (format->which =3D=3D V4L2_SUBDEV_FORMAT_ACTIVE) { int exposure_max; @@ -847,7 +849,62 @@ static int imx214_ctrls_init(struct imx214 *imx214) return 0; }; =20 -static int imx214_start_streaming(struct imx214 *imx214) +static int imx214_set_framefmt(struct imx214 *imx214, + struct v4l2_subdev_state *state) +{ + const struct v4l2_mbus_framefmt *format; + const struct v4l2_rect *crop; + u64 bin_mode; + u64 bin_type; + int ret =3D 0; + + format =3D v4l2_subdev_state_get_format(state, 0); + crop =3D v4l2_subdev_state_get_crop(state, 0); + + cci_write(imx214->regmap, IMX214_REG_X_ADD_STA, + crop->left - IMX214_PIXEL_ARRAY_LEFT, &ret); + cci_write(imx214->regmap, IMX214_REG_X_ADD_END, + crop->left - IMX214_PIXEL_ARRAY_LEFT + crop->width - 1, &ret); + cci_write(imx214->regmap, IMX214_REG_Y_ADD_STA, + crop->top - IMX214_PIXEL_ARRAY_TOP, &ret); + cci_write(imx214->regmap, IMX214_REG_Y_ADD_END, + crop->top - IMX214_PIXEL_ARRAY_TOP + crop->height - 1, &ret); + + /* Proper setting is required even if cropping is not used */ + cci_write(imx214->regmap, IMX214_REG_DIG_CROP_WIDTH, crop->width, &ret); + cci_write(imx214->regmap, IMX214_REG_DIG_CROP_HEIGHT, crop->height, &ret); + + switch (crop->width / format->width) { + case 1: + default: + bin_mode =3D IMX214_BINNING_NONE; + bin_type =3D IMX214_BINNING_1X1; + break; + case 2: + bin_mode =3D IMX214_BINNING_ENABLE; + bin_type =3D IMX214_BINNING_2X2; + break; + case 4: + bin_mode =3D IMX214_BINNING_ENABLE; + bin_type =3D IMX214_BINNING_4X4; + break; + } + + cci_write(imx214->regmap, IMX214_REG_BINNING_MODE, bin_mode, &ret); + cci_write(imx214->regmap, IMX214_REG_BINNING_TYPE, bin_type, &ret); + + cci_write(imx214->regmap, IMX214_REG_X_OUTPUT_SIZE, format->width, &ret); + cci_write(imx214->regmap, IMX214_REG_Y_OUTPUT_SIZE, format->height, &ret); + + cci_write(imx214->regmap, IMX214_REG_CSI_DATA_FORMAT, + IMX214_CSI_DATA_FORMAT_RAW10, &ret); + cci_write(imx214->regmap, IMX214_REG_OPPXCK_DIV, IMX214_OPPXCK_DIV_RAW10,= &ret); + + return ret; +}; + +static int imx214_start_streaming(struct imx214 *imx214, + struct v4l2_subdev_state *state) { int ret; =20 @@ -865,6 +922,14 @@ static int imx214_start_streaming(struct imx214 *imx21= 4) return ret; } =20 + /* Apply format and crop settings */ + ret =3D imx214_set_framefmt(imx214, state); + if (ret) { + dev_err(imx214->dev, "%s failed to set frame format: %d\n", + __func__, ret); + return ret; + } + ret =3D cci_multi_reg_write(imx214->regmap, imx214->cur_mode->reg_table, imx214->cur_mode->num_of_regs, NULL); if (ret < 0) { @@ -913,7 +978,7 @@ static int imx214_s_stream(struct v4l2_subdev *subdev, = int enable) return ret; =20 state =3D v4l2_subdev_lock_and_get_active_state(subdev); - ret =3D imx214_start_streaming(imx214); + ret =3D imx214_start_streaming(imx214, state); v4l2_subdev_unlock_state(state); if (ret < 0) goto err_rpm_put; --=20 2.47.0 From nobody Tue Nov 26 06:40:31 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE0181991C1; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FNLrexUE" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3665EC4CEFA; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729462452; bh=PweRBHEo5QtIKPF4uuLIiad5fmqzbffeOgUoyOKTttc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=FNLrexUEkqoUy4yqzDfM8XW9IjK3cKbbXh14viLoIp1myK7VLZD1B0W6rIQ12dATF oRPCD97UZYJ3xj2IjjTN6VXr0DhH6JO9MnUWN2yVph5+VX1BuuPFphnnXXQsl83pp0 KS2LCrKOZFgOyH/qCAqFeEX5lz9oH08H6K+B1GJDw+Ddtg30p1AVSnee0RPhUlefrp +CGzRk5pd8WSo8tmrDe7/gZtPODnoF/lEk69hTOCcrKeAqCbvo3AukywOvNUl+jbof DUl6o0k04Q6jz4m+z5HrJYBy4sen54AEXBmSHxO96VMizAF6t7Gh4/HLlveUD6hupG 9aMkrLPS2UBVw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BECCD3C935; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Mon, 21 Oct 2024 00:13:30 +0200 Subject: [PATCH v2 10/13] media: i2c: imx214: Implement vflip/hflip controls Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-10-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=5924; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=TWO/BcgBISCxxfC2d/H2lS3pg23/eXAtD4hde4yNOUg=; b=VKW+2eRwG/GMMUQs/0xAhlF4DokAu+i51bhgreO5G30/zABCwSbGAcJ7ekxAPxkMVkDK+DDal GFhpIi2fMsdAMyN4INfjBbAAu/vyzIcJbT/UAjcgT/rZKrXNTCyPY2E X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch The imx214 sensor supports horizontal and vertical flipping. Add appropriate controls to the driver. Signed-off-by: Andr=C3=A9 Apitzsch Acked-by: Ricardo Ribalda --- drivers/media/i2c/imx214.c | 69 ++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 61 insertions(+), 8 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 87a03e292e19ccd71f1b2dcee3409826b2f5cb6f..f2d21c2e8cf84ed25403c98e280= 073f32e50e758 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -30,7 +30,6 @@ #define IMX214_DEFAULT_LINK_FREQ 600000000 #define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10) #define IMX214_FPS 30 -#define IMX214_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10 =20 /* V-TIMING internal */ #define IMX214_REG_FRM_LENGTH_LINES CCI_REG16(0x0340) @@ -189,6 +188,22 @@ static const char * const imx214_supply_name[] =3D { =20 #define IMX214_NUM_SUPPLIES ARRAY_SIZE(imx214_supply_name) =20 +/* + * The supported formats. + * This table MUST contain 4 entries per format, to cover the various flip + * combinations in the order + * - no flip + * - h flip + * - v flip + * - h&v flips + */ +static const u32 imx214_mbus_formats[] =3D { + MEDIA_BUS_FMT_SRGGB10_1X10, + MEDIA_BUS_FMT_SGRBG10_1X10, + MEDIA_BUS_FMT_SGBRG10_1X10, + MEDIA_BUS_FMT_SBGGR10_1X10, +}; + struct imx214 { struct device *dev; struct clk *xclk; @@ -204,6 +219,10 @@ struct imx214 { struct v4l2_ctrl *hblank; struct v4l2_ctrl *exposure; struct v4l2_ctrl *unit_size; + struct { + struct v4l2_ctrl *hflip; + struct v4l2_ctrl *vflip; + }; =20 const struct imx214_mode *cur_mode; =20 @@ -339,7 +358,6 @@ static const struct cci_reg_sequence mode_table_common[= ] =3D { =20 /* global setting */ /* basic config */ - { IMX214_REG_ORIENTATION, 0 }, { IMX214_REG_MASK_CORR_FRAMES, IMX214_CORR_FRAMES_MASK }, { IMX214_REG_FAST_STANDBY_CTRL, 1 }, { IMX214_REG_LINE_LENGTH_PCK, IMX214_PPL_DEFAULT }, @@ -518,11 +536,21 @@ static int __maybe_unused imx214_power_off(struct dev= ice *dev) return 0; } =20 +/* Get bayer order based on flip setting. */ +static u32 imx214_get_format_code(struct imx214 *imx214) +{ + unsigned int i; + + i =3D (imx214->vflip->val ? 2 : 0) | (imx214->hflip->val ? 1 : 0); + + return imx214_mbus_formats[i]; +} + static void imx214_update_pad_format(struct imx214 *imx214, const struct imx214_mode *mode, struct v4l2_mbus_framefmt *fmt, u32 code) { - fmt->code =3D IMX214_MBUS_CODE; + fmt->code =3D imx214_get_format_code(imx214); fmt->width =3D mode->width; fmt->height =3D mode->height; fmt->field =3D V4L2_FIELD_NONE; @@ -538,10 +566,12 @@ static int imx214_enum_mbus_code(struct v4l2_subdev *= sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { - if (code->index > 0) + struct imx214 *imx214 =3D to_imx214(sd); + + if (code->index >=3D (ARRAY_SIZE(imx214_mbus_formats) / 4)) return -EINVAL; =20 - code->code =3D IMX214_MBUS_CODE; + code->code =3D imx214_get_format_code(imx214); =20 return 0; } @@ -550,7 +580,11 @@ static int imx214_enum_frame_size(struct v4l2_subdev *= subdev, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse) { - if (fse->code !=3D IMX214_MBUS_CODE) + struct imx214 *imx214 =3D to_imx214(subdev); + u32 code; + + code =3D imx214_get_format_code(imx214); + if (fse->code !=3D code) return -EINVAL; =20 if (fse->index >=3D ARRAY_SIZE(imx214_modes)) @@ -713,6 +747,7 @@ static int imx214_entity_init_state(struct v4l2_subdev = *subdev, struct v4l2_subdev_format fmt =3D { }; =20 fmt.which =3D sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTI= VE; + fmt.format.code =3D MEDIA_BUS_FMT_SRGGB10_1X10; fmt.format.width =3D imx214_modes[0].width; fmt.format.height =3D imx214_modes[0].height; =20 @@ -755,6 +790,11 @@ static int imx214_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_EXPOSURE: cci_write(imx214->regmap, IMX214_REG_EXPOSURE, ctrl->val, &ret); break; + case V4L2_CID_HFLIP: + case V4L2_CID_VFLIP: + cci_write(imx214->regmap, IMX214_REG_ORIENTATION, + imx214->hflip->val | imx214->vflip->val << 1, &ret); + break; case V4L2_CID_VBLANK: cci_write(imx214->regmap, IMX214_REG_FRM_LENGTH_LINES, format->height + ctrl->val, &ret); @@ -793,7 +833,7 @@ static int imx214_ctrls_init(struct imx214 *imx214) return ret; =20 ctrl_hdlr =3D &imx214->ctrls; - ret =3D v4l2_ctrl_handler_init(&imx214->ctrls, 8); + ret =3D v4l2_ctrl_handler_init(&imx214->ctrls, 10); if (ret) return ret; =20 @@ -830,6 +870,18 @@ static int imx214_ctrls_init(struct imx214 *imx214) IMX214_EXPOSURE_STEP, exposure_def); =20 + imx214->hflip =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + if (imx214->hflip) + imx214->hflip->flags |=3D V4L2_CTRL_FLAG_MODIFY_LAYOUT; + + imx214->vflip =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + if (imx214->vflip) + imx214->vflip->flags |=3D V4L2_CTRL_FLAG_MODIFY_LAYOUT; + + v4l2_ctrl_cluster(2, &imx214->hflip); + imx214->unit_size =3D v4l2_ctrl_new_std_compound(ctrl_hdlr, NULL, V4L2_CID_UNIT_CELL_SIZE, @@ -1023,6 +1075,7 @@ static int imx214_enum_frame_interval(struct v4l2_sub= dev *subdev, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_interval_enum *fie) { + struct imx214 *imx214 =3D to_imx214(subdev); const struct imx214_mode *mode; =20 if (fie->index !=3D 0) @@ -1032,7 +1085,7 @@ static int imx214_enum_frame_interval(struct v4l2_sub= dev *subdev, ARRAY_SIZE(imx214_modes), width, height, fie->width, fie->height); =20 - fie->code =3D IMX214_MBUS_CODE; + fie->code =3D imx214_get_format_code(imx214); fie->width =3D mode->width; fie->height =3D mode->height; fie->interval.numerator =3D 1; --=20 2.47.0 From nobody Tue Nov 26 06:40:31 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFA6B1991C6; Sun, 20 Oct 2024 22:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; cv=none; b=ek+Ef6E8WijmPeHARA+VxjCjJaI+eNkE8h73zfpiM9zQ2roTUfDLckLaVAodyC3sk8LMR3RvqNyrTgGXQciuC7sfN8TamiFzExnvfThobrB3ooOfs7DtPqctBKNKsGll6I4qMKulqMIOFl4OGHF9DhEJD3jThXOZ3I2lsEWMEJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729462452; c=relaxed/simple; bh=71QPmlZCbZanm+0hrX+C+CLoss9GpN+DnnoqT8310lE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Sun, 20 Oct 2024 22:14:12 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Mon, 21 Oct 2024 00:13:31 +0200 Subject: [PATCH v2 11/13] media: i2c: imx214: Add analogue/digital gain control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-11-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= , Ricardo Ribalda X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=4360; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=rXL1g7Oe8YzuPPhYACw/Jy36nnaFTf5MQS8SSUXbNRE=; b=WXzI6ca0GpCmGXV5kfd81sVpwBwcxO20nmSYMpCVzCYDlSMqSE99G519iO0kdYJTqvNoBcrlz +3B7Ev4qk4rBGIiATX+S+xa2f/eZgvQvJONCJhC8YpRWxdoSt2aI+Mi X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch The imx214 sensor supports analogue gain up to 8x and digital gain up to 16x. Implement the corresponding controls in the driver. Default gain values are not modified by this patch. Acked-by: Ricardo Ribalda Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 53 +++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 38 insertions(+), 15 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index f2d21c2e8cf84ed25403c98e280073f32e50e758..ad1f88057ac47ae0d494d7a1052= 0fabf969315ed 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -53,12 +53,20 @@ /* Analog gain control */ #define IMX214_REG_ANALOG_GAIN CCI_REG16(0x0204) #define IMX214_REG_SHORT_ANALOG_GAIN CCI_REG16(0x0216) +#define IMX214_ANA_GAIN_MIN 0 +#define IMX214_ANA_GAIN_MAX 448 +#define IMX214_ANA_GAIN_STEP 1 +#define IMX214_ANA_GAIN_DEFAULT 0x0 =20 /* Digital gain control */ #define IMX214_REG_DIG_GAIN_GREENR CCI_REG16(0x020e) #define IMX214_REG_DIG_GAIN_RED CCI_REG16(0x0210) #define IMX214_REG_DIG_GAIN_BLUE CCI_REG16(0x0212) #define IMX214_REG_DIG_GAIN_GREENB CCI_REG16(0x0214) +#define IMX214_DGTL_GAIN_MIN 0x0100 +#define IMX214_DGTL_GAIN_MAX 0x0fff +#define IMX214_DGTL_GAIN_DEFAULT 0x0100 +#define IMX214_DGTL_GAIN_STEP 1 =20 #define IMX214_REG_ORIENTATION CCI_REG8(0x0101) =20 @@ -273,13 +281,6 @@ static const struct cci_reg_sequence mode_4096x2304[] = =3D { =20 { IMX214_REG_SHORT_EXPOSURE, 500 }, =20 - { IMX214_REG_ANALOG_GAIN, 0 }, - { IMX214_REG_DIG_GAIN_GREENR, 256 }, - { IMX214_REG_DIG_GAIN_RED, 256 }, - { IMX214_REG_DIG_GAIN_BLUE, 256 }, - { IMX214_REG_DIG_GAIN_GREENB, 256 }, - { IMX214_REG_SHORT_ANALOG_GAIN, 0 }, - { CCI_REG8(0x4170), 0x00 }, { CCI_REG8(0x4171), 0x10 }, { CCI_REG8(0x4176), 0x00 }, @@ -329,13 +330,6 @@ static const struct cci_reg_sequence mode_1920x1080[] = =3D { =20 { IMX214_REG_SHORT_EXPOSURE, 500 }, =20 - { IMX214_REG_ANALOG_GAIN, 0 }, - { IMX214_REG_DIG_GAIN_GREENR, 256 }, - { IMX214_REG_DIG_GAIN_RED, 256 }, - { IMX214_REG_DIG_GAIN_BLUE, 256 }, - { IMX214_REG_DIG_GAIN_GREENB, 256 }, - { IMX214_REG_SHORT_ANALOG_GAIN, 0 }, - { CCI_REG8(0x4170), 0x00 }, { CCI_REG8(0x4171), 0x10 }, { CCI_REG8(0x4176), 0x00 }, @@ -756,6 +750,18 @@ static int imx214_entity_init_state(struct v4l2_subdev= *subdev, return 0; } =20 +static int imx214_update_digital_gain(struct imx214 *imx214, u32 val) +{ + int ret =3D 0; + + cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_GREENR, val, &ret); + cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_RED, val, &ret); + cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_BLUE, val, &ret); + cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_GREENB, val, &ret); + + return ret; +} + static int imx214_set_ctrl(struct v4l2_ctrl *ctrl) { struct imx214 *imx214 =3D container_of(ctrl->handler, @@ -787,6 +793,15 @@ static int imx214_set_ctrl(struct v4l2_ctrl *ctrl) return 0; =20 switch (ctrl->id) { + case V4L2_CID_ANALOGUE_GAIN: + cci_write(imx214->regmap, IMX214_REG_ANALOG_GAIN, + ctrl->val, &ret); + cci_write(imx214->regmap, IMX214_REG_SHORT_ANALOG_GAIN, + ctrl->val, &ret); + break; + case V4L2_CID_DIGITAL_GAIN: + ret =3D imx214_update_digital_gain(imx214, ctrl->val); + break; case V4L2_CID_EXPOSURE: cci_write(imx214->regmap, IMX214_REG_EXPOSURE, ctrl->val, &ret); break; @@ -833,7 +848,7 @@ static int imx214_ctrls_init(struct imx214 *imx214) return ret; =20 ctrl_hdlr =3D &imx214->ctrls; - ret =3D v4l2_ctrl_handler_init(&imx214->ctrls, 10); + ret =3D v4l2_ctrl_handler_init(&imx214->ctrls, 12); if (ret) return ret; =20 @@ -870,6 +885,14 @@ static int imx214_ctrls_init(struct imx214 *imx214) IMX214_EXPOSURE_STEP, exposure_def); =20 + v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + IMX214_ANA_GAIN_MIN, IMX214_ANA_GAIN_MAX, + IMX214_ANA_GAIN_STEP, IMX214_ANA_GAIN_DEFAULT); + + v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, V4L2_CID_DIGITAL_GAIN, + IMX214_DGTL_GAIN_MIN, IMX214_DGTL_GAIN_MAX, + IMX214_DGTL_GAIN_STEP, IMX214_DGTL_GAIN_DEFAULT); + imx214->hflip =3D v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0); if (imx214->hflip) --=20 2.47.0 From nobody Tue Nov 26 06:40:31 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 911D21990DE; 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Acked-by: Ricardo Ribalda Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index ad1f88057ac47ae0d494d7a10520fabf969315ed..46f3e27371d8075517a75891e6a= 742912c2a3604 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -20,6 +20,10 @@ #include #include =20 +/* Chip ID */ +#define IMX214_REG_CHIP_ID CCI_REG16(0x0016) +#define IMX214_CHIP_ID 0x0214 + #define IMX214_REG_MODE_SELECT CCI_REG8(0x0100) #define IMX214_MODE_STANDBY 0x00 #define IMX214_MODE_STREAMING 0x01 @@ -1153,6 +1157,27 @@ static int imx214_get_regulators(struct device *dev,= struct imx214 *imx214) imx214->supplies); } =20 +/* Verify chip ID */ +static int imx214_identify_module(struct imx214 *imx214) +{ + struct i2c_client *client =3D v4l2_get_subdevdata(&imx214->sd); + int ret; + u64 val; + + ret =3D cci_read(imx214->regmap, IMX214_REG_CHIP_ID, &val, NULL); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241021-imx214-v2-13-fbd23e99541e@apitzsch.eu> References: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> In-Reply-To: <20241021-imx214-v2-0-fbd23e99541e@apitzsch.eu> To: Ricardo Ribalda , Mauro Carvalho Chehab , Sakari Ailus Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Stevenson , =?utf-8?q?Andr=C3=A9_Apitzsch?= , Ricardo Ribalda X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729462449; l=4254; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=Ycuv3mccDEUrqsrrRYMMgnDXXWQgzfPBCnvvdHtarng=; b=bI5djwgEKIrSxryBacux+T5CBYrRX/3hNryn31sxQI1+EwJXGIWJDKBdMgJpMH4kYelxOgast ncT0/+Sm/xQAjW+vzk7FFQ1kqgGUsfNy/SRDxCEIYN4XrzV3p37q4KZ X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch This adds V4L2_CID_TEST_PATTERN control support. Acked-by: Ricardo Ribalda Signed-off-by: Andr=C3=A9 Apitzsch --- drivers/media/i2c/imx214.c | 77 ++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 75 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 46f3e27371d8075517a75891e6a742912c2a3604..2aca3d88a0a7fa9b870090f1083= b31b0c3c84652 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -184,6 +184,23 @@ =20 #define IMX214_REG_ATR_FAST_MOVE CCI_REG8(0x9300) =20 +/* Test Pattern Control */ +#define IMX214_REG_TEST_PATTERN CCI_REG16(0x0600) +#define IMX214_TEST_PATTERN_DISABLE 0 +#define IMX214_TEST_PATTERN_SOLID_COLOR 1 +#define IMX214_TEST_PATTERN_COLOR_BARS 2 +#define IMX214_TEST_PATTERN_GREY_COLOR 3 +#define IMX214_TEST_PATTERN_PN9 4 + +/* Test pattern colour components */ +#define IMX214_REG_TESTP_RED CCI_REG16(0x0602) +#define IMX214_REG_TESTP_GREENR CCI_REG16(0x0604) +#define IMX214_REG_TESTP_BLUE CCI_REG16(0x0606) +#define IMX214_REG_TESTP_GREENB CCI_REG16(0x0608) +#define IMX214_TESTP_COLOUR_MIN 0 +#define IMX214_TESTP_COLOUR_MAX 0x03ff +#define IMX214_TESTP_COLOUR_STEP 1 + /* IMX214 native and active pixel array size */ #define IMX214_NATIVE_WIDTH 4224U #define IMX214_NATIVE_HEIGHT 3136U @@ -216,6 +233,22 @@ static const u32 imx214_mbus_formats[] =3D { MEDIA_BUS_FMT_SBGGR10_1X10, }; =20 +static const char * const imx214_test_pattern_menu[] =3D { + "Disabled", + "Color Bars", + "Solid Color", + "Grey Color Bars", + "PN9" +}; + +static const int imx214_test_pattern_val[] =3D { + IMX214_TEST_PATTERN_DISABLE, + IMX214_TEST_PATTERN_COLOR_BARS, + IMX214_TEST_PATTERN_SOLID_COLOR, + IMX214_TEST_PATTERN_GREY_COLOR, + IMX214_TEST_PATTERN_PN9, +}; + struct imx214 { struct device *dev; struct clk *xclk; @@ -818,6 +851,26 @@ static int imx214_set_ctrl(struct v4l2_ctrl *ctrl) cci_write(imx214->regmap, IMX214_REG_FRM_LENGTH_LINES, format->height + ctrl->val, &ret); break; + case V4L2_CID_TEST_PATTERN: + cci_write(imx214->regmap, IMX214_REG_TEST_PATTERN, + imx214_test_pattern_val[ctrl->val], &ret); + break; + case V4L2_CID_TEST_PATTERN_RED: + cci_write(imx214->regmap, IMX214_REG_TESTP_RED, + ctrl->val, &ret); + break; + case V4L2_CID_TEST_PATTERN_GREENR: + cci_write(imx214->regmap, IMX214_REG_TESTP_GREENR, + ctrl->val, &ret); + break; + case V4L2_CID_TEST_PATTERN_BLUE: + cci_write(imx214->regmap, IMX214_REG_TESTP_BLUE, + ctrl->val, &ret); + break; + case V4L2_CID_TEST_PATTERN_GREENB: + cci_write(imx214->regmap, IMX214_REG_TESTP_GREENB, + ctrl->val, &ret); + break; default: ret =3D -EINVAL; } @@ -845,14 +898,14 @@ static int imx214_ctrls_init(struct imx214 *imx214) struct v4l2_ctrl_handler *ctrl_hdlr; int exposure_max, exposure_def; int hblank; - int ret; + int i, ret; =20 ret =3D v4l2_fwnode_device_parse(imx214->dev, &props); if (ret < 0) return ret; =20 ctrl_hdlr =3D &imx214->ctrls; - ret =3D v4l2_ctrl_handler_init(&imx214->ctrls, 12); + ret =3D v4l2_ctrl_handler_init(&imx214->ctrls, 13); if (ret) return ret; =20 @@ -909,6 +962,26 @@ static int imx214_ctrls_init(struct imx214 *imx214) =20 v4l2_ctrl_cluster(2, &imx214->hflip); =20 + v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx214_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(imx214_test_pattern_menu) - 1, + 0, 0, imx214_test_pattern_menu); + for (i =3D 0; i < 4; i++) { + /* + * The assumption is that + * V4L2_CID_TEST_PATTERN_GREENR =3D=3D V4L2_CID_TEST_PATTERN_RED + 1 + * V4L2_CID_TEST_PATTERN_BLUE =3D=3D V4L2_CID_TEST_PATTERN_RED + 2 + * V4L2_CID_TEST_PATTERN_GREENB =3D=3D V4L2_CID_TEST_PATTERN_RED + 3 + */ + v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, + V4L2_CID_TEST_PATTERN_RED + i, + IMX214_TESTP_COLOUR_MIN, + IMX214_TESTP_COLOUR_MAX, + IMX214_TESTP_COLOUR_STEP, + IMX214_TESTP_COLOUR_MAX); + /* The "Solid color" pattern is white by default */ + } + imx214->unit_size =3D v4l2_ctrl_new_std_compound(ctrl_hdlr, NULL, V4L2_CID_UNIT_CELL_SIZE, --=20 2.47.0