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charset="utf-8" Save trap CSRs in the kvm_riscv_vcpu_enter_exit() function instead of the kvm_arch_vcpu_ioctl_run() function so that HTVAL and HTINST CSRs are accessed in more optimized manner while running under some other hypervisor. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/kvm/vcpu.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index e191e6eae0c0..e048dcc6e65e 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -768,12 +768,21 @@ static __always_inline void kvm_riscv_vcpu_swap_in_ho= st_state(struct kvm_vcpu *v * This must be noinstr as instrumentation may make use of RCU, and this i= s not * safe during the EQS. */ -static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu) +static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu, + struct kvm_cpu_trap *trap) { void *nsh; struct kvm_cpu_context *gcntx =3D &vcpu->arch.guest_context; struct kvm_cpu_context *hcntx =3D &vcpu->arch.host_context; =20 + /* + * We save trap CSRs (such as SEPC, SCAUSE, STVAL, HTVAL, and + * HTINST) here because we do local_irq_enable() after this + * function in kvm_arch_vcpu_ioctl_run() which can result in + * an interrupt immediately after local_irq_enable() and can + * potentially change trap CSRs. + */ + kvm_riscv_vcpu_swap_in_guest_state(vcpu); guest_state_enter_irqoff(); =20 @@ -816,14 +825,24 @@ static void noinstr kvm_riscv_vcpu_enter_exit(struct = kvm_vcpu *vcpu) } else { gcntx->hstatus =3D csr_swap(CSR_HSTATUS, hcntx->hstatus); } + + trap->htval =3D nacl_csr_read(nsh, CSR_HTVAL); + trap->htinst =3D nacl_csr_read(nsh, CSR_HTINST); } else { hcntx->hstatus =3D csr_swap(CSR_HSTATUS, gcntx->hstatus); =20 __kvm_riscv_switch_to(&vcpu->arch); =20 gcntx->hstatus =3D csr_swap(CSR_HSTATUS, hcntx->hstatus); + + trap->htval =3D csr_read(CSR_HTVAL); + trap->htinst =3D csr_read(CSR_HTINST); } =20 + trap->sepc =3D gcntx->sepc; + trap->scause =3D csr_read(CSR_SCAUSE); + trap->stval =3D csr_read(CSR_STVAL); + vcpu->arch.last_exit_cpu =3D vcpu->cpu; guest_state_exit_irqoff(); kvm_riscv_vcpu_swap_in_host_state(vcpu); @@ -940,22 +959,11 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) =20 guest_timing_enter_irqoff(); =20 - kvm_riscv_vcpu_enter_exit(vcpu); + kvm_riscv_vcpu_enter_exit(vcpu, &trap); =20 vcpu->mode =3D OUTSIDE_GUEST_MODE; vcpu->stat.exits++; =20 - /* - * Save SCAUSE, STVAL, HTVAL, and HTINST because we might - * get an interrupt between __kvm_riscv_switch_to() and - * local_irq_enable() which can potentially change CSRs. - */ - trap.sepc =3D vcpu->arch.guest_context.sepc; - trap.scause =3D csr_read(CSR_SCAUSE); - trap.stval =3D csr_read(CSR_STVAL); - trap.htval =3D ncsr_read(CSR_HTVAL); - trap.htinst =3D ncsr_read(CSR_HTINST); - /* Syncup interrupts state with HW */ kvm_riscv_vcpu_sync_interrupts(vcpu); =20 --=20 2.43.0