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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:42 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 08/23] ARM: dts: socfpga: add clock-frequency property Date: Sun, 20 Oct 2024 19:40:13 +0000 Message-Id: <20241020194028.2272371-9-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add 'clock-frequency' is a required property by dtschema. Initialization is open, similar to agilex devices. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 65d04339f..5f4bed187 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -99,21 +99,25 @@ clocks { cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 f2s_free_clk: f2s_free_clk { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 osc1: osc1 { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 main_pll: main_pll@40 { --=20 2.25.1