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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:39 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 06/23] ARM: dts: socfpga: add missing cells properties Date: Sun, 20 Oct 2024 19:40:11 +0000 Message-Id: <20241020194028.2272371-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Binding requires size-cells and address-cells to be around for the SRAM. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 7f7ac0dc1..4b19fad1e 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -684,6 +684,8 @@ nand: nand-controller@ffb90000 { =20 ocram: sram@ffe00000 { compatible =3D "mmio-sram"; + #address-cells =3D <1>; + #size-cells =3D <1>; reg =3D <0xffe00000 0x40000>; }; =20 --=20 2.25.1