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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:30 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 01/23] ARM: dts: socfpga: fix typo Date: Sun, 20 Oct 2024 19:40:06 +0000 Message-Id: <20241020194028.2272371-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A semicolon was fallen off the wall. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 6b6e77596..7113fe5b5 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -169,8 +169,7 @@ main_gpio_db_clk: main_gpio_db_clk@74 { =20 main_sdmmc_clk: main_sdmmc_clk@78 { #clock-cells =3D <0>; - compatible =3D "altr,socfpga-a10-perip-clk" -; + compatible =3D "altr,socfpga-a10-perip-clk"; clocks =3D <&main_pll>; reg =3D <0x78>; }; --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD03F1957FD; Sun, 20 Oct 2024 19:40:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453236; cv=none; b=BT6Dti6LzLS375DY8E8JxZcPCfJOamG/jkv0o8Fw+h8qU3a2NJkcEKZhYpcoAQUmR9845sqDpNYv2oqGDeOEMMISU3M9WmgSNwvcY1Fyc6YPGLs6pQfUgqepsgxctOV0bn189IWxpUwduBMqAzyl7qsej1HydjaLB8bOwsYEoLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453236; c=relaxed/simple; bh=McMTyWzS0Bg4WFWkM4x5Eq6n8AM1vXInQ676orlwBs8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WUOzklbS39ZOOMFV92KVaHK9nLB7AvproVR5Sg+MoCs/Nio37jGpqiaK1R3z4if1DyK4SMHRDnGh3wzYmPb31NtWiQWxQI1xb+X4GDS3Z4P8aS1aBZDmQObomALx8rXVTq/2GvQRsJjcsfVeMNQcBWLNnj3A5Tu958N7AFld1rk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DYjabbB2; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DYjabbB2" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a9a68480e3eso25260966b.1; Sun, 20 Oct 2024 12:40:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453233; x=1730058033; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a7BTF2QgV5p9nNttdJyKFEUTkRzHJB1L1AnxAUE0mKw=; b=DYjabbB2j5c+Vdrwq7qD9DYAK/9ZiwJ2LcHV+clSTzOX4r9pzqoZldgEc8zr4cma6/ iMAr1eGUYjcccQ4mvO1zCZ4CCUVVEPJXi4yQMzYovVW6AZiMDkfi8SLoe6cO704BOSKn rVgRxZQRWsQQMXNE3AlH6m9FgiyLXn7L4SzWawAaMoGVoEvOY0ThlKPbFovTNWTpBPNs g413bLetTUjZ8nDI/A4jXrzyrvOYSLntg27xaTxjrV6O9P6EFPHVYZNhoRE1GwlyIoJL 9rS9CvvpEyIhbejADGfr9IisNTb6ZgPTQzLAzRFZcQ00rdj3uCLZ2yHcyZBBC0ZI1HCg aqeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453233; x=1730058033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a7BTF2QgV5p9nNttdJyKFEUTkRzHJB1L1AnxAUE0mKw=; b=rC5AARXce2DyLBP53nG1OHgK6fhQiSbqptGNasD6eEvdB2q8JpBx7u8lc8UwMxzUzE hyFWhmleFEsBkyDi8zu/JWIyl3r5cpnlNNNzqdbBxW0iVSaHkLXgXxnBsOVNI3wq1PEG HNIn8WtQ4Ux5h9QKZl7bDgu1LL+MbkN9phF8uShoIkO9DTuNae3K8ISnoiq0gQT+Zt6u NBjrZrv8RpaVjNgIeNuXK+vcA23LJXuh0T0hIvc4qSnmrf582VO5Xy7UscL83RSJU/Du OnrNgCAjghWHn7QaVJymbgGqhSNcjqBcy+lTOr0PMr9AnyYeXYQhslqmDly5UkAW+nn0 2ICg== X-Forwarded-Encrypted: i=1; AJvYcCU/mduWYDKkhX2H5fNaXAjHJmO/ghbM/T6Rmp6cYXoRJN7ZUHFFljW+asYpttjGHfdR/wyY6GtbQD9mv75j@vger.kernel.org, AJvYcCWji4Y4C7JNYeCgpm5MeUHEsMvaVTe7ObQyvluvSgafz9t53MXKIuZ5+QgPIvrMQYya7yZmYCQDxwXq@vger.kernel.org X-Gm-Message-State: AOJu0YytAKdtilgvGaQSSUE3Lt6Iy03jz9CVEF1f6h2iDU4epvzZr23E hxsYRXEHYS7RYWApHCnJqOIQOovyLn+nb41NByoURGShjoy62Qvl X-Google-Smtp-Source: AGHT+IHIPy0w64KwZCJzE4v/DFqFINpH4qYlAw3nXSjCuQPizSxqR85cFPUFjcbg/F/q+RvKiQZlPA== X-Received: by 2002:a17:907:7e83:b0:a9a:522a:ba3a with SMTP id a640c23a62f3a-a9a69a65ed1mr396830166b.2.1729453232769; Sun, 20 Oct 2024 12:40:32 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:31 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 02/23] ARM: dts: socfpga: align bus name with bindings Date: Sun, 20 Oct 2024 19:40:07 +0000 Message-Id: <20241020194028.2272371-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Binding expects the bus node name to match bus and not amba. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 2 +- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/d= ts/intel/socfpga/socfpga.dtsi index 35be14150..c7ba1e4c7 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -62,7 +62,7 @@ soc { interrupt-parent =3D <&intc>; ranges; =20 - amba { + bus { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 7113fe5b5..7abb8a0c5 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -54,7 +54,7 @@ soc { interrupt-parent =3D <&intc>; ranges; =20 - amba { + bus { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37490198A0E; Sun, 20 Oct 2024 19:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453239; cv=none; b=cig4n7xDwdz/ptjQI+aowMoh4kq6O4GwzzftKO1PSn4M1r6yi6ewI5bCpoSkG3zQEffQZPAHNQFqqcJB7GDv/yPl2Pi5UesS4A5r3zih6tqGq6jmWdqYypWwymIFWDuCEVm63gqWcGEXQa7o2y9vl/AL+T5rKw/NZOrkys+zxhw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453239; c=relaxed/simple; bh=zUAJFmmnkJAWnOviaASwhwRRUPKQVvu8A4WKyBwFSeg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sm0yCZ8R4IoUYXH/xszjiKRi43tQy2GhlibpCp1ud2U4djLHeoTFZir2+8QbDaNk7mGY9l87xPQZXiVajsq9v+SjZuqHD+/EU/Iu+HV9pdpMbPi26ISCH6imSGNfYiigPuc03ngmesDK4vHXraCH5ZTuCSQsVrZ0IZyCocoIV/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QeDKrYDd; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QeDKrYDd" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-a966de2f4d3so35091166b.2; Sun, 20 Oct 2024 12:40:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453235; x=1730058035; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qk9braQhcUfjQhD1zhHgydTWlqcLCgBL7v99PtqcEgk=; b=QeDKrYDdEgUs3JEeTresRe1z8bKkhs5H7I9ZDzoKd+ypzcuaVZy2moBBIKb3XsgC33 rR7xqZXetjfcjlLeM2G1C3lD2IdIEbxLeRzvhZ/0YXCiZB3nMZtSJarw+KiJPAvH8C1f HUYocbUFEOa79TLVvAkpKhk5qzd8KAjkNDLxPvhqSHcyemWFfbx/LIIbwsKvKKITeNYo SZrbSTh2/siDKToPljab2fltWH3b1Uilmdhmobpugbm3ni6EZWNcJ8mW5J7R7g9oAvwz D9ELEvT+dWxWhkkNAbAq8Sgi9popAA3od7xHSzyvJlO47OaLAnoNnJ99X255HqDzNgGS xDSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453235; x=1730058035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qk9braQhcUfjQhD1zhHgydTWlqcLCgBL7v99PtqcEgk=; b=vxpy/aLl8JVUlL+sNhHswzWk3vi+5hiEVkhD9b7+X1WIAxqNcnJa8Kr/pz3PscL+Nm 5wN1p8ScOtUWYcbL+DPogrgjb4w7eXn02SsMh1qHOE0vtQkh6dN/Xjdku/Gp4RxqIMYe YHJEgXCoHkZN/uDHtLZetSZOxwcSp+KxwcCkZQghKMTwKcnoTduYMzHE+L2S/zkWOUgs EjiYRnVd7pLKc839VIQLdoLPflDMu/kPSak3UAYhcurdVGCKBOgQcG91s7A461zkx/wL CecG9mxf0ke85gJ4f0QWTqs12vlbhil4HVXy83YAF6u8i4cRqFtLP+ZNPL11NPKxaQT4 /40w== X-Forwarded-Encrypted: i=1; AJvYcCVsJURC69bGvjbUkxwaNPEo18jcGyiYDz8OFHUzqSytP4GEbECE690ZmlzjgBFSC6a9dyO3Q1ewdam8v9vA@vger.kernel.org, AJvYcCXx/C0QIhTh3nOaFCptyg7g0bFcPEEheR+8TaqNKCnsEsgWdIDI/vZfYKydWPdZzb9XHpEO1rLZtbAB@vger.kernel.org X-Gm-Message-State: AOJu0YwxINwJhKBFepPOhDJbe/NX9X74gvWah7yN1+U8QuWkmjEmlEnR K2hjDmWbrm9/0r16/yCS9wmjdca40ga+emResPsUfoVz66MYFEXD X-Google-Smtp-Source: AGHT+IE/fDR5kX58OzYRpo+s8afTu2DqWPvANQoZiz+MOG/8dfrXzp1n8R64yI0Q3T/sm35IPAPrtQ== X-Received: by 2002:a17:906:dc90:b0:a9a:147d:fec2 with SMTP id a640c23a62f3a-a9a69a7b3ddmr300859966b.6.1729453235287; Sun, 20 Oct 2024 12:40:35 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:34 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 03/23] ARM: dts: socfpga: align dma name with binding Date: Sun, 20 Oct 2024 19:40:08 +0000 Message-Id: <20241020194028.2272371-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Binding expects the node name to match with dma-controller. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 2 +- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/d= ts/intel/socfpga/socfpga.dtsi index c7ba1e4c7..01cc5280f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -68,7 +68,7 @@ bus { #size-cells =3D <1>; ranges; =20 - pdma: pdma@ffe01000 { + pdma: dma-controller@ffe01000 { compatible =3D "arm,pl330", "arm,primecell"; reg =3D <0xffe01000 0x1000>; interrupts =3D <0 104 4>, diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 7abb8a0c5..aa0e960a3 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -60,7 +60,7 @@ bus { #size-cells =3D <1>; ranges; =20 - pdma: pdma@ffda1000 { + pdma: dma-controller@ffda1000 { compatible =3D "arm,pl330", "arm,primecell"; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:36 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 04/23] ARM: dts: socfpga: align fpga-region name Date: Sun, 20 Oct 2024 19:40:09 +0000 Message-Id: <20241020194028.2272371-5-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Binding and setup expects to match fpga-region instead of old naming. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 2 +- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/d= ts/intel/socfpga/socfpga.dtsi index 01cc5280f..1562669b3 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -87,7 +87,7 @@ pdma: dma-controller@ffe01000 { }; }; =20 - base_fpga_region { + fpga-region { compatible =3D "fpga-region"; fpga-mgr =3D <&fpgamgr0>; =20 diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index aa0e960a3..90e4ea61d 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -80,7 +80,7 @@ pdma: dma-controller@ffda1000 { }; }; =20 - base_fpga_region { + fpga-region { #address-cells =3D <0x1>; #size-cells =3D <0x1>; =20 --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2FAC1990D6; Sun, 20 Oct 2024 19:40:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453241; cv=none; b=D7Yni/9DmuHoIqMmxitHkK2LCfaDzaep1FV8d6rN8KmVE5uKc7xAbvM5qCIHOkomyYfCoBOOehNIcmQO/YCcCUlSm/Kq/sSdyLGODNYkNKQ9j+veAcqt+0Cxy31hfVq+t4Xw0iWs+6UDmTN3ee/TYWTy87IQvLkx2v3qrWX8nmU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453241; c=relaxed/simple; bh=V2yl4lNntEuPEV0X2MVL+IE3GiZVw/y9HCOf0Pz1aTk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IPnXrB26wrAJQwGbUaDhP+4tbQBP8hWj9mW0QosQ4fa0e+C16iNaalDHu/FwRE0yB151kDubBUAaLYW7zjW64pQNkx8RgCiAsEOfRlx3KDrIA6tWbZpsDLNIB1LHS8TmzutPER9CesTM3NTjJC9/bgBCi9evU81REXmiYyvC7Mo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hmal9wc3; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hmal9wc3" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-5c8ae7953b2so613128a12.2; Sun, 20 Oct 2024 12:40:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453238; x=1730058038; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9wwdH5E3n/FKvtFIFoeUG2vP8wssuIiUjkTOLgVYvdE=; b=hmal9wc3QvYCrHXv2utNaLd+jigDQURvqcwwGvpH3NaPz5Z83pBSooUwOKMwcCdyMv kqalbcNuOCirPBuM5zSgc1O5oD4lLZOn3ly7zyuycJ8jwEHf/1TEChBeJvX4slTPNGz2 tDvQwLi4gla5+PXyfzOWUHEU7crf2+sKfU8by6XE+tKsN9e/5xqRrk71xDHET0fLZiTE W/kmJ5elkE0pMxM8vTODAWa6uou5DN5cjQphZunMYmNIEJ0M0KQMAfEs8K6/iJfX8zoh beUQSvOeww7nlTSe10nrFZXpVfL7JMyT+TTmxjB1GXe+oOVa5T0F2hofQgN3JyUNGgew CsGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453238; x=1730058038; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9wwdH5E3n/FKvtFIFoeUG2vP8wssuIiUjkTOLgVYvdE=; b=waZfzaTl/QL/8JR0dhx6w/3XTrtJdepuKwZyBKnOixYJZy2jv/Qwlk/6cK/A7dxpLT UuM2ph7VHF1mfSm96V07GS5qA1EgqtxTC1QqqZvwohgqq8Rd9fuISRvvp6Uhm5LcFwGI bqkuSnPQGTS/IK+JYbCv1f0qdUZMQS+VuC0c2nk7k26dxWGZjkSl0V458UFljpxeUoRg 7uef8iJm9fvdst7lmt72MFzeRyfyQSRh16bgJbbW+KipqgQlubXOQr589VTLLtWWhPCc Q6sLFem003JjZgUpGIce5r52nEXnfE2leLHIFVheau+JtESqha8rQQVlGWm+2DT05rC1 LVew== X-Forwarded-Encrypted: i=1; AJvYcCWhm/b4J6rRzT+SNwnwj178Jb5MmTT6oGlwVxpM1sBucwUiXmEcgbH4RCHQbP3XvirY3yEmgTRhNClE@vger.kernel.org, AJvYcCXRZSzQkBIR/lZI5w8weIZZDs0uiPvQj7xQscxbmoVCDgN17+RpckkdawQlj20PPLr4A5DGptAk+C6D3/eF@vger.kernel.org X-Gm-Message-State: AOJu0YzfS0K/Xd6eGD3GMn1zvz3/XuuBKJUh2X5ZnqOjaOjAAdBNLUrh PJWMJ9f38G7wnMPOlbE+K23fZHnEDv7jiEPsP233IvZ30L1WQgEx X-Google-Smtp-Source: AGHT+IEoUqPWyMGSegIGl7DGeOkVLEGnTmbG8Hwr2jDlIpvyJfAnfAvxvisexunW9mN25cbmNor73Q== X-Received: by 2002:a17:906:cb89:b0:a9a:123d:3f25 with SMTP id a640c23a62f3a-a9a69ca374fmr320996366b.13.1729453238173; Sun, 20 Oct 2024 12:40:38 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:37 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 05/23] ARM: dts: socfpga: add label to clock manager Date: Sun, 20 Oct 2024 19:40:10 +0000 Message-Id: <20241020194028.2272371-6-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Devicetree setup expects a clock manager label to be around. In preparation of upcoming changes to allow for compatibility. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 90e4ea61d..7f7ac0dc1 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -88,7 +88,7 @@ fpga-region { fpga-mgr =3D <&fpga_mgr>; }; =20 - clkmgr@ffd04000 { + clkmgr: clkmgr@ffd04000 { compatible =3D "altr,clk-mgr"; reg =3D <0xffd04000 0x1000>; =20 --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFA97194AE6; Sun, 20 Oct 2024 19:40:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453243; cv=none; b=rxvkk7zppT5GbH+hKhSw1BdrznVXuSzNN9g/sJmXK+Cl60CubpxzOHpe/2yri8ga0ttBQ/a3h1dWCafX4mf70dJjYW2+JluimFfiY9Jwyr6BW9AQO4b+YBrsQfDUCA6rNu4RBvfJetpd6YbApZ7A8NmnGjSAw/8pB0Lz/+cqF0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453243; c=relaxed/simple; bh=OtMc8F1P0PTrSTV9GAwD2G3wO6F1jpiSdyrg5IQ28zs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=l4IcadXDgMEMVgLQsLF6g5Sn4Iy/OP0MW3oHTItgg582kfnYOCzMmtgqGGu2VipWtrvRrBa9ZC2m9ujPliuwzPrG0bKwdcSw/Y4t7Uq/E2uRylkgvRrn9UzSIQd/u+QXiTHA1oBfFrDYkwuI5DioiHjp55QQt+izPkdDA6USd3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Zj+lW1PF; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Zj+lW1PF" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-5c9589ba577so519557a12.1; Sun, 20 Oct 2024 12:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453240; x=1730058040; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zykG5xT9htU2beqODKL0ma8uO47wG8f6mRcFvD55rTU=; b=Zj+lW1PF+Rf2b7mGqMN0v9Igjl7ZrKIYIzMDzmoF8ULvJM/m5hpyNxPBO0E+jx6zBt FZJUzGIVxiiJb6BJ2zdiljAJ5f7BpP2vs7AD3mosFWx6VNRGe4fEmR64Wi+4UmWUDWlk qvX7nkJDcP/YRK72DPbGRdozKU4P5KtLzqlazMbVPZrw26cI39EyReHul2QnRr9XLaC/ hXgYCYH4/1ogCwv2MycohUuYTzQhXdY96XJcoHDuK4CeV3pFdajid/l45crn8VdNPjic Ao0xtOccvpO6nlCPIyKBBPsbL+KHhBBUgOYKrAExw2j0KhGuFbYq2zBdtdCLFljq0AAi D00A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453240; x=1730058040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zykG5xT9htU2beqODKL0ma8uO47wG8f6mRcFvD55rTU=; b=iY7r+ubmbSilXEkLvmXY6IoRs/tO88sBeVE111N3TBhIjySq2uCIp/pJY+C5LKrA72 53jmPislZzodUkfwucx4JMZwQOElY5sp/lJdwaDbGs967MpYDlEi9bHMN5Zd78NLffGS bxoWvGr3h38MGKNtOKIrXEfHMDwBoHtr7EQNG6F9+fdLyB/12CQMW6ncrCLSmZKpeGFV 4AJgJ/+sMKZlbT6BycRqUo+KvZKfm2wWnbwibQq0zGj5mJrNX1vZinJAkQJF6KlnJTGw EQLod+Tz/BEjnxOgdVBevD+dIxFlilbRk8/cwKbU8ToJZuUxGgsYPjN+KEoT8n5QHret 7vXQ== X-Forwarded-Encrypted: i=1; AJvYcCWVU4RA/cV7s2sco3wDofnhXbs+OoPoy8L3tL493LpSMyGjw58XhF9T8tevFiK1/P0/kbt11+BcJ7Vm@vger.kernel.org, AJvYcCXxo96JE1FqOliSRXuLqSIwaaDvfTzMsmTETzcsyIdsTeK8KqlG6ND1DZdFXQA6fNnKz4JpErLRFdAuL82r@vger.kernel.org X-Gm-Message-State: AOJu0YxcD4zRSrq34sUkqkKqwuazZbMk/jEp0IJcsmvblEJn4FWQwuUn XmutspWPYPrV6mJJZaZwjqEp7tfC7UmSIWZyuyRqfvyziEg7DwOM X-Google-Smtp-Source: AGHT+IG4jol5cTVT0VxEpWzwTs6pDZZiwMQXuY1u7NMDU1ZT0kvzqFRESig0dpSYB6tuCEztbDPNEQ== X-Received: by 2002:a17:906:a28a:b0:a9a:8216:2f4d with SMTP id a640c23a62f3a-a9a8216326fmr231026366b.3.1729453239917; Sun, 20 Oct 2024 12:40:39 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:39 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 06/23] ARM: dts: socfpga: add missing cells properties Date: Sun, 20 Oct 2024 19:40:11 +0000 Message-Id: <20241020194028.2272371-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Binding requires size-cells and address-cells to be around for the SRAM. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 7f7ac0dc1..4b19fad1e 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -684,6 +684,8 @@ nand: nand-controller@ffb90000 { =20 ocram: sram@ffe00000 { compatible =3D "mmio-sram"; + #address-cells =3D <1>; + #size-cells =3D <1>; reg =3D <0xffe00000 0x40000>; }; =20 --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC1EB19596F; Sun, 20 Oct 2024 19:40:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453245; cv=none; b=pBXJdbX2A9CrNOZQTUWA3rz6E9bP03T8OhXKVaqDsy2SFcymuOLdosGWlusBGgfX5GYcZO8b6GoSzlyWMrJhSgPkZNw0v3xB8ghs+ZL2Ksxet7FmkN4oJjeEUhXneDg2APvZDO37ydOgNRhKRuRCBiFShGUVp58tqZsriRlGaW0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453245; c=relaxed/simple; bh=1KzJp/fai6aB837Tp2XCYOTjK4FVSS8lCtpXFfw4Wj0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mP8p8R/T/alMePru76sOc6/xiJm5C7m9fRZ+RHaDB/INu1pU6W6bg030MNldNqBeRPwGvw69cbvm4+xl+kxYRfDgy7fghi8/EIMqZC25VLZyGCmwjimEvNCxvTwx4Y46bekhj8d0zpxX35UimvjZ1pFk//KORHdxs9Ibqp2Vdr8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SguN6/Jn; arc=none smtp.client-ip=209.85.208.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SguN6/Jn" Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5c9ff17eddbso529882a12.3; Sun, 20 Oct 2024 12:40:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453242; x=1730058042; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=syqLQEEuQIy2cda968KqPmvPAkdMXpl9TyM7P/fgr+8=; b=SguN6/JnhUiuRvzM7L44VdjdKbV45x0Uzu1Y1udU4jNnIsgGAn+mMy7+/5yxX7hv6j jcUO6C//SfIEjaxxd0hKLPV8paBh3Gw3CxKluFbEB1mArfCPh4z/HhOJAJN1MqJVp5RN CJXXa2Cg/MjDPkfYIBDkz85bjkH5LW0nlM5nQNvW1z1oNrIvcGc+FRvNg6lwsaj8YHKn gDAhlYLHR6z92Jv3mo0RFnsHScqBpRbXorYkyXQfn9RN3PAAv8wJAlTwdA54UfdX9keS h0/lmz+Za5KyNk0zEHZGFhZTXzWv52/aeK2HDbAN+RNE0+rD3VkSP9vRi8NcrK0EdjGU 9QgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453242; x=1730058042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=syqLQEEuQIy2cda968KqPmvPAkdMXpl9TyM7P/fgr+8=; b=tXD2WmahrIIrCDTcw+oCLk7Ng5/Jrp6lFpWhMICnAHZeNDb/wh2zM/2r7SJWfU0AK0 xeLAE13I8XtNbLsdSJiUpiUZOR2kPYMJrrJxR7e+Ea8J4Xl4xaXIUVCD7dbS8zu/DSDg 6aCIMmDVL7un0GJ99OcdJ1QrfSMdN2/jl8AdDoyGhoAHMWm+4paV0EAi6LPK8Q1tF5k5 NU/aY0lwxGtWD5MadN6fMZJ8IoljdfiakPylbKrqAp9SCO/u/WnBeWCgRYjypQJgqBm8 zAanuoydvTRqC5Zvd7A5MJxIWETf6KYyQCmMLZZQTSGTUTaxqdmcqXsxrsLIu08mTwFp YVMg== X-Forwarded-Encrypted: i=1; AJvYcCUSyLVLHjRrTtR7jJu/lRiwo4fabKIFmqdfb7AgK82sM9OOWf4AbVBT348xV2oNH4kTWWEhpAPo0g8j@vger.kernel.org, AJvYcCVVt+/G/VW59egNFxtHCOcZmg946w6SZn53njzwty1DHlh7qX3t8euiPZXnmJguKx+lITEhoWhjbdLv4NA1@vger.kernel.org X-Gm-Message-State: AOJu0Yzdj4voc4TFvdsIimVTWR0J26AGLo69U/WutfhbmfWzESIMDwaJ kApFv3vnimtmUD9X8J5b3ZbZCvf8W7JwgC/V44/8j6N4Xdans8uZ X-Google-Smtp-Source: AGHT+IH/gdlMGESSvhtbl14hZFRa0X7jzE5onhuD7JHXpbkJXMaKFnK9KJJ3aTbOEPUj4bpYXM9T0g== X-Received: by 2002:a17:906:a28a:b0:a9a:8216:2f4d with SMTP id a640c23a62f3a-a9a8216326fmr231028566b.3.1729453241634; Sun, 20 Oct 2024 12:40:41 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:40 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 07/23] ARM: dts: socfpga: fix missing ranges Date: Sun, 20 Oct 2024 19:40:12 +0000 Message-Id: <20241020194028.2272371-8-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add reanges, since by dtschema 'ranges' is a required property here. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 4b19fad1e..65d04339f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -81,10 +81,10 @@ pdma: dma-controller@ffda1000 { }; =20 fpga-region { + compatible =3D "fpga-region"; #address-cells =3D <0x1>; #size-cells =3D <0x1>; - - compatible =3D "fpga-region"; + ranges; fpga-mgr =3D <&fpga_mgr>; }; =20 --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 807F7195980; Sun, 20 Oct 2024 19:40:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453246; cv=none; b=jrnG9348PgEt6MVKwgXmOUQumjHTcBjo7dpkb6lpsYIodMkfErldFrmE5rkI5pBgfFlups/pCFr6Tod5hf0VcnCDTM16nYJ9STLVddUj8xmwpG+hvzzJwY+DBUgC6Jc9km0EsTOlyNSPFUgosfweW8i33Ve2e7PL9g2VFvwgxow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453246; c=relaxed/simple; bh=y6S/vFniqdK8FnY4Owxt462kYlq+HMo/27OIQpdXFyk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jHBi9/Z1pWpp5z4Gy55760vSXIKSXyQ71kpKcMhue+qBNrdmHwcnEl/CkiaBt22SchzhvZOJm6JacOUX6OpvhdB+gDqFgE4GO7gAu/qlf+ghR0UQ2OFT+Pq6Hn4a57hpRhTf6jX9mGx/WiQigC5KhFBiAYsh48zSOMF7lq/i9Us= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lULRPdIL; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lULRPdIL" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-5c8ae7953b2so613131a12.2; Sun, 20 Oct 2024 12:40:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453243; x=1730058043; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QbnDXxocaCyheHFI8hTECOWKPKoXgfCmEGz3dctI1es=; b=lULRPdILEfYpJGcHQoiuebKm0ukTR+vGxSDi1swTMXhwUFOcka9kF08hEsJEmIVbri GNC+YLs7lCTYZcZeYqa9dDSx+vdjeU/svkHgm/Ak3QvcLSk63/tC4Bb931h0mpF05I+u iQnPF8IIo9lpdzpXlK763KNA2REjE0LbChcPUVAuEuPwtzJaPs3RN/dBkc7q4dLtGwuz Ox3hmfutBZ6AG3AzMyGxVILQbDGm3tCbxFhp8XHHMjWuxv6b/B/S7CTlqdWRHAH5kS64 FmGtbm9KI2GViF3Tl2Zk4hS6xSFLZbJS/n14vQGsk1s1KmmGjzFaCKf98E3ppXkBwUod nW9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453243; x=1730058043; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QbnDXxocaCyheHFI8hTECOWKPKoXgfCmEGz3dctI1es=; b=SLL6mRcn+Imf+/9irAV3lH9VCiq26HiZvw68C4dfUTRx4d5amuN4DZgndpMdmweGP6 wyyrbHXisYYNVc99f359pyBYSxmV1UDb6F76j1Eapq0AYJiywZbsLDWJ/jvqZxGiseK2 +xo7B0vgEmA6gX89UOInCiH37QrfveDkrDeiidANzwMtWfKYBuYthhodo8+9TWMBF8z3 aIOobDXHtSM+5IES0o+bQY/wpkE0TWxEb1oB+TS9vK8ebXJHw87y9TEgLQwNoIU+C11t VxmAMusO8fBlDb+0c1kKmI+oqsi7ItFz2NvH+mzPM8RivwTKVMtKy2nENWeWiVo0v9de ZSdQ== X-Forwarded-Encrypted: i=1; AJvYcCUaSDJYSoXG0R6VbFEBpPkMKgXYPNTrLzJONc3YPe6yJ471sKSTOnNEi4UUMWtmgaA06IOXUVaMzA0n@vger.kernel.org, AJvYcCXdLzwvqZoBa0V8+Tn0f+o+vnr1n7bYPnN3T5He2F9rHs6iNGLnnZhLzQ1Vt2WwViIIFJGKvAvRv3wzPyz7@vger.kernel.org X-Gm-Message-State: AOJu0Yza72lsfMG3em5XfPlRKqghiUj7EX5UgwH9GVZgJl1MW88OA3VM Y19iUUMAClNOOlLaV+YethJg/2TQi7skyS/naoFlZWXoy6LfUy+y X-Google-Smtp-Source: AGHT+IEjTtTGxSGdX0i2yMMew0hF21usnZjLRMotUlz/FT0METXEgvaxuYjPqd6HCeN4v3FhhksB5Q== X-Received: by 2002:a17:906:4113:b0:a9a:7f84:9408 with SMTP id a640c23a62f3a-a9a7f849ed7mr252065466b.3.1729453242665; Sun, 20 Oct 2024 12:40:42 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:42 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 08/23] ARM: dts: socfpga: add clock-frequency property Date: Sun, 20 Oct 2024 19:40:13 +0000 Message-Id: <20241020194028.2272371-9-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add 'clock-frequency' is a required property by dtschema. Initialization is open, similar to agilex devices. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 65d04339f..5f4bed187 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -99,21 +99,25 @@ clocks { cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 f2s_free_clk: f2s_free_clk { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 osc1: osc1 { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 main_pll: main_pll@40 { --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64644199E84; Sun, 20 Oct 2024 19:40:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453248; cv=none; b=TYDtRFZgSxRI86T15XToBvky0Nys4cGStgNNEGSrqsEKp97AtSe7Pv8Qwke5okcIaxPpwjDubcE5vm8H+2ahcZj+kAQCJaq84XeA9A3ldZKw6MtVjeO4VnImWV1v6hM0s17dEl7IfG7/qHK4oy5V0oGTaiyIdRTkCzRYPbttbgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453248; c=relaxed/simple; bh=Ek3f9IntqkTVZaMM5+9uMLvwBlmFC1g5tii851ibiMQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=o/bMgh+anLtaJMcExE4dN1LGZUj8P13oxERtLfw4YVmRnXhMQfXT8beC9VKXdYyminIFfjjdqPmfJIzK8KAEOtAXD8WPPgys/LLforAtrH9hhs4UPfUKP38BkyPIQ/COf7kmcgCkwoTpwOcgq8cGWeIbILKOldWVmvSP1YiWfwU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RGw4FQhb; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RGw4FQhb" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-a99f9fa66fdso41532266b.0; Sun, 20 Oct 2024 12:40:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453245; x=1730058045; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JxrWAGvbebnl7bShJIljz1Nm6dGXiAY6T1E3WWpWzg0=; b=RGw4FQhbRUjOfTj7IvNwmBVAwzwJBuOYCRE1EHMWbmFwVXAwAP7EH01YId0w/Mv5iG lKqswTwS2+w6Wnx/j5K0jIFMa4IdJinvfWvTRIrVIDDeeY2roV1XZmyEe98MXrQWD5b7 kfEb2ndg82gIa9LG5r9+FdlumOjljE7Njza9G3PJErpUs+OLkObdGcvbTPHWl3ngdKFx aotl8qcWKzMFpDlpTJdEBz3qTib6op8NnMNQNQRB8tqDmCG7Sd3H949ouPgQo1l2OWxF Ed6s2rG9pUJ/fo1vtCSOKkiNlvSvyhSIuxcCYr+fhooPiL+V54ZjUM7i0EjgRga1anzL 2e9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453245; x=1730058045; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JxrWAGvbebnl7bShJIljz1Nm6dGXiAY6T1E3WWpWzg0=; b=tKpVPGLB3GALu0SnwaeZFSoMx34LAdRLR0vCtNDxOtABzQWnuAJU1HdMDq32wXowDZ 6bAo3b6NqLcr31m0s+0MsIdAnhdrjbZb6n2eI58brTwpeIMUWy4lSYNXYQXrI2Ine210 Y9RGebO1SeaasQB8G5WbmfUvQtd6p20R9Ts6n2n+iJam829q0FMGPaH7rNGZ0yLPezH0 f09Od6oiXJHIogB41UiSwNaeN4JvSbom3bYOLwBvZ3QkzCaK0z5xFJoOxGa6LacgEHXN GmvL9G8uNKQsdfzxq7qcQhSO5CnG+kjUAcfTbcz7PLhznW3DCLXIT3Ac+9yr1MPElxm7 qFJA== X-Forwarded-Encrypted: i=1; AJvYcCV8IknSx6QMX70XpEYAWWBE1c1nBI7AKxKoycMl23sO2sT8DWRbc8mqILg/lB6u55aCBvFQpiD4q9Hc2iop@vger.kernel.org, AJvYcCW9Nz1a5FQJLD2jtHBa6+hG+50k4VAHNaXVp3fX55y63ce6aPgrLZ8ybok+R2v/irXfHdmTpFvr+8kq@vger.kernel.org X-Gm-Message-State: AOJu0Yzwsgldw9TYIS4jnQVWliSW2nH4JF7Tz6jEyQ0P8Nf83KipzJgO FxTfCwN6EZoGoG+AaWaGW4gFHgCzIOwHAI4cQAWw/GnvW2tv5Wlp X-Google-Smtp-Source: AGHT+IFCZ6BJIUyBnORr0mBO7BasiZrlFliRi4/7kBie7xUahDtQZwEAY2svoJaIho4w3E2UALcNBw== X-Received: by 2002:a17:907:a47:b0:a9a:2a56:b54 with SMTP id a640c23a62f3a-a9a69a6aa6emr501922166b.5.1729453244416; Sun, 20 Oct 2024 12:40:44 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:44 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 09/23] ARM: dts: socfpga: add ranges property to sram Date: Sun, 20 Oct 2024 19:40:14 +0000 Message-Id: <20241020194028.2272371-10-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add 'ranges' to the SRAM node as it is a required property by the dtschema. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 5f4bed187..6a2ecc7ed 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -691,6 +691,7 @@ ocram: sram@ffe00000 { #address-cells =3D <1>; #size-cells =3D <1>; reg =3D <0xffe00000 0x40000>; + ranges; }; =20 eccmgr: eccmgr { --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07388199FB4; Sun, 20 Oct 2024 19:40:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453250; cv=none; b=roNpOwaGTCYbameFj33QjAPwCsrKdMsxCpJ6cXYZBaiOT+DRwtNuKSM0hBQpQSCh5ifK/6Tcj7BMPEfYgo/9sPlax1udwdrbiDRGVQSiQJ5HZZdoIlOnoxtetS7umzja+wAu5twrJmbbIT7gni3GXUgqKuwfZDmrOgbugNZ1heU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453250; c=relaxed/simple; bh=GRIprTk55YoxyAtAqBSmeVlFwn+FJRp9HdXHznTSR8s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aM7MYascx1yUufmnkna5xzZW9sECVQZrtdVG+lIosfMfp87yi2upa2wZlmgQ7zXRNBPU8Qs9Wm05RQ0Ex8p8iy+sKACj5SsEFuYl4vv6wlCrc/m2OcQFFLhQK5R5VKOAvHSDMRR33aefyPeOyza5VDtc+oWnqnHCYdTvayvlbk4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JIXPcXb6; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JIXPcXb6" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-5ca0a1fc1aeso437355a12.2; Sun, 20 Oct 2024 12:40:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453246; x=1730058046; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vySvn0PrZ5KmWWRcUjB0f7ffbO3G5ojONpptbAIcwaU=; b=JIXPcXb6vjx5l9UfSZIuM0iprnXU15ckb3+uEQxXbtTH4/mEzYWVR+mTQLp8lw50+t xmkF5sbp9IB/89Eu36SSUPgNumzNIfe22+RV/MZYbFk4rLcFSknY3RqI84j4yE26O/HO qXUyKpY4DKqAiIIE2Qo23LX52sDzOGZhJIcTUkZMyg7vpF2Zotpo7kw87+xn771bfDQ5 Nkj0Oe7mB1b11tyNUl2EJNqVXWND1Nr0/4FJFNajQqrJq26DSBaVt/ZL0phNvBduANCl q71ttZ1o5Q7XfN0lPxa88lEU7FLe0ngtvm9tETzP3BxBo/L+BCsrqLn2QF87rW7wsuPU RqqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453246; x=1730058046; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vySvn0PrZ5KmWWRcUjB0f7ffbO3G5ojONpptbAIcwaU=; b=riW1lVjfGrF59QXgFBVaQ9ZRZVrSW+HqwY1n0a7nMJW4yuNII9mp7WegYEmO1Sp2FL 74ZjrN3lZ7N+1CmiZnWMWGTbFaOae69pjXKZJJ+OK2GGseDQ2UdB0GToY5vTfMgoiXY6 IFCmdmKjAtWa9kpkjh7W35mPWHyxPt1v/zBug3GpKuSaUZUlAzdp4s06Vp3QDVTDmaQ9 QrcMVit9b+K+Ue13+UMW1Owl3fsA8AqTWtQSGJ6VQfw/l/LSXb6+f50PSnx+Kc2zwdC1 gKCFzKWOVyk75vA7eBZtaWApqC4QGTfG+keTjFLJcKrfTw7UM9x3EziA8fpfUVxovmnh AUgg== X-Forwarded-Encrypted: i=1; AJvYcCVfpHT/R9CR0RVaMomIM46WewjrP1Li0mlFxOJHMsb/kCDtzRQMB8yBZknygLwoPGWP0wrbqHWzzJDxTxuk@vger.kernel.org, AJvYcCVyUzdZSaZvDZJ9rMN111PVRO7i5Sj28T4F8yJ6dGXR+FTvy2EAkouSRSw4Qc3XnBCtLDVTgmuI6lTp@vger.kernel.org X-Gm-Message-State: AOJu0YyzTUonsS03F1xWPLjCs1QVurYS/rZJIvMA1ngWWCv74I/sEgXP YyDhRq8vsX19tzQIjubgdyvxlUldvXehHpMl39Ly/5iwlEhDXqbS X-Google-Smtp-Source: AGHT+IEfscwM9JQL3H60yPkVgWVilalHL4+zNcKDM3YY77l5JS1uaBflsxUbryv8FkPvJ5oCEQK7dA== X-Received: by 2002:a17:907:3d88:b0:a9a:3999:23e9 with SMTP id a640c23a62f3a-a9a69a7668dmr371353866b.6.1729453246148; Sun, 20 Oct 2024 12:40:46 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:45 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 10/23] ARM: dts: socfpga: remove arria10 reset-names Date: Sun, 20 Oct 2024 19:40:15 +0000 Message-Id: <20241020194028.2272371-11-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the reset-names since the binding does not mention them, and they seem not to be used in arria10 (similarily to agilex). Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 6a2ecc7ed..005c57843 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -818,7 +818,6 @@ timer0: timer0@ffc02700 { clocks =3D <&l4_sp_clk>; clock-names =3D "timer"; resets =3D <&rst SPTIMER0_RESET>; - reset-names =3D "timer"; }; =20 timer1: timer1@ffc02800 { @@ -828,7 +827,6 @@ timer1: timer1@ffc02800 { clocks =3D <&l4_sp_clk>; clock-names =3D "timer"; resets =3D <&rst SPTIMER1_RESET>; - reset-names =3D "timer"; }; =20 timer2: timer2@ffd00000 { @@ -838,7 +836,6 @@ timer2: timer2@ffd00000 { clocks =3D <&l4_sys_free_clk>; clock-names =3D "timer"; resets =3D <&rst L4SYSTIMER0_RESET>; - reset-names =3D "timer"; }; =20 timer3: timer3@ffd00100 { @@ -848,7 +845,6 @@ timer3: timer3@ffd00100 { clocks =3D <&l4_sys_free_clk>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:46 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 11/23] ARM: socfpga: dts: add compatibility for arria10 Date: Sun, 20 Oct 2024 19:40:16 +0000 Message-Id: <20241020194028.2272371-12-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatibility to the arria10 platform. This fixes the dtschema issue 'dwmac: failed to match any schema with compatible'. Signed-off-by: Lothar Rubusch --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 15073627c..d26bb77eb 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -26,6 +26,7 @@ select: - snps,dwmac-3.610 - snps,dwmac-3.70a - snps,dwmac-3.710 + - snps,dwmac-3.72a - snps,dwmac-4.00 - snps,dwmac-4.10a - snps,dwmac-4.20a @@ -88,6 +89,7 @@ properties: - snps,dwmac-3.610 - snps,dwmac-3.70a - snps,dwmac-3.710 + - snps,dwmac-3.72a - snps,dwmac-4.00 - snps,dwmac-4.10a - snps,dwmac-4.20a --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37C2319AA75; Sun, 20 Oct 2024 19:40:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453252; cv=none; b=FngoKVeE2wXbHHpm3BiMSA0+I1WRD+BH8e1OgAj8pPfxmXnU9hkZC0oOsjEBWtVfD4WPgvbl4HD4lswhN4w9WgxiQJ3Vaw8irT63dbcsYt9o/XHzQHUVpHf+Q4ynze2g5XctEMtDSusyKt+b1uE6jV8fdwwriVcNs4F3cdUGyng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453252; c=relaxed/simple; bh=LxKeuuubBdeyS7smSFyKjfRR58SVpqZBgKhy2eKoKkY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YJyGRdnf3gEVliESlOsrsnbuk4gm1rFTZmwwbrL/e187EaUKVTc4QYoropEUA3sZCI6ozJuaN+ePt3fO9mcEn0smkXMiZ7GQTS2oKuj3L9gWZhX+uYcN/nwblQ9vyGKslxskxfBpMbnN6XIZ9pZ9D1b/ZQpd6nPikPRbyGOmO+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=J/V9JJuR; arc=none smtp.client-ip=209.85.208.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="J/V9JJuR" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-5c940512711so703412a12.1; Sun, 20 Oct 2024 12:40:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453248; x=1730058048; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kfSYuXKOV63fz8fGkqZMMmJTLZOt2OeBpdkhvHCPQZA=; b=J/V9JJuRTHhLazfOxInBeyXbwRiDKZzKWOb1vCjZ8/j5FW4mS/QX5CMsins3LKfrUG DKtYwaZaAM/VfRemUxMu7mnPjL4loWPb6S8SZI6kDgTRLr6tiE5HeH5msb+N94wt6sVq mi/M82uPJnpW9PgaU1zDBnD42UrEnp64CTS2REnTU+vOFhVy86HbGJN07iR1Y7kyLSjC dXuG+KYJXLDx8K6fizf/5GWle902C7a3+9Ru9TbDp6I57FVR9FREMmpYc2+CQ71OWPbW bA9e5rZ53IWneaUHEWxI0A9Jm70Ti+mUTVBLhyXFNc67WR7FmIhSjb4hNxH/MHlbgJYN asag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453248; x=1730058048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kfSYuXKOV63fz8fGkqZMMmJTLZOt2OeBpdkhvHCPQZA=; b=AABTbs0mXfVN1QjeEsY1XX69TlRYy0e1Fe/xf9yfKOdpMHW3Tl9Ly0zoCDpo3HjSqt UA8TxUMLKXiGXMPXuBexiV/jpvrzUt2dTYyI1qJ6qCvDbB8ifyeTpnACuOB+43lnfvqF CKTv0RgX/pGG858Q/BEc0ziyB3rB7CB8MUAFrnaqoGoVb+MYv9J1VDz08t/aFkTIVxTV svLc7BpTPf4tJ35vosT5PmiiwNtojuL1yQEQ2ndQXDMtIKqOf8lRR1PT7GlEouDKDyFl YClEEqC/lWwMYhi3ScD4owWENutzt7h7izFpvR312EJ9NfX+Q3PtN67h4r7FXHNCXFG4 1rbQ== X-Forwarded-Encrypted: i=1; AJvYcCWX0/ORot6TJd9kV38SwHCmdgCVab3FDN1hnhvTBr0pCVh3XadTgBlrdB9s0ZuerndON7AsIAlulylfntEo@vger.kernel.org, AJvYcCXcHePl43sPtUBVGKtd3mGrhgK3qSrKcmH9qQjbGHdmy3UhwMm9Yx3PRIgkgwniPe6VAast/S4QQhJb@vger.kernel.org X-Gm-Message-State: AOJu0YxnUdZ8EclxhCXfXrL7jvwv8tMEUpQQ5cviSvyOTc929AslSKek 2e/JMEtmjKMln3+xIl96RrDK71rSyk44xnwRAgSafOvl99oWyJSv X-Google-Smtp-Source: AGHT+IF4md087S5ok8j/uZls2JeEHQpY1kiuzvt0B4nM4HR296L11vSNyHyTVyvX9HNfwkkAUjFhdg== X-Received: by 2002:a17:907:e91:b0:a99:8642:4f41 with SMTP id a640c23a62f3a-a9a69ca3744mr403961866b.14.1729453248216; Sun, 20 Oct 2024 12:40:48 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:47 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 12/23] ARM: socfpga: dts: add a10 clock binding yaml Date: Sun, 20 Oct 2024 19:40:17 +0000 Message-Id: <20241020194028.2272371-13-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert content of the altera socfpga.txt to match clock bindings for the Arria10 SoC devicetrees. Currently all altr,* bindings appear as error at dtbs_check, since these bindings are only written in .txt format. Signed-off-by: Lothar Rubusch --- .../bindings/clock/altr,socfpga-a10.yaml | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/altr,socfpga-a1= 0.yaml diff --git a/Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml = b/Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml new file mode 100644 index 000000000..795826f53 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/altr,socfpga-a10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device Tree Clock bindings for Altera's SoCFPGA platform + +maintainers: + - TODO + +description: + This binding uses the common clock binding[1]. + + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +properties: + compatible: + description: | + shall be one of the following + - "altr,socfpga-a10-pll-clock" - for a PLL clock + - "altr,socfpga-a10-perip-clk" - The peripheral clock divided from= the + PLL clock. + - "altr,socfpga-a10-gate-clk" - Clocks that directly feed peripher= als + and can get gated. + enum: + - altr,socfpga-a10-pll-clock + - altr,socfpga-a10-perip-clk + - altr,socfpga-a10-gate-clk + + reg: + description: | + shall be the control register offset from CLOCK_MANAGER's base for t= he + clock. + maxItems: 1 + + clocks: + description: | + shall be the input parent clock phandle for the clock. This is eithe= r an + oscillator or a pll output. + minItems: 1 + maxItems: 5 + + '#clock-cells': + description: from common clock binding, shall be set to 0. + maxItems: 1 + + fixed-divider: + description: if clocks have a fixed divider value, use this property. + minimum: 1 + maximum: 16 + + clk-gate: + description: | + for "socfpga-a10-gate-clk", clk-gate contains the gating register an= d the + bit index. + minItems: 2 + + div-reg: + description: | + for "socfpga-a10-gate-clk" and "socfpga-a10-periph-clk", div-reg con= tains + the divider register, bit shift, and width. + minItems: 3 + maxItems: 3 + + clk-phase: + description: | + for the sdmmc_clk, contains the value of the clock phase that contro= ls + the SDMMC CIU clock. The first value is the clk_sample(smpsel), and = the + second value is the cclk_in_drv(drvsel). The clk-phase is used to en= able + the correct hold/delay times that is needed for the SD/MMC CIU clock= . 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:48 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 13/23] ARM: dts: socfpga: add Enclustra boot-mode dtsi Date: Sun, 20 Oct 2024 19:40:18 +0000 Message-Id: <20241020194028.2272371-14-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add generic boot-mode support to Enclustra Arria10 and Cyclone5 boards. Some Enclustra carrier boards need hardware adjustments specific to the selected boot-mode. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_bootmode_emmc.dtsi | 12 ++++++++++++ .../socfpga_enclustra_mercury_bootmode_qspi.dtsi | 8 ++++++++ .../socfpga_enclustra_mercury_bootmode_sdmmc.dtsi | 8 ++++++++ 3 files changed, 28 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_emmc.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_qspi.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_sdmmc.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_emmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_= bootmode_emmc.dtsi new file mode 100644 index 000000000..d79cb64da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_em= mc.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status =3D "disabled"; +}; + +&mmc { + bus-width =3D <8>; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_qspi.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_= bootmode_qspi.dtsi new file mode 100644 index 000000000..5ba21dd8f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qs= pi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&mmc { + status =3D "disabled"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_sdmmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury= _bootmode_sdmmc.dtsi new file mode 100644 index 000000000..2b102e0b6 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sd= mmc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status =3D "disabled"; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:49 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 14/23] ARM: dts: socfpga: add Enclustra base-board dtsi Date: Sun, 20 Oct 2024 19:40:19 +0000 Message-Id: <20241020194028.2272371-15-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add generic Enclustra base-board support for the Mercury+ PE1, the Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be freely combined with the SoMs Mercury+ AA1, Mercury SA1 and Mercury+ SA2. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_pe1.dtsi | 33 +++++++++++ .../socfpga_enclustra_mercury_pe3.dtsi | 55 +++++++++++++++++++ .../socfpga_enclustra_mercury_st1.dtsi | 15 +++++ 3 files changed, 103 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_pe1.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_pe3.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_st1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi new file mode 100644 index 000000000..11f418e88 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + status =3D "okay"; + + 24aa128@57 { + status =3D "okay"; + compatible =3D "microchip,24c128"; + reg =3D <0x57>; + pagesize =3D <64>; + label =3D "user eeprom"; + address-width =3D <16>; + }; + + lm96080@2f { + status =3D "okay"; + compatible =3D "national,lm80"; + reg =3D <0x2f>; + }; + + si5338@70 { + compatible =3D "silabs,si5338"; + reg =3D <0x70>; + }; + +}; + +&i2c_encl_fpga { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi new file mode 100644 index 000000000..9fbde91ad --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + i2c-mux@74 { + status =3D "okay"; + compatible =3D "nxp,pca9547"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x74>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + 24aa128@56 { + status =3D "okay"; + compatible =3D "microchip,24c128"; + reg =3D <0x56>; + pagesize =3D <64>; + label =3D "user eeprom"; + address-width =3D <16>; + }; + + lm96080@2f { + status =3D "okay"; + compatible =3D "national,lm80"; + reg =3D <0x2f>; + }; + + pcal6416@20 { + status =3D "okay"; + compatible =3D "nxp,pcal6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; + }; + }; +}; + +&i2c_encl_fpga { + status =3D "okay"; + + i2c-mux@75 { + status =3D "okay"; + compatible =3D "nxp,pca9547"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x75>; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi new file mode 100644 index 000000000..ffcef353e --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + si5338@70 { + compatible =3D "silabs,si5338"; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:50 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 15/23] ARM: dts: socfpga: add Enclustra Mercury SA1 Date: Sun, 20 Oct 2024 19:40:20 +0000 Message-Id: <20241020194028.2272371-16-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce support for Enclustra's Mercury SA1 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_cyclone5_mercury_sa1.dtsi | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.d= tsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi new file mode 100644 index 000000000..3eb2c559f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model =3D "Enclustra Mercury SA1"; + compatible =3D "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + ethernet0 =3D &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name =3D "memory"; + device_type =3D "memory"; + reg =3D <0x0 0x40000000>; /* 1GB */ + }; +}; + +&osc1 { + clock-frequency =3D <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + status =3D "okay"; + + isl12020: isl12020@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; +}; + +&uart0 { + clock-frequency =3D <100000000>; +}; + +&mmc0 { + status =3D "okay"; + /delete-property/ cap-mmc-highspeed; + /delete-property/ cap-sd-highspeed; +}; + +&qspi { + status =3D "okay"; + + flash0: s25fl512s@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "spansion,s25fl512s", "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; + /delete-property/ mac-address; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy3>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; + rxd0-skew-ps =3D <420>; + rxd1-skew-ps =3D <420>; + rxd2-skew-ps =3D <420>; + rxd3-skew-ps =3D <420>; + rxdv-skew-ps =3D <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:52 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 16/23] dt-bindings: altera: add Enclustra Mercury SA1 Date: Sun, 20 Oct 2024 19:40:21 +0000 Message-Id: <20241020194028.2272371-17-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the DT binding for the Enclustra Mercury+ SA1 SoM Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 8c7575455..87a22d2a4 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -51,6 +51,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga =20 + - description: Mercury SA1 boards + items: + - enum: + - enclustra,mercury-sa1-pe1 + - enclustra,mercury-sa1-pe3 + - enclustra,mercury-sa1-st1 + - const: enclustra,mercury-sa1 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 503DD19CC2D; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:53 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 17/23] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Date: Sun, 20 Oct 2024 19:40:22 +0000 Message-Id: <20241020194028.2272371-18-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce Enclustra's Mercury+ SA2 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_cyclone5_mercury_sa2.dtsi | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.d= tsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi new file mode 100644 index 000000000..0425520e9 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2"; + compatible =3D "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + ethernet0 =3D &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name =3D "memory"; + device_type =3D "memory"; + reg =3D <0x0 0x80000000>; /* 2GB */ + }; +}; + +&osc1 { + clock-frequency =3D <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + status =3D "okay"; + + isl12020: isl12020@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; + + atsha204a: atsha204a@64 { + compatible =3D "atmel,atsha204a"; + reg =3D <0x64>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; +}; + +&uart0 { + clock-frequency =3D <100000000>; +}; + +&mmc0 { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; + + flash0: s25fl512s@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "spansion,s25fl512s", "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; + /delete-property/ mac-address; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy3>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; + rxd0-skew-ps =3D <420>; + rxd1-skew-ps =3D <420>; + rxd2-skew-ps =3D <420>; + rxd3-skew-ps =3D <420>; + rxdv-skew-ps =3D <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:54 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 18/23] dt-bindings: altera: add binding for Mercury+ SA2 Date: Sun, 20 Oct 2024 19:40:23 +0000 Message-Id: <20241020194028.2272371-19-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the device-tree binding for the Enclustra Mercury+ SA2 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 87a22d2a4..31af6859d 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -61,6 +61,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga =20 + - description: Mercury+ SA2 boards + items: + - enum: + - enclustra,mercury-sa2-pe1 + - enclustra,mercury-sa2-pe3 + - enclustra,mercury-sa2-st1 + - const: enclustra,mercury-sa2 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60DA919DF53; Sun, 20 Oct 2024 19:40:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453261; cv=none; b=PJRMFi9S3qHOz7akUqrKArqxJMsO1/xZQtqH2i6aJ5ExO2zoAiii4foyBAOMsqCV8UroU1lHw3i5JPD71kBOA5NxVZn4xWnTsrOt5hx5+DSBN+ZQGZc8Zp9LgjRzBTeU/BjI4a0J73XsXxvp/ffO9UNlFMOYN4zkk5VlqSUJWxY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453261; c=relaxed/simple; bh=4T4tsGiTu+7Yp74UkjgnnEqk77vW7pHzaOm0tx4xbNo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Nh41aYOFfC7jn9FBR4+fs/UBAg5Tw9ZGFnNsWU0wuo+/Jcm8iqvvFp/YamdzR2YLdsMsdQXhI4Xi8HtkXMKk7xonSL/8TB32HJmHj27h76Mn9z4+xp9qvilo519B+Mpnvg3uNjXDpe3KY282Ez476LbwwBL1OAWyeEXOoCEbcKI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=d/C3bGgr; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="d/C3bGgr" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-5c94c0bf354so565806a12.1; Sun, 20 Oct 2024 12:40:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453258; x=1730058058; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PoMQoTVDf0EJ7kPt2JC+Fe2z9tRYP9H50/zuHO5yLsU=; b=d/C3bGgrJ75WVNWwWrysc8yaJk2jk4hRMj1eBaFTHaZotD24MLjpLmUj4w9vNtG1H6 tdI4iiPlz8SaDzW/mf0zRWMHejPps9I5xlVGyRuZQeoDXMSd/05r43UtGwPzb5m8N604 XAnufUzLblqpqflgJNHt6MbxloO142o44KSSsls9gOTxHQiLyrFvYkQs2PaJJxmBft8Q smyvKxaJiK9vog+k27bhYiMdf/xckEXpx9WMxGCt1U5Vown9eFbVvyppjRyd351j57I9 Bqslmrs0NtBnmHQdQFFJICH22+kR17n+NicJ/VmluV9kNq/3HO14t8QchCQqFAI5vX98 ODUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453258; x=1730058058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PoMQoTVDf0EJ7kPt2JC+Fe2z9tRYP9H50/zuHO5yLsU=; b=KLl8+fSYViP9C2vhPAcuio9wdob1cS2TA5IC/DJ64QgTXfMHR+7ph7korSxH4ezuyy wFpuDYueomRH/KnaHCjjgJnKvVZkGsaW5P+u8YVfoyoaZbnQzApbHVdbxLDULBWuqpvp a0jDn6yqn5q+Bm6bY74TWwHsdMloDZQGWR6FzSXCHfXhMQiqTRBOn9ImuniotgE3cgHD uEkO9N0Uel2OU9Rm4OYjG9zpi/kUM2pijA1+qjhyqmHKCtDa73raTLHuCfsYt9YQOTU/ Rk4EWyudRe+T4sJhWQHfCVKhU2MBMz3bEysh6mK40bynHiqjA1WSIC6ZkB5SmtFbaT2I WA0g== X-Forwarded-Encrypted: i=1; AJvYcCU5SNy1P5cJQo9zaSKboYpgp7WUZTyRGPg2cMQGn452Ld4LCFkKh+Yngs4kgZtn6cJpyMrkDBVTX5YnYVVV@vger.kernel.org, AJvYcCVBalGepxjSY3V7ZtBJJ476XyRpFvGXmvZco0kVQZx1BMhNxOSzFxeqtEimJ0KS2I+zsFhMimPAX0b0@vger.kernel.org X-Gm-Message-State: AOJu0YxkGssjYv852i0RVK/n1nQZjUOWLT6y6JAUNWiYw+ZuQHS4Pfiv y76LKkaTOpM7ELkS3ZdeZWXsRGffQwuXV2PQkMqIrjgSDAUjm0/z X-Google-Smtp-Source: AGHT+IEBTRY13v0XBcACXcKCX1tPnEF+SFzDCQDyyS5oWNP61q6zQ2zyZ9NXzqb9/StiQ5Rs87g4ig== X-Received: by 2002:a17:907:940c:b0:a9a:1a17:e1cc with SMTP id a640c23a62f3a-a9a695d8adamr354288066b.0.1729453257490; Sun, 20 Oct 2024 12:40:57 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:56 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 19/23] ARM: dts: socfpga: add Mercury AA1 combinations Date: Sun, 20 Oct 2024 19:40:24 +0000 Message-Id: <20241020194028.2272371-20-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce support for Enclustra's Mercury+ AA1 SoM, based on Intel Arria10. This is a flexible approach to allow for combining SoM with carrier board .dtsi and boot-mode .dtsi in a device-tree file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_arria10_mercury_aa1.dtsi | 141 +++++++++++++++--- 1 file changed, 120 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dt= si b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi index 41f865c8c..cdd693cf9 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi @@ -7,12 +7,14 @@ =20 / { =20 - model =3D "Enclustra Mercury AA1"; - compatible =3D "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,soc= fpga"; + model =3D "Enclustra Mercury+ AA1"; + compatible =3D "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; =20 aliases { ethernet0 =3D &gmac0; serial1 =3D &uart1; + spi0 =3D &qspi; }; =20 memory@0 { @@ -24,52 +26,102 @@ memory@0 { chosen { stdout-path =3D "serial1:115200n8"; }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc02300 { + }; + i2c_encl_fpga: i2c@ffc02200 { + }; + }; +}; + +&i2c_encl { + status =3D "okay"; + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + + atsha204a: atsha204a@64 { + compatible =3D "atmel,atsha204a"; + reg =3D <0x64>; + }; + + isl12022: isl12022@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; }; =20 &gmac0 { + status =3D "okay"; phy-mode =3D "rgmii"; phy-addr =3D <0xffffffff>; /* probe for phy addr */ - max-frame-size =3D <3800>; - phy-handle =3D <&phy3>; =20 + /delete-property/ mac-address; + mdio { #address-cells =3D <1>; #size-cells =3D <0>; compatible =3D "snps,dwmac-mdio"; phy3: ethernet-phy@3 { - txd0-skew-ps =3D <0>; /* -420ps */ - txd1-skew-ps =3D <0>; /* -420ps */ - txd2-skew-ps =3D <0>; /* -420ps */ - txd3-skew-ps =3D <0>; /* -420ps */ + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; /* 780ps */ rxd0-skew-ps =3D <420>; /* 0ps */ rxd1-skew-ps =3D <420>; /* 0ps */ rxd2-skew-ps =3D <420>; /* 0ps */ rxd3-skew-ps =3D <420>; /* 0ps */ - txen-skew-ps =3D <0>; /* -420ps */ - txc-skew-ps =3D <1860>; /* 960ps */ rxdv-skew-ps =3D <420>; /* 0ps */ - rxc-skew-ps =3D <1680>; /* 780ps */ - reg =3D <3>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; /* 960ps */ + txd0-skew-ps =3D <0>; /* -420ps */ + txd1-skew-ps =3D <0>; /* -420ps */ + txd2-skew-ps =3D <0>; /* -420ps */ + txd3-skew-ps =3D <0>; /* -420ps */ + txen-skew-ps =3D <0>; /* -420ps */ }; }; }; =20 -&i2c1 { - atsha204a: crypto@64 { - compatible =3D "atmel,atsha204a"; - reg =3D <0x64>; - }; +&gpio0 { + status =3D "okay"; +}; =20 - isl12022: isl12022@6f { - compatible =3D "isil,isl12022"; - reg =3D <0x6f>; - }; +&gpio1 { + status =3D "okay"; +}; + +&gpio2 { + status =3D "okay"; +}; + +&uart0 { + status =3D "disabled"; +}; + +&uart1 { + status =3D "okay"; }; =20 /* Following mappings are taken from arria10 socdk dts */ &mmc { + status =3D "okay"; cap-sd-highspeed; broken-cd; bus-width =3D <4>; @@ -79,3 +131,50 @@ &mmc { &osc1 { clock-frequency =3D <33330000>; }; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible =3D "altr,socfpga-sdmmc-ecc"; + reg =3D <0xff8c2c00 0x400>; + altr,ecc-parent =3D <&mmc>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&qspi { + status =3D "okay"; + flash0: s25fl512s@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "spansion,s25fl512s", "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:58 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 20/23] dt-bindings: altera: add Mercury AA1 combinations Date: Sun, 20 Oct 2024 19:40:25 +0000 Message-Id: <20241020194028.2272371-21-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update binding with combined .dts for the Mercury+ PE1, PE3 and ST1 carrier boards with the Mercury+ AA1 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 31af6859d..51f10ff8e 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -32,6 +32,9 @@ properties: items: - enum: - enclustra,mercury-pe1 + - enclustra,mercury-aa1-pe1 + - enclustra,mercury-aa1-pe3 + - enclustra,mercury-aa1-st1 - google,chameleon-v3 - const: enclustra,mercury-aa1 - const: altr,socfpga-arria10 --=20 2.25.1 From nobody Tue Nov 26 06:39:23 2024 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE83619EEBF; Sun, 20 Oct 2024 19:41:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453264; cv=none; b=HYfaGwkjmrvoTNLQ/HZ1gTTgo4f4GDH3EfkIG+jmW6+ScRkBB6TJfZAmhH9ftjDfXXPYsuxJqQdJgX3jzf4uYp9SN9b/IPaaFmGNsIRha7wfvXO6kWr2N3+4di+xZxRrxkD2jGhFE06jIOceWXlsqNM8pPSzPR96e4MhiUHvRzI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453264; c=relaxed/simple; bh=S9k+VQ0WleJZ5GpcYDB2e3SzoRT8QVHAAnec/ufVy8M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qDHNASykeijWHncCVzIR9COnLlprBj2pExV/+83lK0kHGpvO4L+DTcE4vc7ny1umO/dKWcOeK+JRdfwFxhexYJNTNw6yF0ss4Muigm65zyAd3FgQhYQGEJ9PxeZFvxGaYGHItwFQgLWWd+JXpPJcvAkqSCgtxQpi0t0286GIdNk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=baXx6kBc; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="baXx6kBc" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-5c940512711so703441a12.1; Sun, 20 Oct 2024 12:41:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453261; x=1730058061; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p5pESrG6jMEz3xnbtE1/gQgYKtauCE3QcRjN239YnKs=; b=baXx6kBcP0j7mQ/rBmfMbO38MyNohCNU82zurLeoP0ecixts5Um91pw5ow+najE6Ti A0VFxOZz9C0rmzXxrlvUTBinQjJLW4cyoMG5VvC5+iWA0IBx7awK+15/w85NOEw+rQs3 1uBRaygcO0wVrbZ3/fA8GfogucaAzLbgOIHCT5OHbEQCyIGKE+y1DO6Zna9+sFrLJCQ+ uwuiuhxmogM/oOdNXi2yCnpvkThJz83VnckduR8fFa9cSb2Hmffgn0kmlv96vBEddH2k +wkXvMgaUy/88huy6U7EobXWCD458W/QPyKVoIPL/irYc16AaHcZMa/eUjcqI5Ca1Ze3 C4CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453261; x=1730058061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p5pESrG6jMEz3xnbtE1/gQgYKtauCE3QcRjN239YnKs=; b=r3X2/xkIbpCOYp9msUXByTB7WI2uFxGct0KYY1IcXHcOfU64ErLi912YmmXVuVKqTP 9txoZnDZbOFOXb7tWOlsokyiL3JTIvAcC5g3xw/d09ZAiJruJzdTjyVIk2qeMYFsVaHk 3vvAmPyQ5d1gLpNdFVx96vdg0n40/Ik8SV4FZR0EogLsGVtq+YpD4jJQEw3w72MvixgQ 3AqaMkqTXBzajjeYn0yB6jkXSXIsBZKmFhFs5qDQLA0JR24zgJBTysRS0qpIKPHFPpQF azkWDHCWAkmha7g6Anyt/xKNfimnB2g+mMA+BOYpaA9MudtFu5kBRCwbUP3JlHVb1Xz/ k0bQ== X-Forwarded-Encrypted: i=1; AJvYcCWJT7J71cLyuAk/QO14iwJMMUcDeJdYutOQpUD8pAYJ885GEVQXkuMcuftJ8QuD5UXgNM1bcVvwivNnCRa2@vger.kernel.org, AJvYcCWapsYPaxRdHgvwdDaaTmXifHKI5bsk/IacueJXsirPaQnz90beZ4HfGiYTNUK0n82cUVQx0IzxCyOd@vger.kernel.org X-Gm-Message-State: AOJu0YxTbNc/W4xv/JF+1XGfSYHKPsa4DCQvt3fKsR2dMbiR2CWTSuQG q8lAYJVOyiGNzQXZigXW9/abGeJJKIxzHTJm4DvCElGuyUJ9toKV X-Google-Smtp-Source: AGHT+IF83gtc3ceZBYemTxj0XFxbfY/ErtG6IxAMozBeReiybohHByeIJGVjNxrziEzzmZQmGm954g== X-Received: by 2002:a17:907:7f17:b0:a9a:3dc0:fbc3 with SMTP id a640c23a62f3a-a9a699608c7mr466509066b.2.1729453261075; Sun, 20 Oct 2024 12:41:01 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:41:00 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 21/23] ARM: dts: socfpga: removal of generic PE1 dts Date: Sun, 20 Oct 2024 19:40:26 +0000 Message-Id: <20241020194028.2272371-22-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the older socfpga_arria10_mercury_pe1.dts, since it is duplicate, the hardware is covered by the combination of Enclustra's .dtsi files. The older .dts was limited to only the case of having an Enclustra Mercury+ AA1 on a Mercury+ PE1 base board, booting from sdmmc. This functionality is provided also by the generic Enclustra dtsi and dts files, in particular socfpga_arria10_mercury_aa1_pe1_sdmmc.dts. Since both .dts files cover the same, the older one is to e replaced in favor of the more modularized approach. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/Makefile | 1 - .../socfpga/socfpga_arria10_mercury_pe1.dts | 55 ------------------- 2 files changed, 56 deletions(-) delete mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _pe1.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/i= ntel/socfpga/Makefile index c467828ae..d95862e34 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,7 +2,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ - socfpga_arria10_mercury_pe1.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dt= s b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts deleted file mode 100644 index cf533f76a..000000000 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2023 Steffen Trumtrar - */ -/dts-v1/; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:41:01 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 22/23] dt-bindings: altera: removal of generic PE1 dts Date: Sun, 20 Oct 2024 19:40:27 +0000 Message-Id: <20241020194028.2272371-23-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the binding for the generic Mercury+ AA1 on PE1 carrier board. Signed-off-by: Lothar Rubusch --- Documentation/devicetree/bindings/arm/altera.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 51f10ff8e..1561f0164 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -31,7 +31,6 @@ properties: - description: Mercury+ AA1 boards items: - enum: - - enclustra,mercury-pe1 - enclustra,mercury-aa1-pe1 - enclustra,mercury-aa1-pe3 - enclustra,mercury-aa1-st1 --=20 2.25.1 From nobody Tue Nov 26 06:39:24 2024 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 438EE19F411; Sun, 20 Oct 2024 19:41:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453268; cv=none; b=W3T8IDJP2X8x/+eSLRbLunAzUfIlRgq1pF86T+t2IpSrWGLkLu4Aop144nzaqWv2fO7PSYCKKSW3rp7Nlxr1RL5Mo/ug6pOi/e51o4r+Fj496PQFYTc9V/kjtLXv9mK+QzDDaa5fPJy3HmPGzXf7SkpCTRmpG8pQKFsZoUDrle4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729453268; c=relaxed/simple; bh=BKcROuWUYTw9JhFiD7stJcvz4b+0cKybV+ykIP65zt4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uHJcP1/TNAjRFMkHa+OqvxlyUfgnLYCKw2UXWaB4vnjPatQehJGtDRmy9U0rvwSCl2HwabGLBwA7XotijCQCH08tjZrGd9aUOcSi9NnHEd8mDOxp5vNN5PbojvJ4z+iQu1UjTY+uL11o3TQHu/EHfBSuSlcgiO8/v8TeMSM3ZKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NfIA00Dp; arc=none smtp.client-ip=209.85.208.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NfIA00Dp" Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5c9589ba577so519595a12.1; Sun, 20 Oct 2024 12:41:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729453263; x=1730058063; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=58/Yp9z5BeuiNsOYUdEfHyKptWKflHI/Ww9dE/OYykM=; b=NfIA00DpppjA4Jc4hhaT7PGW8m9uExhsu3m5pcgd+Muv7zacrFaj7owVGrhi0IkJ7V MMUMD4QR4bM7xQbBV7uAfuwVvLrYWvd5AgiVI0oNwH+d2zv8fMs2JtxpjZGc2o9LlnNO i0aywaCayp9P6DbYfYl/32n4fGm/dyRWZpFD2bOAi5Ff3mWB5VhzmBSvnOtamRqtemwr oykIh+2pSzeEoXzUNwYstO6UDfDHF4siURN1z97JM6+w/wpjOh4Ye8ViExzdEyfXexqH TnuZXUCN+UYs/MHqLLIuES15BBOP3OtM72xb93BoS77Y7V2/5fagD1Jn5bUQ2xvQJWpv jHtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453263; x=1730058063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=58/Yp9z5BeuiNsOYUdEfHyKptWKflHI/Ww9dE/OYykM=; b=KGVJAx8ST2noJKZ/IHzsKI/XDpm+5dkjf31yfbaDI4L/CPm3PSgKSwcxVElImOesnW osRsQzB1PZjRj62+vh50iPNPcItx3xfFuq7VQw+NRhwYzayAqgfqmYP5UPfyDjppzUqa cvohKj3yCoabiOtvioycQiLP2ZmD19jvU0B9QPEZJMhZFivPFOvIMqM2RbxxWVZYx49c n3iUOd5kHEzopIXIMBGHvMABQvMnOyAKl2zKySAHSHXx3K4JF3Y8J2si/NaABLtIf9m1 +JSSsbdpwlcIVIZ5b7keDl+cyTyC/XPTghEk7W/ty7oLjbV5o5JOK8Ho24u/zkciM0lv nJcQ== X-Forwarded-Encrypted: i=1; AJvYcCV9H3zU/3ndLX5uc1wlBs4SbWTBjSiilYL7zNSO1pcFYEIXskqYyr35hni451sgLqBdWn2TsQ6qxeOJgYK7@vger.kernel.org, AJvYcCWnLPdeIPjfSGN5qB9c8WKsDxIsjMakKHtgI8asuOqERIeKi947g33r/rICwD/o4Q9eTpktZTE7aP5Y@vger.kernel.org X-Gm-Message-State: AOJu0YxRDDWa8UKG3OLIpOlqSJnrdxMBpCpHQND2DKhGLpyfDLnlyvra dKsgr1umVLdUrBWLGOtNtOzN8iAAB87frDPZx1zmMR/xKsyABi8/ X-Google-Smtp-Source: AGHT+IG+u/HiorUNZvdcujWejFMP2LtxT7MumZe4fUaCUbX19p36C3evsUqvejXKc2kAeH+sCbER2Q== X-Received: by 2002:a17:907:6ea1:b0:a99:5a3d:3cb with SMTP id a640c23a62f3a-a9a69ba6422mr431511866b.8.1729453263186; Sun, 20 Oct 2024 12:41:03 -0700 (PDT) Received: from e8ff02ae9b18.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a91578129sm120576966b.186.2024.10.20.12.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:41:02 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 23/23] ARM: dts: socfpga: add Enclustra SoM dts files Date: Sun, 20 Oct 2024 19:40:28 +0000 Message-Id: <20241020194028.2272371-24-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com> References: <20241020194028.2272371-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the approach to set up a combination of Enclustra's SoM on a carrier board and corresponding boot-mode as single device-tree target. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/Makefile | 24 +++++++++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts | 16 +++++++++++++ 25 files changed, 408 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_st1_sdmmc.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/i= ntel/socfpga/Makefile index d95862e34..861880560 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,6 +2,30 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ + socfpga_arria10_mercury_aa1_pe1_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe1_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_st1_emmc.dtb \ + socfpga_arria10_mercury_aa1_st1_qspi.dtb \ + socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_emmc.dts new file mode 100644 index 000000000..b6cca0b5f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_qspi.dts new file mode 100644 index 000000000..6ad023477 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_p= e1_sdmmc.dts new file mode 100644 index 000000000..653c9a865 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_emmc.dts new file mode 100644 index 000000000..ae9c7c6a2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_qspi.dts new file mode 100644 index 000000000..c3a0c30a0 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_p= e3_sdmmc.dts new file mode 100644 index 000000000..dc1e1ad20 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_emmc.dts new file mode 100644 index 000000000..61d5e4c85 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_qspi.dts new file mode 100644 index 000000000..a3b99c9b1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_s= t1_sdmmc.dts new file mode 100644 index 000000000..5deb289e2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe1_emmc.dts new file mode 100644 index 000000000..85d6146da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe1_qspi.dts new file mode 100644 index 000000000..770ab680a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _pe1_sdmmc.dts new file mode 100644 index 000000000..990ca0fec --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe3_emmc.dts new file mode 100644 index 000000000..6c8fd5b0d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe3_qspi.dts new file mode 100644 index 000000000..329242607 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _pe3_sdmmc.dts new file mode 100644 index 000000000..1eb10b524 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= st1_emmc.dts new file mode 100644 index 000000000..8c97b5b3a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= st1_qspi.dts new file mode 100644 index 000000000..e6d14b22e --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _st1_sdmmc.dts new file mode 100644 index 000000000..beaeca94d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= pe1_qspi.dts new file mode 100644 index 000000000..6f79d9ed1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _pe1_sdmmc.dts new file mode 100644 index 000000000..b94bd8baf --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= pe3_qspi.dts new file mode 100644 index 000000000..51fc4a229 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _pe3_sdmmc.dts new file mode 100644 index 000000000..e4209209f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_s= t1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= st1_qspi.dts new file mode 100644 index 000000000..ab4549a0d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_s= t1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _st1_sdmmc.dts new file mode 100644 index 000000000..ebe62879c --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; --=20 2.25.1