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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a48903sm2276459f8f.37.2024.10.20.11.21.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 11:21:57 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/6] arm64: dts: exynos: Add clock management unit nodes Date: Sun, 20 Oct 2024 21:21:18 +0300 Message-ID: <20241020182121.377969-4-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> References: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clock management unit nodes for: - cmu_top, which provides muxes, divs and gates for other CMUs - cmu_peris, which provides clocks for GIC and MCT - cmu_fsys0, which provides clocks for USBDRD30 - cmu_fsys1, which provides clocks for MMC, UFS and PCIE - cmu_peric0, which provides clocks for UART_DBG, USI00 ~ USI03 - cmu_peric1, which provides clocks for SPI_CAM0/1, UART_BT, USI04 ~ USI13 Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/d= ts/exynos/exynos8895.dtsi index 223ebd482..802e135c4 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2024, Ivaylo Ivanov */ =20 +#include #include =20 / { @@ -159,6 +160,15 @@ chipid@10000000 { reg =3D <0x10000000 0x24>; }; =20 + cmu_peris: clock-controller@10010000 { + compatible =3D "samsung,exynos8895-cmu-peris"; + reg =3D <0x10010000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIS_BUS>; + clock-names =3D "oscclk", "bus"; + }; + gic: interrupt-controller@10201000 { compatible =3D "arm,gic-400"; reg =3D <0x10201000 0x1000>, @@ -173,24 +183,93 @@ gic: interrupt-controller@10201000 { #size-cells =3D <1>; }; =20 + cmu_peric0: clock-controller@10400000 { + compatible =3D "samsung,exynos8895-cmu-peric0"; + reg =3D <0x10400000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI00>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI01>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI02>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI03>; + clock-names =3D "oscclk", "bus", "uart_dbg", "usi00", + "usi01", "usi02", "usi03"; + }; + pinctrl_peric0: pinctrl@104d0000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x104d0000 0x1000>; interrupts =3D ; }; =20 + cmu_peric1: clock-controller@10800000 { + compatible =3D "samsung,exynos8895-cmu-peric1"; + reg =3D <0x10800000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM1>, + <&cmu_top CLK_DOUT_CMU_PERIC1_UART_BT>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI04>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI05>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI06>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI07>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI08>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI09>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI10>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI11>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI12>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI13>; + clock-names =3D "oscclk", "bus", "speedy2", "cam0", + "cam1", "uart_bt", "usi04", "usi05", + "usi06", "usi07", "usi08", "usi09", + "usi10", "usi11", "usi12", "usi13"; + }; + pinctrl_peric1: pinctrl@10980000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x10980000 0x1000>; interrupts =3D ; }; =20 + cmu_fsys0: clock-controller@11000000 { + compatible =3D "samsung,exynos8895-cmu-fsys0"; + reg =3D <0x11000000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS0_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS0_DPGTC>, + <&cmu_top CLK_DOUT_CMU_FSYS0_MMC_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS0_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS0_USBDRD30>; + clock-names =3D "oscclk", "bus", + "dpgtc", "mmc_embd", + "ufs_embd", "usbdrd30"; + }; + pinctrl_fsys0: pinctrl@11050000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x11050000 0x1000>; interrupts =3D ; }; =20 + cmu_fsys1: clock-controller@11400000 { + compatible =3D "samsung,exynos8895-cmu-fsys1"; + reg =3D <0x11400000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS1_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>, + <&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>, + <&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>; + clock-names =3D "oscclk", "bus", "mmc_card", + "pcie", "ufs_card"; + }; + pinctrl_fsys1: pinctrl@11430000 { compatible =3D "samsung,exynos8895-pinctrl"; reg =3D <0x11430000 0x1000>; @@ -213,6 +292,14 @@ pinctrl_busc: pinctrl@15a30000 { interrupts =3D ; }; =20 + cmu_top: clock-controller@15a80000 { + compatible =3D "samsung,exynos8895-cmu-top"; + reg =3D <0x15a80000 0x8000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>; + clock-names =3D "oscclk"; + }; + pmu_system_controller: system-controller@16480000 { compatible =3D "samsung,exynos8895-pmu", "samsung,exynos7-pmu", "syscon"; --=20 2.43.0