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[71.34.69.82]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e5ad355bebsm2337008a91.7.2024.10.20.19.36.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 19:36:54 -0700 (PDT) From: Drew Fustini Date: Sun, 20 Oct 2024 19:36:00 -0700 Subject: [PATCH net-next v4 1/3] dt-bindings: net: Add T-HEAD dwmac support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241020-th1520-dwmac-v4-1-c77acd33ccef@tenstorrent.com> References: <20241020-th1520-dwmac-v4-0-c77acd33ccef@tenstorrent.com> In-Reply-To: <20241020-th1520-dwmac-v4-0-c77acd33ccef@tenstorrent.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Coquelin , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Lunn , Drew Fustini Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, Drew Fustini , linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.14.1 From: Jisheng Zhang Add documentation to describe the DesginWare-based GMAC controllers in the T-HEAD TH1520 SoC. Signed-off-by: Jisheng Zhang Signed-off-by: Emil Renner Berthing [drew: rename compatible, add apb registers as second reg of gmac node, add clocks and interrupts poroperties] Signed-off-by: Drew Fustini Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/net/snps,dwmac.yaml | 1 + .../devicetree/bindings/net/thead,th1520-gmac.yaml | 115 +++++++++++++++++= ++++ MAINTAINERS | 1 + 3 files changed, 117 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 4e2ba1bf788c..474ade185033 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -99,6 +99,7 @@ properties: - snps,dwxgmac-2.10 - starfive,jh7100-dwmac - starfive,jh7110-dwmac + - thead,th1520-gmac =20 reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml b= /Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml new file mode 100644 index 000000000000..cea652ff6255 --- /dev/null +++ b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/thead,th1520-gmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 GMAC Ethernet controller + +maintainers: + - Drew Fustini + +description: | + The TH1520 GMAC is described in the TH1520 Peripheral Interface User Man= ual + https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs + + Features include + - Compliant with IEEE802.3 Specification + - IEEE 1588-2008 standard for precision networked clock synchronization + - Supports 10/100/1000Mbps data transfer rate + - Supports RGMII/MII interface + - Preamble and start of frame data (SFD) insertion in Transmit path + - Preamble and SFD deletion in the Receive path + - Automatic CRC and pad generation options for receive frames + - MDIO master interface for PHY device configuration and management + + The GMAC Registers consists of two parts + - APB registers are used to configure clock frequency/clock enable/clo= ck + direction/PHY interface type. + - AHB registers are use to configure GMAC core (DesignWare Core part). + GMAC core register consists of DMA registers and GMAC registers. + +select: + properties: + compatible: + contains: + enum: + - thead,th1520-gmac + required: + - compatible + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + items: + - enum: + - thead,th1520-gmac + - const: snps,dwmac-3.70a + + reg: + items: + - description: DesignWare GMAC IP core registers + - description: GMAC APB registers + + reg-names: + items: + - const: dwmac + - const: apb + + clocks: + items: + - description: GMAC main clock + - description: Peripheral registers interface clock + + clock-names: + items: + - const: stmmaceth + - const: pclk + + interrupts: + items: + - description: Combined signal for various interrupt events + + interrupt-names: + items: + - const: macirq + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - phy-mode + +unevaluatedProperties: false + +examples: + - | + gmac0: ethernet@e7070000 { + compatible =3D "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg =3D <0xe7070000 0x2000>, <0xec003000 0x1000>; + reg-names =3D "dwmac", "apb"; + clocks =3D <&clk 1>, <&clk 2>; + clock-names =3D "stmmaceth", "pclk"; + interrupts =3D <66>; + interrupt-names =3D "macirq"; + phy-mode =3D "rgmii-id"; + snps,fixed-burst; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,pbl =3D <32>; + phy-handle =3D <&phy0>; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index a858224b59d5..a16418d68383 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20066,6 +20066,7 @@ L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/pdp7/linux.git F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c --=20 2.34.1 From nobody Tue Nov 26 06:28:09 2024 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E85752110E for ; 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[71.34.69.82]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e5ad355bebsm2337008a91.7.2024.10.20.19.36.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 19:36:55 -0700 (PDT) From: Drew Fustini Date: Sun, 20 Oct 2024 19:36:01 -0700 Subject: [PATCH net-next v4 2/3] net: stmmac: Add glue layer for T-HEAD TH1520 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241020-th1520-dwmac-v4-2-c77acd33ccef@tenstorrent.com> References: <20241020-th1520-dwmac-v4-0-c77acd33ccef@tenstorrent.com> In-Reply-To: <20241020-th1520-dwmac-v4-0-c77acd33ccef@tenstorrent.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Coquelin , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Lunn , Drew Fustini Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, Drew Fustini , linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.14.1 From: Jisheng Zhang Add dwmac glue driver to support the DesignWare-based GMAC controllers on the T-HEAD TH1520 SoC. Signed-off-by: Jisheng Zhang [esmil: rename plat->interface -> plat->mac_interface, use devm_stmmac_probe_config_dt()] Signed-off-by: Emil Renner Berthing [drew: convert from stmmac_dvr_probe() to devm_stmmac_pltfr_probe(), convert register access from regmap to regular mmio] Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + drivers/net/ethernet/stmicro/stmmac/Kconfig | 10 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c | 268 ++++++++++++++++++= ++++ 4 files changed, 280 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a16418d68383..db05123389ac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20070,6 +20070,7 @@ F: Documentation/devicetree/bindings/net/thead,th15= 20-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c +F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h =20 diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 05cc07b8f48c..6658536a4e17 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -228,6 +228,16 @@ config DWMAC_SUN8I stmmac device driver. This driver is used for H3/A83T/A64 EMAC ethernet controller. =20 +config DWMAC_THEAD + tristate "T-HEAD dwmac support" + depends on OF && (ARCH_THEAD || COMPILE_TEST) + help + Support for ethernet controllers on T-HEAD RISC-V SoCs + + This selects the T-HEAD platform specific glue layer support for + the stmmac device driver. This driver is used for T-HEAD TH1520 + ethernet controller. + config DWMAC_IMX8 tristate "NXP IMX8 DWMAC support" default ARCH_MXC diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index c2f0e91f6bf8..d065634c6223 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_DWMAC_STI) +=3D dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) +=3D dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) +=3D dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) +=3D dwmac-sun8i.o +obj-$(CONFIG_DWMAC_THEAD) +=3D dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) +=3D dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) +=3D dwmac-intel-plat.o obj-$(CONFIG_DWMAC_LOONGSON1) +=3D dwmac-loongson1.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-thead.c new file mode 100644 index 000000000000..273efcc66890 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * T-HEAD DWMAC platform driver + * + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang + * + */ + +#include +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +#define GMAC_CLK_EN 0x00 +#define GMAC_TX_CLK_EN BIT(1) +#define GMAC_TX_CLK_N_EN BIT(2) +#define GMAC_TX_CLK_OUT_EN BIT(3) +#define GMAC_RX_CLK_EN BIT(4) +#define GMAC_RX_CLK_N_EN BIT(5) +#define GMAC_EPHY_REF_CLK_EN BIT(6) +#define GMAC_RXCLK_DELAY_CTRL 0x04 +#define GMAC_RXCLK_BYPASS BIT(15) +#define GMAC_RXCLK_INVERT BIT(14) +#define GMAC_RXCLK_DELAY_MASK GENMASK(4, 0) +#define GMAC_RXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) +#define GMAC_TXCLK_DELAY_CTRL 0x08 +#define GMAC_TXCLK_BYPASS BIT(15) +#define GMAC_TXCLK_INVERT BIT(14) +#define GMAC_TXCLK_DELAY_MASK GENMASK(4, 0) +#define GMAC_TXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) +#define GMAC_PLLCLK_DIV 0x0c +#define GMAC_PLLCLK_DIV_EN BIT(31) +#define GMAC_PLLCLK_DIV_MASK GENMASK(7, 0) +#define GMAC_PLLCLK_DIV_NUM(x) FIELD_PREP(GMAC_PLLCLK_DIV_MASK, (x)) +#define GMAC_GTXCLK_SEL 0x18 +#define GMAC_GTXCLK_SEL_PLL BIT(0) +#define GMAC_INTF_CTRL 0x1c +#define PHY_INTF_MASK BIT(0) +#define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1) +#define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0) +#define GMAC_TXCLK_OEN 0x20 +#define TXCLK_DIR_MASK BIT(0) +#define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0) +#define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1) + +#define GMAC_GMII_RGMII_RATE 125000000 +#define GMAC_MII_RATE 25000000 + +struct thead_dwmac { + struct plat_stmmacenet_data *plat; + void __iomem *apb_base; + struct device *dev; +}; + +static int thead_dwmac_set_phy_if(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac =3D plat->bsp_priv; + u32 phyif; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + phyif =3D PHY_INTF_MII_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + phyif =3D PHY_INTF_RGMII; + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + }; + + writel(phyif, dwmac->apb_base + GMAC_INTF_CTRL); + return 0; +} + +static int thead_dwmac_set_txclk_dir(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac =3D plat->bsp_priv; + u32 txclk_dir; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + txclk_dir =3D TXCLK_DIR_INPUT; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + txclk_dir =3D TXCLK_DIR_OUTPUT; + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + }; + + writel(txclk_dir, dwmac->apb_base + GMAC_TXCLK_OEN); + return 0; +} + +static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned= int mode) +{ + struct plat_stmmacenet_data *plat; + struct thead_dwmac *dwmac =3D priv; + unsigned long rate; + u32 div, reg; + + plat =3D dwmac->plat; + + switch (plat->mac_interface) { + /* For MII, rxc/txc is provided by phy */ + case PHY_INTERFACE_MODE_MII: + return; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + rate =3D clk_get_rate(plat->stmmac_clk); + if (!rate || rate % GMAC_GMII_RGMII_RATE !=3D 0 || + rate % GMAC_MII_RATE !=3D 0) { + dev_err(dwmac->dev, "invalid gmac rate %ld\n", rate); + return; + } + + writel(FIELD_PREP(GMAC_PLLCLK_DIV_EN, 0), dwmac->apb_base + GMAC_PLLCLK_= DIV); + + switch (speed) { + case SPEED_1000: + div =3D rate / GMAC_GMII_RGMII_RATE; + break; + case SPEED_100: + div =3D rate / GMAC_MII_RATE; + break; + case SPEED_10: + div =3D rate * 10 / GMAC_MII_RATE; + break; + default: + dev_err(dwmac->dev, "invalid speed %u\n", speed); + return; + } + + reg =3D FIELD_PREP(GMAC_PLLCLK_DIV_EN, 1) | + FIELD_PREP(GMAC_PLLCLK_DIV_MASK, GMAC_PLLCLK_DIV_NUM(div)); + writel(reg, dwmac->apb_base + GMAC_PLLCLK_DIV); + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return; + } +} + +static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac =3D plat->bsp_priv; + u32 reg; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + reg =3D GMAC_RX_CLK_EN | GMAC_TX_CLK_EN; + break; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* use pll */ + writel(GMAC_GTXCLK_SEL_PLL, dwmac->apb_base + GMAC_GTXCLK_SEL); + reg =3D GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN | + GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN; + break; + + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + } + + writel(reg, dwmac->apb_base + GMAC_CLK_EN); + return 0; +} + +static int thead_dwmac_init(struct platform_device *pdev, void *priv) +{ + struct thead_dwmac *dwmac =3D priv; + int ret; + + ret =3D thead_dwmac_set_phy_if(dwmac->plat); + if (ret) + return ret; + + ret =3D thead_dwmac_set_txclk_dir(dwmac->plat); + if (ret) + return ret; + + writel(GMAC_RXCLK_DELAY_VAL(0), dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL); + writel(GMAC_TXCLK_DELAY_VAL(0), dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL); + + return thead_dwmac_enable_clk(dwmac->plat); +} + +static int thead_dwmac_probe(struct platform_device *pdev) +{ + struct stmmac_resources stmmac_res; + struct plat_stmmacenet_data *plat; + struct thead_dwmac *dwmac; + void __iomem *apb; + int ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to get resources\n"); + + plat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat)) + return dev_err_probe(&pdev->dev, PTR_ERR(plat), + "dt configuration failed\n"); + + dwmac =3D devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); + if (!dwmac) + return -ENOMEM; + + apb =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(apb)) + return dev_err_probe(&pdev->dev, PTR_ERR(apb), + "Failed to remap gmac apb registers\n"); + + dwmac->dev =3D &pdev->dev; + dwmac->plat =3D plat; + dwmac->apb_base =3D apb; + plat->bsp_priv =3D dwmac; + plat->fix_mac_speed =3D thead_dwmac_fix_speed; + plat->init =3D thead_dwmac_init; + + return devm_stmmac_pltfr_probe(pdev, plat, &stmmac_res); +} + +static const struct of_device_id thead_dwmac_match[] =3D { + { .compatible =3D "thead,th1520-gmac" }, + { } +}; +MODULE_DEVICE_TABLE(of, thead_dwmac_match); + +static struct platform_driver thead_dwmac_driver =3D { + .probe =3D thead_dwmac_probe, + .driver =3D { + .name =3D "thead-dwmac", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D thead_dwmac_match, + }, +}; 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[71.34.69.82]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e5ad355bebsm2337008a91.7.2024.10.20.19.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 19:36:56 -0700 (PDT) From: Drew Fustini Date: Sun, 20 Oct 2024 19:36:02 -0700 Subject: [PATCH net-next v4 3/3] riscv: dts: thead: Add TH1520 ethernet nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241020-th1520-dwmac-v4-3-c77acd33ccef@tenstorrent.com> References: <20241020-th1520-dwmac-v4-0-c77acd33ccef@tenstorrent.com> In-Reply-To: <20241020-th1520-dwmac-v4-0-c77acd33ccef@tenstorrent.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Coquelin , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Lunn , Drew Fustini Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, Drew Fustini , linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.14.1 From: Emil Renner Berthing Add gmac, mdio, and phy nodes to enable the gigabit Ethernet ports on the BeagleV Ahead and Sipeed Lichee Pi 4a boards. Signed-off-by: Emil Renner Berthing [drew: change apb registers from syscon to second reg of gmac node, add phy reset delay properties for beaglev ahead] Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 91 ++++++++++++++++ .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 119 +++++++++++++++++= ++++ arch/riscv/boot/dts/thead/th1520.dtsi | 50 +++++++++ 3 files changed, 260 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 86feb3df02c8..21c33f165ba9 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -15,6 +15,7 @@ / { compatible =3D "beagle,beaglev-ahead", "thead,th1520"; =20 aliases { + ethernet0 =3D &gmac0; gpio0 =3D &gpio0; gpio1 =3D &gpio1; gpio2 =3D &gpio2; @@ -98,6 +99,25 @@ &emmc { status =3D "okay"; }; =20 +&gmac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_pins>; + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <22 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&gpio3 21 GPIO_ACTIVE_LOW>; + reset-delay-us =3D <10000>; + reset-post-delay-us =3D <50000>; + }; +}; + &padctrl_aosys { led_pins: led-0 { led-pins { @@ -116,6 +136,77 @@ led-pins { }; =20 &padctrl0_apsys { + gmac0_pins: gmac0-0 { + tx-pins { + pins =3D "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <25>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + mdc-pins { + pins =3D "GMAC0_MDC"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + mdio-pins { + pins =3D "GMAC0_MDIO"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + + phy-reset-pins { + pins =3D "GMAC0_COL"; /* GPIO3_21 */ + bias-disable; + drive-strength =3D <3>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + phy-interrupt-pins { + pins =3D "GMAC0_CRS"; /* GPIO3_22 */ + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <1>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pins =3D "UART0_TXD"; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 724d9645471d..8e76b63e0100 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -11,6 +11,11 @@ / { model =3D "Sipeed Lichee Module 4A"; compatible =3D "sipeed,lichee-module-4a", "thead,th1520"; =20 + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + }; + memory@0 { device_type =3D "memory"; reg =3D <0x0 0x00000000 0x2 0x00000000>; @@ -45,6 +50,22 @@ &emmc { status =3D "okay"; }; =20 +&gmac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_pins>, <&mdio0_pins>; + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; +}; + +&gmac1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1_pins>; + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; +}; + &gpio0 { gpio-line-names =3D "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", @@ -78,6 +99,104 @@ &gpio3 { "GPIO10"; }; =20 +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + }; + + phy1: ethernet-phy@2 { + reg =3D <2>; + }; +}; + +&padctrl0_apsys { + gmac0_pins: gmac0-0 { + tx-pins { + pins =3D "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <25>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + gmac1_pins: gmac1-0 { + tx-pins { + pins =3D "GPIO2_18", /* GMAC1_TX_CLK */ + "GPIO2_20", /* GMAC1_TXEN */ + "GPIO2_21", /* GMAC1_TXD0 */ + "GPIO2_22", /* GMAC1_TXD1 */ + "GPIO2_23", /* GMAC1_TXD2 */ + "GPIO2_24"; /* GMAC1_TXD3 */ + function =3D "gmac1"; + bias-disable; + drive-strength =3D <25>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "GPIO2_19", /* GMAC1_RX_CLK */ + "GPIO2_25", /* GMAC1_RXDV */ + "GPIO2_30", /* GMAC1_RXD0 */ + "GPIO2_31", /* GMAC1_RXD1 */ + "GPIO3_0", /* GMAC1_RXD2 */ + "GPIO3_1"; /* GMAC1_RXD3 */ + function =3D "gmac1"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + mdio0_pins: mdio0-0 { + mdc-pins { + pins =3D "GMAC0_MDC"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + mdio-pins { + pins =3D "GMAC0_MDIO"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; +}; + &sdio0 { bus-width =3D <4>; max-frequency =3D <198000000>; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index cd835aea07d2..acfe030e803a 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -223,6 +223,12 @@ aonsys_clk: clock-73728000 { #clock-cells =3D <0>; }; =20 + stmmac_axi_config: stmmac-axi-config { + snps,wr_osr_lmt =3D <15>; + snps,rd_osr_lmt =3D <15>; + snps,blen =3D <0 0 64 32 0 0 0>; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -274,6 +280,50 @@ uart0: serial@ffe7014000 { status =3D "disabled"; }; =20 + gmac1: ethernet@ffe7060000 { + compatible =3D "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg =3D <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; + reg-names =3D "dwmac", "apb"; + interrupts =3D <67 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq"; + clocks =3D <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>; + clock-names =3D "stmmaceth", "pclk"; + snps,pbl =3D <32>; + snps,fixed-burst; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <32>; + snps,axi-config =3D <&stmmac_axi_config>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + gmac0: ethernet@ffe7070000 { + compatible =3D "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg =3D <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; + reg-names =3D "dwmac", "apb"; + interrupts =3D <66 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq"; + clocks =3D <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>; + clock-names =3D "stmmaceth", "pclk"; + snps,pbl =3D <32>; + snps,fixed-burst; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <32>; + snps,axi-config =3D <&stmmac_axi_config>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + emmc: mmc@ffe7080000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7080000 0x0 0x10000>; --=20 2.34.1