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([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:48:06 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 09/12] arm64: dts: renesas: r9a08g045: Add RTC node Date: Sat, 19 Oct 2024 11:47:35 +0300 Message-Id: <20241019084738.3370489-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v4: - dropped the assigned-clocks, assigned-clock-parents properties as they fit better on vbattb node - moved the RTC close to serial node for ordering Changes in v3: - added CPG clock, power domain, reset - and assigned-clocks, assigned-clock-parents to configure the VBATTCLK - included dt-bindings/clock/r9a08g045-vbattb.h Changes in v2: - updated compatibles arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 827db9f61802..14e105de2f08 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -7,6 +7,7 @@ =20 #include #include +#include =20 / { compatible =3D "renesas,r9a08g045"; @@ -72,6 +73,20 @@ scif0: serial@1004b800 { status =3D "disabled"; }; =20 + rtc: rtc@1004ec00 { + compatible =3D "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg =3D <0 0x1004ec00 0 0x400>; + interrupts =3D , + , + ; + interrupt-names =3D "alarm", "period", "carry"; + clocks =3D <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK= >; + clock-names =3D "bus", "counter"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G045_VBAT_BRESETN>; + status =3D "disabled"; + }; + vbattb: clock-controller@1005c000 { compatible =3D "renesas,r9a08g045-vbattb"; reg =3D <0 0x1005c000 0 0x1000>; --=20 2.39.2