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([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.47.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:47:50 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 01/12] dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC Date: Sat, 19 Oct 2024 11:47:27 +0300 Message-Id: <20241019084738.3370489-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The RTC and VBATTB don't share the MSTOP control bit (but only the bus clock and the reset signal). As the MSTOP control is modeled though power domains add power domain ID for the RTC device available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- Changes in v4: - none; this patch is new; after discussions w/ HW team internally it has established that the RTC and VBATTB shares different MSTOP settings include/dt-bindings/clock/r9a08g045-cpg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-binding= s/clock/r9a08g045-cpg.h index 8281e9caf3a9..311521fe4b59 100644 --- a/include/dt-bindings/clock/r9a08g045-cpg.h +++ b/include/dt-bindings/clock/r9a08g045-cpg.h @@ -308,5 +308,6 @@ #define R9A08G045_PD_DDR 64 #define R9A08G045_PD_TZCDDR 65 #define R9A08G045_PD_OTFDE_DDR 66 +#define R9A08G045_PD_RTC 67 =20 #endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */ --=20 2.39.2 From nobody Tue Nov 26 08:54:06 2024 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2A981DE8AA for ; Sat, 19 Oct 2024 08:47:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327678; cv=none; b=dP0oA5JKeBQp8j7TAmun6PL+lwxnraXWI32GvLb4FA5FO2CXQ7XSyvpQOVj1UHsWBDPTrssD0lYn6qLY2l+OLD160mymnVSMVkGoWuNj+DEZ9P3oU3Mu/K0Y08XfE5Lct/TqDsKoUqkulFNmSa0UA/AUvN7DDNdCFIN+jVxNuws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327678; c=relaxed/simple; bh=bBMfGXWqc59VvywxMcrKKTmoSCTWD+93WcF84hRM7k8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NsyPHS8HJNH+Vp/1hqjpC8LcwM8Gs9KPTtA/T+0xxfUzZrIsy3o4bEtEyfusOR7C9qM4HVKqtOW98oT7s+NgdvHvfHCnw23GtcLKf8xfYa0jXxPbI62NCWTVX+3xwQgqDAoJMkDeeX2zqfLYTMqucLluGUsnnqzEBezbWv+DSS4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=B9Zsvemh; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="B9Zsvemh" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-43162cf1eaaso16525935e9.0 for ; Sat, 19 Oct 2024 01:47:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1729327673; x=1729932473; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=su/gA2vZm43OZPNrjqU3H6dnR7lMMIQDMznyw802HoA=; b=B9ZsvemhVN2m5H87AdwSJGATcbgDuJzln1j6tjVeHE97f7YZZuIIi3yDODM/oqSgPW FFoDBK0NCSYvQnYb5hWR71czA/CGrXJJtcK8XD8POdaNJ0j7H3JUVjZZc9xS0vqU8qsB Y1znKXz52RCccAULtk4gntj5J62KqU7eQpedKI9BPMSPWVlp32+yxmw+fLnLZfOTfRAS Fgg05Tl3fdd3ZKS/wCUIF3/O91cUbU44yA0LXhBok8fuRzDiCPe7ptEy4drbzjCHTkr+ dUdsxvSbgWcmIkJ+FTQJeJYpvQF9kbXgeK5O3DTjmgrIITRFSa8MAEjkTYMSkFtjZaYe ZKpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729327673; x=1729932473; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=su/gA2vZm43OZPNrjqU3H6dnR7lMMIQDMznyw802HoA=; b=wUvo6Gu5WrSxXAliJyNzV+viDNIKSkPoSYgcv2Ll2WLuijIlJt4yd6yAkcITaOzbRf U6T6pqw69ARRmzXRu1fhzH47dH9FZWrCD02OYrfFwZRyNWXS9D0cgsJCn5KMtzv44GrP r3bS9gNBXeTx2XqoJzZIm+m8usKu0A7u42oFB9OzjCstJ9Gb5usxKI99GKSryMw5da/L TTxEOUrwuURYTsOI4fNS+1kx8NJPPUBTZSdnPplZuugnQx5pSKY9zy6HXVdQmgh4XPIQ QGLkUq4dGrs/NSZ5bVGVl8uJ7S0xLf/i4r4INaykyh2OM8vx1xV4BjTlXCLi1HhMQcXy R7Eg== X-Forwarded-Encrypted: i=1; AJvYcCVJUTjRs9hUiTZQBDLwq/Er1r5WmySGuMavjM//H1irdns9Dd3a/vzXfnaIk+xNyJE+MFglZ8Gg3JDaIQE=@vger.kernel.org X-Gm-Message-State: AOJu0Yw576guAOR5MF86SkUmJ5evZtcxPOzwVIhnynR/Ki7GVplnsDGp poS1r57uVBAyszTVslRPGgH6WoO218ojgKjuuvUsEUPKNhKLRJRCp7mx/aqEI4s= X-Google-Smtp-Source: AGHT+IG77C1AJn6G4KHr/98gwp5TO2FyaZmbbg9kHUJJo7AxaVAri13cwdvUg7gZGWh/UvC983QSQg== X-Received: by 2002:a05:600c:12c9:b0:431:555d:e184 with SMTP id 5b1f17b1804b1-43161686b11mr51728705e9.25.1729327672912; Sat, 19 Oct 2024 01:47:52 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:47:52 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 02/12] clk: renesas: r9a08g045: Add power domain for RTC Date: Sat, 19 Oct 2024 11:47:28 +0300 Message-Id: <20241019084738.3370489-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The RTC and VBATTB don't share the MSTOP control bit (but only the bus clock and the reset signal). As the MSTOP control is modeled though power domains add power domain support for the RTC device available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v4: - none; this patch is new drivers/clk/renesas/r9a08g045-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 213499fc8fb5..97ade53f79c3 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -304,6 +304,9 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08= g045_pm_domains[] =3D { DEF_PD("vbat", R9A08G045_PD_VBAT, DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), RZG2L_PD_F_ALWAYS_ON), + DEF_PD("rtc", R9A08G045_PD_RTC, + DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(7)), + RZG2L_PD_F_NONE), }; =20 const struct rzg2l_cpg_info r9a08g045_cpg_info =3D { --=20 2.39.2 From nobody Tue Nov 26 08:54:06 2024 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F7F81DEFE5 for ; Sat, 19 Oct 2024 08:47:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327678; cv=none; b=qDZldR4iTROBmUMMj/Jqvh39PvHrNAQNtEPum5ARPwUzNLFoQTqGk+8fj00kBEVxEGdGCcOlv/ZSOWFEqZLuTXe0XVy0/PqeRc2WtFTOvDHR+65TOfqpkACNc13Y1yr3nSpj/VuseUcl9z4GkR9zeaXyMUj9aJ83iyyMI8FbXfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327678; c=relaxed/simple; bh=Sn7ORRCE5Ncj/dbTqXqX5LKB2nwx75LDE9TXAGdyEJE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oTG83DSOW4EtdjqVoONj8OSTKoBd7JvbbMko9NpylggN09uC5zCmiptOYdCouXqYiU/iQ1csDslKGxvmVXfxOJ++57IQju+4M+cM2STmuyA3p0izHoWw/l4pr4AQ+XIRy/bQM9IBW7a838Jxpv/HNZy9EsF421zxWA5Dj6Lg+cU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=Kv8rXjNU; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="Kv8rXjNU" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4305413aec9so30608455e9.2 for ; Sat, 19 Oct 2024 01:47:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1729327674; x=1729932474; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JBq7RVkEl9Cf/cK4z2v6tILMX3KuhnMuVzHgHuEOrQc=; b=Kv8rXjNUHFArXY73JuwJEGfBLwjFRtjvmHOlLtZue4H+dhPduQ/qmZgOTR33+EXc99 Z1RDxMwnI/qD6PCbID6f24B9J9gufQ/gvMLcf+U/+iwoeMqSZJDIm4hcEXStmkC5n6Ze x557IzbNtFIcOVt7YhKphZMxyRlm9r/5HZw75esDZRC3n7TZBNpNmEv+W+UdgV45JpJQ Mxrdgwznkj93QoymsbWbdw/DegfH2S4pW5ITlQPL/4JaYd3z5NY/+rzwChNmmpNvEa32 Ng4w2iNDtvD7EQdxu528HJ6+GXWXAHzKUVUjC9KIlChjHaBZi9AL4mJuSliar3+Cievy XTnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729327674; x=1729932474; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JBq7RVkEl9Cf/cK4z2v6tILMX3KuhnMuVzHgHuEOrQc=; b=nlVGz57uIF/jgkjYOJ5c9b8aCacsp4RiMMK/14lSEgK1yxibGdVqtyPPW0tYvhQFqX IzujGZQYJlE4ay5X7eDJKYl5nogbfv6bxZaNmA8Y7ZEaOQOnasc/vfQDWK83jETHkEqj JekQ+zFgCjfKgqoEAeKkCcF/zBu+WE+2fvvY1irdSMX6DPyDehYGmzZiYtbpB6VaIO2P meHaDTEY4liRVkB9VzrkgG+OKjzO3uiNQcMNqVvivH2lCeTJeKNEjLLSp3VSJTBOkjyD lvdPV/lSa1Wu+vH49mheWbwPPc1YpXoUx+Ay9sxfgZjvUXfANGvMgneHG/bt50J1QyTQ xtuQ== X-Forwarded-Encrypted: i=1; AJvYcCWulQVrvXWaHjrgjRhnoh6FmBycdKq7meY9p5OnSs0cpUYqwuAAKc66nP/gTGbPtsQaiAUcTlGW9juDIoQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwbiL4fiE7QfYDYEfHj4HH4kVstDJPNJvcJiRVPIY/zW7EDYDdI sTfzYs0sugY75tCgcJE7GzA6gFfdI51tFcuNjWgfJshxlPCHUBjxiI8/zof7elw= X-Google-Smtp-Source: AGHT+IFMgmHe/BVhwnaOPrKExZFyFNJOjcLNAMmu8ASdWjGhVkbiW4b15qBipXXbiOu4w50XS+X9wQ== X-Received: by 2002:a05:600c:474e:b0:431:4880:3120 with SMTP id 5b1f17b1804b1-4316162906dmr41326615e9.11.1729327674552; Sat, 19 Oct 2024 01:47:54 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:47:54 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 03/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Date: Sat, 19 Oct 2024 11:47:29 +0300 Message-Id: <20241019084738.3370489-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. The VBATTB controller controls the clock for the RTC on the Renesas RZ/G3S. The HW block diagram for the clock logic is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ ,/ One could connect as input to this HW block either a crystal or an external clock device. After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: input-xtal xbyp xc mux vbattclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. This allows select the input of the mux based on the type of the connected input clock: - if the 32768 crystal is connected as input for the VBATTB, the input of the mux should be xc - if an external clock device is connected as input for the VBATTB the input of the mux should be xbyp Add bindings for the VBATTB controller. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v4: - squashed with patch "Add clock IDs for the VBATTB controller" from v3 - removed "oscillator" word from commit description - added assigned-clocks, assigned-clock-parents to the documentation example - used clock-controller for the node name - used "quartz-load-femtofarads" property for the load capacitance - renamed include/dt-bindings/clock/r9a08g045-vbattb.h to include/dt-bindings/clock/renesas,r9a08g045-vbattb.h Changes in v3: - moved the file to clock dt bindings directory as it is the only functionality supported at the moment; the other functionalities (tamper detector, SRAM) are offered though register spreaded though the address space of the VBATTB IP and not actually individual devices; the other functionalities are not planned to be supported soon and if they will be I think they fit better on auxiliary bus than MFD - dropped interrupt names as requested in the review process - dropped the inner node for clock controller - added #clock-cells - added rtx clock - updated description for renesas,vbattb-load-nanofarads - included dt-bindings/interrupt-controller/irq.h in examples section Changes in v2: - changed file name and compatible - updated title, description sections - added clock controller part documentation and drop dedicated file for it included in v1 - used items to describe interrupts, interrupt-names, clocks, clock-names, resets - dropped node labels and status - updated clock-names for clock controller to cope with the new logic on detecting the necessity to setup bypass .../clock/renesas,r9a08g045-vbattb.yaml | 83 +++++++++++++++++++ .../clock/renesas,r9a08g045-vbattb.h | 13 +++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g0= 45-vbattb.yaml create mode 100644 include/dt-bindings/clock/renesas,r9a08g045-vbattb.h diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbat= tb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.= yaml new file mode 100644 index 000000000000..4c78b4b1fcd0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + interrupts: + items: + - description: tamper detector interrupt + + clocks: + items: + - description: VBATTB module clock + - description: RTC input clock (crystal or external clock device) + + clock-names: + items: + - const: bclk + - const: rtx + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + quartz-load-femtofarads: + description: load capacitance of the on board crystal + enum: [ 4000, 7000, 9000, 12500 ] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + clock-controller@1005c000 { + compatible =3D "renesas,r9a08g045-vbattb"; + reg =3D <0x1005c000 0x1000>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names =3D "bclk", "rtx"; + assigned-clocks =3D <&vbattb VBATTB_MUX>; + assigned-clock-parents =3D <&vbattb VBATTB_XC>; + #clock-cells =3D <1>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G045_VBAT_BRESETN>; + quartz-load-femtofarads =3D <12500>; + }; diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include= /dt-bindings/clock/renesas,r9a08g045-vbattb.h new file mode 100644 index 000000000000..67774eafad06 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ + +#define VBATTB_XC 0 +#define VBATTB_XBYP 1 +#define VBATTB_MUX 2 +#define VBATTB_VBATTCLK 3 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */ --=20 2.39.2 From nobody Tue Nov 26 08:54:06 2024 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B5931DF96D for ; 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([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:47:55 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 04/12] clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw() Date: Sat, 19 Oct 2024 11:47:30 +0300 Message-Id: <20241019084738.3370489-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add devm_clk_hw_register_gate_parent_hw() macro to allow registering devres managed gate clocks providing struct clk_hw object as parent. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v4: - collected tags Changes in v3: - none; this patch is new include/linux/clk-provider.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 4a537260f655..824b62059364 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -608,6 +608,24 @@ struct clk *clk_register_gate(struct device *dev, cons= t char *name, __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_hw - register a gate clock with the cl= ock + * framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_hw: pointer to parent clk + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, = \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ + NULL, (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) /** * devm_clk_hw_register_gate_parent_data - register a gate clock with the * clock framework --=20 2.39.2 From nobody Tue Nov 26 08:54:06 2024 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 186421DFDB0 for ; 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([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:47:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 05/12] clk: renesas: clk-vbattb: Add VBATTB clock driver Date: Sat, 19 Oct 2024 11:47:31 +0300 Message-Id: <20241019084738.3370489-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal or an external clock device. The HW block diagram for the clock generator is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ , After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: vbattb-xtal xbyp xc mux vbattbclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. If the crystal is connected on RTXIN, RTXOUT pins the XC will be selected as mux input. If an external clock device is connected on RTXIN, RTXOUT pins the XBYP will be selected as mux input. The load capacitance of the internal crystal can be configured with renesas,vbattb-load-nanofarads DT property. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v4: - dropped oscillator from patch description - s/on-board/internal in patch description - updated dt-binding included file name in the driver as it has been renamed to include/dt-bindings/clock/renesas,r9a08g045-vbattb.h - dropped the "_BIT" from driver macros - used "quartz-load-femtofarads" dt property instead of adding a new one - register the "vbattclk" as critical clock as this feeds the RTC counter logic and it needs to stay on from the moment the RTC is configured; along with it, added a comment to express this. Changes in v3: - updated patch description - dropped dependency on MFD_RENESAS_VBATTB as now there is no driver built under this flag - dropped include/clk.h - added pm_runtime and reset control support - updated register offsets - registered 4 clocks: xc, xbyp, mux, vbattclk using generic clock drivers - added MODULE_DEVICE_TABLE() Changes in v2: - updated patch description - added vendor name in Kconfig flag - used cleanup.h lock helpers - dropped the MFD code - updated registers offsets - added vbattb_clk_update_bits() and used it where possible - added vbattb_clk_need_bypass() to detect the bypass setup necessity - changed the compatible and driver names drivers/clk/renesas/Kconfig | 4 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-vbattb.c | 205 +++++++++++++++++++++++++++++++ 3 files changed, 210 insertions(+) create mode 100644 drivers/clk/renesas/clk-vbattb.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 76791a1c50ac..4e835a3f1ab4 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -237,6 +237,10 @@ config CLK_RZV2H bool "RZ/V2H(P) family clock support" if COMPILE_TEST select RESET_CONTROLLER =20 +config CLK_RENESAS_VBATTB + bool "Renesas VBATTB clock controller" + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 23d2e26051c8..82efaa835ac7 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_CLK_RZV2H) +=3D rzv2h-cpg.o obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) +=3D renesas-cpg-mssr.o obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) +=3D clk-mstp.o obj-$(CONFIG_CLK_RENESAS_DIV6) +=3D clk-div6.o +obj-$(CONFIG_CLK_RENESAS_VBATTB) +=3D clk-vbattb.o diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vba= ttb.c new file mode 100644 index 000000000000..ff9d1ead455c --- /dev/null +++ b/drivers/clk/renesas/clk-vbattb.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB clock driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define VBATTB_BKSCCR 0x1c +#define VBATTB_BKSCCR_SOSEL 6 +#define VBATTB_SOSCCR2 0x24 +#define VBATTB_SOSCCR2_SOSTP2 0 +#define VBATTB_XOSCCR 0x30 +#define VBATTB_XOSCCR_OUTEN 16 +#define VBATTB_XOSCCR_XSEL GENMASK(1, 0) +#define VBATTB_XOSCCR_XSEL_4_PF 0x0 +#define VBATTB_XOSCCR_XSEL_7_PF 0x1 +#define VBATTB_XOSCCR_XSEL_9_PF 0x2 +#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 + +/** + * struct vbattb_clk - VBATTB clock data structure + * @base: base address + * @lock: lock + */ +struct vbattb_clk { + void __iomem *base; + spinlock_t lock; +}; + +static int vbattb_clk_validate_load_capacitance(u32 *reg_lc, u32 of_lc) +{ + switch (of_lc) { + case 4000: + *reg_lc =3D VBATTB_XOSCCR_XSEL_4_PF; + break; + case 7000: + *reg_lc =3D VBATTB_XOSCCR_XSEL_7_PF; + break; + case 9000: + *reg_lc =3D VBATTB_XOSCCR_XSEL_9_PF; + break; + case 12500: + *reg_lc =3D VBATTB_XOSCCR_XSEL_12_5_PF; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void vbattb_clk_action(void *data) +{ + struct device *dev =3D data; + struct reset_control *rstc =3D dev_get_drvdata(dev); + int ret; + + ret =3D reset_control_assert(rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret =3D pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); + + of_clk_del_provider(dev->of_node); +} + +static int vbattb_clk_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct clk_parent_data parent_data =3D {}; + struct clk_hw_onecell_data *clk_data; + const struct clk_hw *parent_hws[2]; + struct device *dev =3D &pdev->dev; + struct reset_control *rstc; + struct vbattb_clk *vbclk; + u32 of_lc, reg_lc; + struct clk_hw *hw; + /* 4 clocks are exported: VBATTB_XC, VBATTB_XBYP, VBATTB_MUX, VBATTB_VBAT= TCLK. */ + u8 num_clks =3D 4; + int ret; + + /* Default to 4pF as this is not needed if external clock device is conne= cted. */ + of_lc =3D 4000; + of_property_read_u32(np, "quartz-load-femtofarads", &of_lc); + + ret =3D vbattb_clk_validate_load_capacitance(®_lc, of_lc); + if (ret) + return ret; + + vbclk =3D devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL); + if (!vbclk) + return -ENOMEM; + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, num_clks), GFP_= KERNEL); + if (!clk_data) + return -ENOMEM; + clk_data->num =3D num_clks; + + vbclk->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vbclk->base)) + return PTR_ERR(vbclk->base); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + rstc =3D devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret =3D reset_control_deassert(rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, rstc); + ret =3D devm_add_action_or_reset(dev, vbattb_clk_action, dev); + if (ret) + return ret; + + spin_lock_init(&vbclk->lock); + + parent_data.fw_name =3D "rtx"; + hw =3D devm_clk_hw_register_gate_parent_data(dev, "xc", &parent_data, 0, + vbclk->base + VBATTB_SOSCCR2, + VBATTB_SOSCCR2_SOSTP2, + CLK_GATE_SET_TO_DISABLE, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XC] =3D hw; + + hw =3D devm_clk_hw_register_fixed_factor_fwname(dev, np, "xbyp", "rtx", 0= , 1, 1); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XBYP] =3D hw; + + parent_hws[0] =3D clk_data->hws[VBATTB_XC]; + parent_hws[1] =3D clk_data->hws[VBATTB_XBYP]; + hw =3D devm_clk_hw_register_mux_parent_hws(dev, "mux", parent_hws, 2, 0, + vbclk->base + VBATTB_BKSCCR, + VBATTB_BKSCCR_SOSEL, + 1, 0, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_MUX] =3D hw; + + /* Set load capacitance before registering the VBATTCLK clock. */ + scoped_guard(spinlock, &vbclk->lock) { + u32 val =3D readl_relaxed(vbclk->base + VBATTB_XOSCCR); + + val &=3D ~VBATTB_XOSCCR_XSEL; + val |=3D reg_lc; + writel_relaxed(val, vbclk->base + VBATTB_XOSCCR); + } + + /* This feeds the RTC counter clock and it needs to stay on. */ + hw =3D devm_clk_hw_register_gate_parent_hw(dev, "vbattclk", hw, CLK_IS_CR= ITICAL, + vbclk->base + VBATTB_XOSCCR, + VBATTB_XOSCCR_OUTEN, 0, + &vbclk->lock); + + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_VBATTCLK] =3D hw; + + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); +} + +static const struct of_device_id vbattb_clk_match[] =3D { + { .compatible =3D "renesas,r9a08g045-vbattb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vbattb_clk_match); + +static struct platform_driver vbattb_clk_driver =3D { + .driver =3D { + .name =3D "renesas-vbattb-clk", + .of_match_table =3D vbattb_clk_match, + }, + .probe =3D vbattb_clk_probe, +}; +module_platform_driver(vbattb_clk_driver); + +MODULE_DESCRIPTION("Renesas VBATTB Clock Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); --=20 2.39.2 From nobody Tue Nov 26 08:54:06 2024 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78A741E009A for ; Sat, 19 Oct 2024 08:48:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327685; cv=none; b=ch9ViMgI++FJ1hRKw79P/BaqPH+bRAUNcXeS2cRlFz8Ime019DBwd25Nxy9MqoEs0fTRTn/X8xfuQTsk3l8uhxV81g+rXmjkt6QEP+hIkD/Hn1Jsy4524g9hujDLS/+8x5Ag744fz1Uc1UIvcxmUtQoGzAxe8dcibUBd40PAKv8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327685; c=relaxed/simple; bh=0nyGTQ0S9tANce3jH3/GPn/BPO9i8PA8ogV7QfAeZgo=; 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([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.47.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:48:00 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 06/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Date: Sat, 19 Oct 2024 11:47:32 +0300 Message-Id: <20241019084738.3370489-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. The RTC IP available on Renesas RZ/V2H is almost identical with the one found on Renesas RZ/G3S (it misses the time capture functionality which is not yet implemented on proposed driver). For this, added also a generic compatible that will be used at the moment as fallback for both RZ/G3S and RZ/V2H. Reviewed-by: Rob Herring (Arm) Signed-off-by: Claudiu Beznea --- Changes in v4: - collected tags - dropped the assigned-clocks, assigned-clock-parents properties from the example, along with r9a08g045-vbattb.h inclusion; these were moved to the VBATTB example as it fits better in there since these are related to the VBATTB but not to the RTC; Rob, I haven't dropped your Rb tag for this; please let me know if you consider it otherwise. Changes in v3: - added RTC bus clock, reset and power-domain; it has been detected by reverse engineering that RTC and VBATTB clock, reset and power domain are shared; HW manual doesn't mention it - updated example with these and with assigned-clock properties needed to configure the VBATTCLK MUX with proper parent - updated example section with dt-bindings/clock/r9a08g045-cpg.h and dt-bindings/clock/r9a08g045-vbattb.h includes - for all these, dropped Conor's Rb tag Changes in v2: - updated patch description and title - included reference to rtc.yaml - updated compatible list with a generic compatible as explained in patch description; with this the node in examples section has also been updated - used items to describe interrupts, interrupt-names, clock, clock-names - updated title section .../bindings/rtc/renesas,rz-rtca3.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.= yaml diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/= Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml new file mode 100644 index 000000000000..f1e9d01633c7 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RTCA-3 Real Time Clock + +maintainers: + - Claudiu Beznea + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a08g045-rtca3 # RZ/G3S + - const: renesas,rz-rtca3 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Alarm interrupt + - description: Periodic interrupt + - description: Carry interrupt + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + items: + - description: RTC bus clock + - description: RTC counter clock + + clock-names: + items: + - const: bus + - const: counter + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + rtc@1004ec00 { + compatible =3D "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; 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([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:48:01 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea , kernel test robot Subject: [PATCH v4 07/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Date: Sat, 19 Oct 2024 11:47:33 +0300 Message-Id: <20241019084738.3370489-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Claudiu Beznea The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count mode and binary count mode (selectable though RCR2.CNTMD) capabilities, alarm capabilities, clock error correction capabilities. It can generate alarm, period, carry interrupts. Add a driver for RTCA-3 IP. The driver implements calendar count mode (as the conversion b/w RTC and system time is simpler, done with bcd2bin(), bin2bcd()), read and set time, read and set alarm, read and set an offset. Signed-off-by: Claudiu Beznea Reported-by: kernel test robot --- Changes in v4: - disabled all interrupts on the initial setup, function rtca3_initial_setu= p(); RTCA3_RCR1_PIE interrupt (disabled in this series) is used on alarm setup. - added a comment about the counter clock, when requesting it, to let others know that this should stay on for the full lifetime of the RTC - used RTC_TIMESTAMP_BEGIN_2000 and RTC_TIMESTAMP_BEGIN_2099 - added a comment on rtca3_remove() to mention that the RTC cannot power on the system Changes in v3: - added pm runtime and reset control support; probe() was changed and rtca3_action() was added as for cleanup; VBATTB and RTC shares the clock, reset and PM domain; hw manual doesn't specifies this; it has been detected though reverse engineering - dropped clk member of struct rtca3_priv as it is used only in probe() - renamed rtca3_alarm_irq_enable_helper() to rtca3_alarm_irq_set_helper() and used it all over the places - fixed the issue: Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202407191156.wJPjHtKG-lkp@int= el.com/ - removed __maybe_unused from suspend/resume function and use DEFINE_SIMPLE_DEV_PM_OPS() along with pm_ptr() Changes in v2: - used cleanup.h helpers for locking - updated the MAINTAINERS entry with the new name for RTCA-3 documentation file and a new title (from "RENESAS RZ/G3S RTC DRIVER" to "RENESAS RTCA-3 RTC DRIVER") - used 24 hours mode - changed startup sequence (rtca3_initial_setup()) to avoid stopping the RTC if it's already configured - updated the RTC range to 2000-2099 - updated the compatible with the generic one (renesas,rz-rtca3) in the idea the driver will be also used by the RZ/V2H w/o the necessity to add a new compatible MAINTAINERS | 8 + drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-renesas-rtca3.c | 899 ++++++++++++++++++++++++++++++++ 4 files changed, 918 insertions(+) create mode 100644 drivers/rtc/rtc-renesas-rtca3.c diff --git a/MAINTAINERS b/MAINTAINERS index 97c4b798e65e..a79f3dac0234 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19633,6 +19633,14 @@ S: Supported F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml F: drivers/counter/rz-mtu3-cnt.c =20 +RENESAS RTCA-3 RTC DRIVER +M: Claudiu Beznea +L: linux-rtc@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml +F: drivers/rtc/rtc-renesas-rtca3.c + RENESAS RZ/N1 A5PSW SWITCH DRIVER M: Cl=C3=A9ment L=C3=A9ger L: linux-renesas-soc@vger.kernel.org diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 8d38f55043ca..a1aa6f6b9f88 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1995,6 +1995,16 @@ config RTC_DRV_MA35D1 This driver can also be built as a module, if so, the module will be called "rtc-ma35d1". =20 +config RTC_DRV_RENESAS_RTCA3 + tristate "Renesas RTCA-3 RTC" + depends on ARCH_RENESAS + help + If you say yes here you get support for the Renesas RTCA-3 RTC + available on the Renesas RZ/G3S SoC. + + This driver can also be built as a module, if so, the module + will be called "rtc-rtca3". + comment "HID Sensor RTC drivers" =20 config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 8ee79cb18322..1e19e97d7c51 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -158,6 +158,7 @@ obj-$(CONFIG_RTC_DRV_RX8025) +=3D rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8111) +=3D rtc-rx8111.o obj-$(CONFIG_RTC_DRV_RX8581) +=3D rtc-rx8581.o obj-$(CONFIG_RTC_DRV_RZN1) +=3D rtc-rzn1.o +obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) +=3D rtc-renesas-rtca3.o obj-$(CONFIG_RTC_DRV_S35390A) +=3D rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) +=3D rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) +=3D rtc-s5m.o diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca= 3.c new file mode 100644 index 000000000000..c8efccf3e552 --- /dev/null +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -0,0 +1,899 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * On-Chip RTC Support available on RZ/G3S SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Counter registers. */ +#define RTCA3_RSECCNT 0x2 +#define RTCA3_RSECCNT_SEC GENMASK(6, 0) +#define RTCA3_RMINCNT 0x4 +#define RTCA3_RMINCNT_MIN GENMASK(6, 0) +#define RTCA3_RHRCNT 0x6 +#define RTCA3_RHRCNT_HR GENMASK(5, 0) +#define RTCA3_RHRCNT_PM BIT(6) +#define RTCA3_RWKCNT 0x8 +#define RTCA3_RWKCNT_WK GENMASK(2, 0) +#define RTCA3_RDAYCNT 0xa +#define RTCA3_RDAYCNT_DAY GENMASK(5, 0) +#define RTCA3_RMONCNT 0xc +#define RTCA3_RMONCNT_MONTH GENMASK(4, 0) +#define RTCA3_RYRCNT 0xe +#define RTCA3_RYRCNT_YEAR GENMASK(7, 0) + +/* Alarm registers. */ +#define RTCA3_RSECAR 0x10 +#define RTCA3_RSECAR_SEC GENMASK(6, 0) +#define RTCA3_RMINAR 0x12 +#define RTCA3_RMINAR_MIN GENMASK(6, 0) +#define RTCA3_RHRAR 0x14 +#define RTCA3_RHRAR_HR GENMASK(5, 0) +#define RTCA3_RHRAR_PM BIT(6) +#define RTCA3_RWKAR 0x16 +#define RTCA3_RWKAR_DAYW GENMASK(2, 0) +#define RTCA3_RDAYAR 0x18 +#define RTCA3_RDAYAR_DATE GENMASK(5, 0) +#define RTCA3_RMONAR 0x1a +#define RTCA3_RMONAR_MON GENMASK(4, 0) +#define RTCA3_RYRAR 0x1c +#define RTCA3_RYRAR_YR GENMASK(7, 0) +#define RTCA3_RYRAREN 0x1e + +/* Alarm enable bit (for all alarm registers). */ +#define RTCA3_AR_ENB BIT(7) + +/* Control registers. */ +#define RTCA3_RCR1 0x22 +#define RTCA3_RCR1_AIE BIT(0) +#define RTCA3_RCR1_CIE BIT(1) +#define RTCA3_RCR1_PIE BIT(2) +#define RTCA3_RCR1_PES GENMASK(7, 4) +#define RTCA3_RCR1_PES_1_64_SEC 0x8 +#define RTCA3_RCR2 0x24 +#define RTCA3_RCR2_START BIT(0) +#define RTCA3_RCR2_RESET BIT(1) +#define RTCA3_RCR2_AADJE BIT(4) +#define RTCA3_RCR2_ADJP BIT(5) +#define RTCA3_RCR2_HR24 BIT(6) +#define RTCA3_RCR2_CNTMD BIT(7) +#define RTCA3_RSR 0x20 +#define RTCA3_RSR_AF BIT(0) +#define RTCA3_RSR_CF BIT(1) +#define RTCA3_RSR_PF BIT(2) +#define RTCA3_RADJ 0x2e +#define RTCA3_RADJ_ADJ GENMASK(5, 0) +#define RTCA3_RADJ_ADJ_MAX 0x3f +#define RTCA3_RADJ_PMADJ GENMASK(7, 6) +#define RTCA3_RADJ_PMADJ_NONE 0 +#define RTCA3_RADJ_PMADJ_ADD 1 +#define RTCA3_RADJ_PMADJ_SUB 2 + +/* Polling operation timeouts. */ +#define RTCA3_DEFAULT_TIMEOUT_US 150 +#define RTCA3_IRQSET_TIMEOUT_US 5000 +#define RTCA3_START_TIMEOUT_US 150000 +#define RTCA3_RESET_TIMEOUT_US 200000 + +/** + * enum rtca3_alrm_set_step - RTCA3 alarm set steps + * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step + * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step + * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step + */ +enum rtca3_alrm_set_step { + RTCA3_ALRM_SSTEP_DONE =3D 0, + RTCA3_ALRM_SSTEP_IRQ =3D 1, + RTCA3_ALRM_SSTEP_INIT =3D 3, +}; + +/** + * struct rtca3_ppb_per_cycle - PPB per cycle + * @ten_sec: PPB per cycle in 10 seconds adjutment mode + * @sixty_sec: PPB per cycle in 60 seconds adjustment mode + */ +struct rtca3_ppb_per_cycle { + int ten_sec; + int sixty_sec; +}; + +/** + * struct rtca3_priv - RTCA3 private data structure + * @base: base address + * @rtc_dev: RTC device + * @rstc: reset control + * @set_alarm_completion: alarm setup completion + * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step) + * @lock: device lock + * @ppb: ppb per cycle for each the available adjustment modes + * @wakeup_irq: wakeup IRQ + */ +struct rtca3_priv { + void __iomem *base; + struct rtc_device *rtc_dev; + struct reset_control *rstc; + struct completion set_alarm_completion; + atomic_t alrm_sstep; + spinlock_t lock; + struct rtca3_ppb_per_cycle ppb; + int wakeup_irq; +}; + +static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mas= k, u8 val) +{ + u8 tmp; + + tmp =3D readb(priv->base + off); + tmp &=3D ~mask; + tmp |=3D (val & mask); + writeb(tmp, priv->base + off); +} + +static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv) +{ + u8 val, pending; + + val =3D readb(priv->base + RTCA3_RSR); + pending =3D val & RTCA3_RSR_AF; + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return pending; +} + +static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv =3D dev_id; + u8 pending; + + guard(spinlock)(&priv->lock); + + pending =3D rtca3_alarm_handler_helper(priv); + + return IRQ_RETVAL(pending); +} + +static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv =3D dev_id; + u8 val, pending; + + guard(spinlock)(&priv->lock); + + val =3D readb(priv->base + RTCA3_RSR); + pending =3D val & RTCA3_RSR_PF; + + if (pending) { + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) { + /* Alarm setup in progress. */ + atomic_dec(&priv->alrm_sstep); + + if (atomic_read(&priv->alrm_sstep) =3D=3D RTCA3_ALRM_SSTEP_IRQ) { + /* + * We got 2 * 1/64 periodic interrupts. Disable + * interrupt and let alarm setup continue. + */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, + RTCA3_RCR1_PIE, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, + !(val & RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + complete(&priv->set_alarm_completion); + } + } + } + + return IRQ_RETVAL(pending); +} + +static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, b= ool cnt) +{ + /* Offset b/w time and alarm registers. */ + u8 offset =3D cnt ? 0 : 0xe; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and + * reading from registers) after writing to count registers, alarm + * registers, year alarm enable register, bits RCR2.AADJE, AADJP, + * and HR24 register, we need to do 3 empty reads before being + * able to fetch the registers content. + */ + for (u8 i =3D 0; i < 3; i++) { + readb(priv->base + RTCA3_RSECCNT + offset); + readb(priv->base + RTCA3_RMINCNT + offset); + readb(priv->base + RTCA3_RHRCNT + offset); + readb(priv->base + RTCA3_RWKCNT + offset); + readb(priv->base + RTCA3_RDAYCNT + offset); + readw(priv->base + RTCA3_RYRCNT + offset); + if (!cnt) + readb(priv->base + RTCA3_RYRAREN); + } +} + +static int rtca3_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month, tmp; + u8 trials =3D 0; + u32 year100; + u16 year; + + guard(spinlock_irqsave)(&priv->lock); + + tmp =3D readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) + return -EINVAL; + + do { + /* Clear carry interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0); + + /* Read counters. */ + sec =3D readb(priv->base + RTCA3_RSECCNT); + min =3D readb(priv->base + RTCA3_RMINCNT); + hour =3D readb(priv->base + RTCA3_RHRCNT); + wday =3D readb(priv->base + RTCA3_RWKCNT); + mday =3D readb(priv->base + RTCA3_RDAYCNT); + month =3D readb(priv->base + RTCA3_RMONCNT); + year =3D readw(priv->base + RTCA3_RYRCNT); + + tmp =3D readb(priv->base + RTCA3_RSR); + + /* + * We cannot generate carries due to reading 64Hz counter as + * the driver doesn't implement carry, thus, carries will be + * generated once per seconds. Add a timeout of 5 trials here + * to avoid infinite loop, if any. + */ + } while ((tmp & RTCA3_RSR_CF) && ++trials < 5); + + if (trials >=3D 5) + return -ETIMEDOUT; + + tm->tm_sec =3D bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); + tm->tm_min =3D bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min)); + tm->tm_hour =3D bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour)); + tm->tm_wday =3D bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday)); + tm->tm_mday =3D bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday)); + tm->tm_mon =3D bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1; + year =3D FIELD_GET(RTCA3_RYRCNT_YEAR, year); + year100 =3D bcd2bin((year =3D=3D 0x99) ? 0x19 : 0x20); + tm->tm_year =3D (year100 * 100 + bcd2bin(year)) - 1900; + + return 0; +} + +static int rtca3_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + u8 rcr2, tmp; + int ret; + + guard(spinlock_irqsave)(&priv->lock); + + /* Stop the RTC. */ + rcr2 =3D readb(priv->base + RTCA3_RCR2); + writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret =3D readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + !(tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Update time. */ + writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT); + writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT); + writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT); + writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT); + writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT); + writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT); + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, true); + + /* Start RTC. */ + writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + (tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_alarm_irq_set_helper(struct rtca3_priv *priv, + u8 interrupts, + unsigned int enabled) +{ + u8 tmp, val; + + if (enabled) { + /* + * AIE, CIE, PIE bit indexes in RSR corresponds with + * those on RCR1. Same interrupts mask can be used. + */ + rtca3_byte_update_bits(priv, RTCA3_RSR, interrupts, 0); + val =3D interrupts; + } else { + val =3D 0; + } + + rtca3_byte_update_bits(priv, RTCA3_RCR1, interrupts, val); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + ((tmp & interrupts) =3D=3D val), + 10, RTCA3_IRQSET_TIMEOUT_US); +} + +static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + + guard(spinlock_irqsave)(&priv->lock); + + return rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, enabled); +} + +static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month; + struct rtc_time *tm =3D &wkalrm->time; + u32 year100; + u16 year; + + guard(spinlock_irqsave)(&priv->lock); + + sec =3D readb(priv->base + RTCA3_RSECAR); + min =3D readb(priv->base + RTCA3_RMINAR); + hour =3D readb(priv->base + RTCA3_RHRAR); + wday =3D readb(priv->base + RTCA3_RWKAR); + mday =3D readb(priv->base + RTCA3_RDAYAR); + month =3D readb(priv->base + RTCA3_RMONAR); + year =3D readw(priv->base + RTCA3_RYRAR); + + tm->tm_sec =3D bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); + tm->tm_min =3D bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min)); + tm->tm_hour =3D bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour)); + tm->tm_wday =3D bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday)); + tm->tm_mday =3D bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday)); + tm->tm_mon =3D bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1; + year =3D FIELD_GET(RTCA3_RYRAR_YR, year); + year100 =3D bcd2bin((year =3D=3D 0x99) ? 0x19 : 0x20); + tm->tm_year =3D (year100 * 100 + bcd2bin(year)) - 1900; + + wkalrm->enabled =3D !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE); + + return 0; +} + +static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + struct rtc_time *tm =3D &wkalrm->time; + u8 rcr1, tmp; + int ret; + + scoped_guard(spinlock_irqsave, &priv->lock) { + tmp =3D readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) + return -EPERM; + + /* Disable AIE to prevent false interrupts. */ + rcr1 =3D readb(priv->base + RTCA3_RCR1); + rcr1 &=3D ~RTCA3_RCR1_AIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret =3D readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + !(tmp & RTCA3_RCR1_AIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Set the time and enable the alarm. */ + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR= ); + + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR); + writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, false); + + /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */ + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT); + reinit_completion(&priv->set_alarm_completion); + + /* Enable periodic interrupt. */ + rcr1 |=3D RTCA3_RCR1_PIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret =3D readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + (tmp & RTCA3_RCR1_PIE), + 10, RTCA3_IRQSET_TIMEOUT_US); + } + + if (ret) + goto setup_failed; + + /* Wait for the 2 * 1/64 periodic interrupts. */ + ret =3D wait_for_completion_interruptible_timeout(&priv->set_alarm_comple= tion, + msecs_to_jiffies(500)); + if (ret <=3D 0) { + ret =3D -ETIMEDOUT; + goto setup_failed; + } + + scoped_guard(spinlock_irqsave, &priv->lock) { + ret =3D rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, wkalrm->enabled= ); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + } + + return ret; + +setup_failed: + scoped_guard(spinlock_irqsave, &priv->lock) { + /* + * Disable PIE to avoid interrupt storm in case HW needed more than + * specified timeout for setup. + */ + writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_R= CR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + } + + return ret; +} + +static int rtca3_read_offset(struct device *dev, long *offset) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + u8 val, radj, cycles; + u32 ppb_per_cycle; + + scoped_guard(spinlock_irqsave, &priv->lock) { + radj =3D readb(priv->base + RTCA3_RADJ); + val =3D readb(priv->base + RTCA3_RCR2); + } + + cycles =3D FIELD_GET(RTCA3_RADJ_ADJ, radj); + + if (!cycles) { + *offset =3D 0; + return 0; + } + + if (val & RTCA3_RCR2_ADJP) + ppb_per_cycle =3D priv->ppb.ten_sec; + else + ppb_per_cycle =3D priv->ppb.sixty_sec; + + *offset =3D cycles * ppb_per_cycle; + val =3D FIELD_GET(RTCA3_RADJ_PMADJ, radj); + if (val =3D=3D RTCA3_RADJ_PMADJ_SUB) + *offset =3D -(*offset); + + return 0; +} + +static int rtca3_set_offset(struct device *dev, long offset) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + int cycles, cycles10, cycles60; + u8 radj, adjp, tmp; + int ret; + + /* + * Automatic time error adjustment could be set at intervals of 10 + * or 60 seconds. + */ + cycles10 =3D DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec); + cycles60 =3D DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec); + + /* We can set b/w 1 and 63 clock cycles. */ + if (cycles60 >=3D -RTCA3_RADJ_ADJ_MAX && + cycles60 <=3D RTCA3_RADJ_ADJ_MAX) { + cycles =3D cycles60; + adjp =3D 0; + } else if (cycles10 >=3D -RTCA3_RADJ_ADJ_MAX && + cycles10 <=3D RTCA3_RADJ_ADJ_MAX) { + cycles =3D cycles10; + adjp =3D RTCA3_RCR2_ADJP; + } else { + return -ERANGE; + } + + radj =3D FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); + if (!cycles) + radj |=3D FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE); + else if (cycles > 0) + radj |=3D FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD); + else + radj |=3D FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB); + + guard(spinlock_irqsave)(&priv->lock); + + tmp =3D readb(priv->base + RTCA3_RCR2); + + if ((tmp & RTCA3_RCR2_ADJP) !=3D adjp) { + /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */ + writeb(0, priv->base + RTCA3_RADJ); + ret =3D readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp, + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp); + ret =3D readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + ((tmp & RTCA3_RCR2_ADJP) =3D=3D adjp), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + } + + writeb(radj, priv->base + RTCA3_RADJ); + return readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp =3D= =3D radj), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static const struct rtc_class_ops rtca3_ops =3D { + .read_time =3D rtca3_read_time, + .set_time =3D rtca3_set_time, + .read_alarm =3D rtca3_read_alarm, + .set_alarm =3D rtca3_set_alarm, + .alarm_irq_enable =3D rtca3_alarm_irq_enable, + .set_offset =3D rtca3_set_offset, + .read_offset =3D rtca3_read_offset, +}; + +static int rtca3_initial_setup(struct clk *clk, struct rtca3_priv *priv) +{ + unsigned long osc32k_rate; + u8 val, tmp, mask; + u32 sleep_us; + int ret; + + osc32k_rate =3D clk_get_rate(clk); + if (!osc32k_rate) + return -EINVAL; + + sleep_us =3D DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6; + + priv->ppb.ten_sec =3D DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate *= 10)); + priv->ppb.sixty_sec =3D DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate= * 60)); + + /* + * According to HW manual (section 22.4.2. Clock and count mode setting p= rocedure) + * we need to wait at least 6 cycles of the 32KHz clock after clock was e= nabled. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Disable all interrupts. */ + mask =3D RTCA3_RCR1_AIE | RTCA3_RCR1_CIE | RTCA3_RCR1_PIE; + ret =3D rtca3_alarm_irq_set_helper(priv, mask, 0); + if (ret) + return ret; + + mask =3D RTCA3_RCR2_START | RTCA3_RCR2_HR24; + val =3D readb(priv->base + RTCA3_RCR2); + /* Nothing to do if already started in 24 hours and calendar count mode. = */ + if ((val & mask) =3D=3D mask) + return 0; + + /* Reconfigure the RTC in 24 hours and calendar count mode. */ + mask =3D RTCA3_RCR2_START | RTCA3_RCR2_CNTMD; + writeb(0, priv->base + RTCA3_RCR2); + ret =3D readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* + * Set 24 hours mode. According to HW manual (section 22.3.19. RTC Control + * Register 2) this needs to be done separate from stop operation. + */ + mask =3D RTCA3_RCR2_HR24; + val =3D RTCA3_RCR2_HR24; + writeb(val, priv->base + RTCA3_RCR2); + ret =3D readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Execute reset. */ + mask =3D RTCA3_RCR2_RESET; + writeb(val | RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2); + ret =3D readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_RESET_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.3. Notes on writing to and reading + * from registers) after reset we need to wait 6 clock cycles before + * writing to RTC registers. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Set no adjustment. */ + writeb(0, priv->base + RTCA3_RADJ); + ret =3D readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10, + RTCA3_DEFAULT_TIMEOUT_US); + + /* Start the RTC and enable automatic time error adjustment. */ + mask =3D RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + val |=3D RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + writeb(val, priv->base + RTCA3_RCR2); + ret =3D readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) = =3D=3D mask), + 10, RTCA3_START_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and reading + * from registers) we need to wait 1/128 seconds while the clock is opera= ting + * (RCR2.START bit =3D 1) to be able to read the counters after a return = from + * reset. + */ + usleep_range(8000, 9000); + + /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup.= */ + val =3D FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, val); + return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR= 1_PES) =3D=3D val), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_p= riv *priv) +{ + struct device *dev =3D &pdev->dev; + int ret, irq; + + irq =3D platform_get_irq_byname(pdev, "alarm"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n"); + + ret =3D devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm",= priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n"); + priv->wakeup_irq =3D irq; + + irq =3D platform_get_irq_byname(pdev, "period"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get period IRQ!\n"); + + ret =3D devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-peri= od", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request period IRQ!\n"); + + /* + * Driver doesn't implement carry handler. Just get the IRQ here + * for backward compatibility, in case carry support will be added later. + */ + irq =3D platform_get_irq_byname(pdev, "carry"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n"); + + return 0; +} + +static void rtca3_action(void *data) +{ + struct device *dev =3D data; + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + int ret; + + ret =3D reset_control_assert(priv->rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret =3D pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); +} + +static int rtca3_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rtca3_priv *priv; + struct clk *clk; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + priv->rstc =3D devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(priv->rstc)) + return PTR_ERR(priv->rstc); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret =3D reset_control_deassert(priv->rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, priv); + ret =3D devm_add_action_or_reset(dev, rtca3_action, dev); + if (ret) + return ret; + + /* + * This must be an always-on clock to keep the RTC running even after + * driver is unbinded. + */ + clk =3D devm_clk_get_enabled(dev, "counter"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + spin_lock_init(&priv->lock); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + init_completion(&priv->set_alarm_completion); + + ret =3D rtca3_initial_setup(clk, priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup the RTC!\n"); + + ret =3D rtca3_request_irqs(pdev, priv); + if (ret) + return ret; + + device_init_wakeup(&pdev->dev, 1); + + priv->rtc_dev =3D devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(priv->rtc_dev)) + return PTR_ERR(priv->rtc_dev); + + priv->rtc_dev->ops =3D &rtca3_ops; + priv->rtc_dev->max_user_freq =3D 256; + priv->rtc_dev->range_min =3D RTC_TIMESTAMP_BEGIN_2000; + priv->rtc_dev->range_max =3D RTC_TIMESTAMP_END_2099; + + return devm_rtc_register_device(priv->rtc_dev); +} + +static void rtca3_remove(struct platform_device *pdev) +{ + struct rtca3_priv *priv =3D platform_get_drvdata(pdev); + + guard(spinlock_irqsave)(&priv->lock); + + /* + * Disable alarm, periodic interrupts. The RTC device cannot + * power up the system. + */ + rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE | RTCA3_RCR1_PIE, 0); +} + +static int rtca3_suspend(struct device *dev) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + /* Alarm setup in progress. */ + if (atomic_read(&priv->alrm_sstep) !=3D RTCA3_ALRM_SSTEP_DONE) + return -EBUSY; + + enable_irq_wake(priv->wakeup_irq); + + return 0; +} + +static int rtca3_clean_alarm(struct rtca3_priv *priv) +{ + struct rtc_device *rtc_dev =3D priv->rtc_dev; + time64_t alarm_time, now; + struct rtc_wkalrm alarm; + struct rtc_time tm; + u8 pending; + int ret; + + ret =3D rtc_read_alarm(rtc_dev, &alarm); + if (ret) + return ret; + + if (!alarm.enabled) + return 0; + + ret =3D rtc_read_time(rtc_dev, &tm); + if (ret) + return ret; + + alarm_time =3D rtc_tm_to_time64(&alarm.time); + now =3D rtc_tm_to_time64(&tm); + if (alarm_time >=3D now) + return 0; + + /* + * Heuristically, it has been determined that when returning from deep + * sleep state the RTCA3_RSR.AF is zero even though the alarm expired. + * Call again the rtc_update_irq() if alarm helper detects this. + */ + + guard(spinlock_irqsave)(&priv->lock); + + pending =3D rtca3_alarm_handler_helper(priv); + if (!pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return 0; +} + +static int rtca3_resume(struct device *dev) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + disable_irq_wake(priv->wakeup_irq); + + /* + * According to the HW manual (section 22.6.4 Notes on writing to + * and reading from registers) we need to wait 1/128 seconds while + * RCR2.START =3D 1 to be able to read the counters after a return from l= ow + * power consumption state. + */ + mdelay(8); + + /* + * The alarm cannot wake the system from deep sleep states. In case + * we return from deep sleep states and the alarm expired we need + * to disable it to avoid failures when setting another alarm. + */ + return rtca3_clean_alarm(priv); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume); + +static const struct of_device_id rtca3_of_match[] =3D { + { .compatible =3D "renesas,rz-rtca3", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtca3_of_match); + +static struct platform_driver rtca3_platform_driver =3D { + .driver =3D { + .name =3D "rtc-rtca3", + .pm =3D pm_ptr(&rtca3_pm_ops), + .of_match_table =3D rtca3_of_match, + }, + .probe =3D rtca3_probe, + .remove_new =3D rtca3_remove, +}; +module_platform_driver(rtca3_platform_driver); + +MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); --=20 2.39.2 From nobody Tue Nov 26 08:54:06 2024 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5679D1E0B6E for ; Sat, 19 Oct 2024 08:48:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327688; cv=none; b=jiTgJ+kT/I5/a/Zp9S1epCujIoOLkNBvUKDcduSu9TeLGoD63EHmOdeL3MYWfBsBT/bmMoyQOTA4Xz0fUDpo0IgCviMAG5C8wK74TNv1Ssv2MwgK4zKbFfU1Wkk0a5I26Hp6ztIlMp7Ziqr8hfmCBKhZD0KvQoJstEnO3QjeKm8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327688; c=relaxed/simple; bh=7mbQShJcFfpZtsV/0O0X70LuaZZJCjkF9SKuyahgYN8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LJ7sC0ji2JHQVjhxtNOfaKWJWdUcQmQcBe5KMzd8DXpONShIvfRIWSYj0kdlEJaJij8VMoV4QshBn4K55K/ZnRt9CGmOA9U4Ecb+BY6+Ek+CXADjeEcPqTbtziy2ZVcNbCNO8XAoZNVo6lBn737OIGFhwMxXKhhN+zZnrnK33aA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=ZYs2wCD9; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="ZYs2wCD9" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-37d6ff1cbe1so2191344f8f.3 for ; Sat, 19 Oct 2024 01:48:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1729327685; x=1729932485; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n76uaOc9JNK30gqBdGs/PkLGDzcsWgIHozNG9uixX7Y=; b=ZYs2wCD91F5zDk3THtLqKIm6kGVt5+cYYKijkacAKsZiHLFb8ghPItFZsXDz4hHtoG ISgPYpsMuYWxFAR4CuuL84RiXmlfESs5qtT5hXrF8yDTLZiHjJwmz7daOYCGGdRXSkow PDk1gUB7ibPPkxKa+0SvdO7h1DfINN7zP0mPRSTzrX5pNDjVJ+1SPUBVX/ugqYRdOT0n pcUwD+Bb9nXFYR2y6jhXyPXw+mxUpM2Jyy42uTTJtQGOfnp8hc0zGz9tX6wYVjRv9UBm ZVmNMlslYjR6q+hST0ESNEzkNpOKhCteYWvha5DEZs5ZB6XRu3vycgacYWuiJtH1rgL1 Z6Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729327685; x=1729932485; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n76uaOc9JNK30gqBdGs/PkLGDzcsWgIHozNG9uixX7Y=; b=wh/KHqz1TQN142lAwOyyzbECgbJJP/2AWUCxN3zx5CFd7FaMYt5qDAO2wYZCHHAfaf PM5F9j+QssaW8WbvJNfjG5huEGtuBasxqhCM6pcuDSpgG2wg48UxK3+J7LlDFGP9Tyfa UtfZT2jO4h0pCxdelkshPnhexIdPdKd5fpyurlwEThtYjSAk6mWsXV0+eKv9rl4/aIZ5 S3dsLSSU8R961WzogxSP8w3uRB99ouVB/Z00k3ls5p/7MZrW9MsXvT/re8ycUNuNuQqR UNnI5Lyfu48qyY2eLJ9v9cKYz6KjjobwPP1JFiaF28QU8mZV8OPt8RXldvI7ckluMkAf jYIA== X-Forwarded-Encrypted: i=1; AJvYcCXQwVlvXaCECLps8Q9AeenNVrvZZeHgoAoq/QunyZfy1bhs/4jQJX4t/EzBGpn1nMILwkFGl4+wpys334Q=@vger.kernel.org X-Gm-Message-State: AOJu0YyHvikRZ93/NIaM3KSMVgVOePBSzfY6yJRb+S4yfpDYhXT+PIJm DTjqdkXEc1cFurPE+oSCGabwCmxtYZWrBQySPYBDIfCG1BfyNM2Iw10Y8LQxW7E= X-Google-Smtp-Source: AGHT+IEEpZiPiPfOC3M+a4OKPRdnozREuAvkhWiKYBAZoC4J0fDI95R1gsDCMYp599YKfb8ArETdfQ== X-Received: by 2002:a5d:67cc:0:b0:37d:4cd6:6f2b with SMTP id ffacd0b85a97d-37eab6ec97cmr3930148f8f.14.1729327684650; Sat, 19 Oct 2024 01:48:04 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:48:04 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 08/12] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Sat, 19 Oct 2024 11:47:34 +0300 Message-Id: <20241019084738.3370489-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v4: - used clock-controller for the vbattb node name - move the node near scif0 for ordering - set the vbattb_xtal status as disabled to avoid having it exported in linux with frequency =3D 0 in boards that don't use it - collected tags Changes in v3: - dropped the child nodes of vbattb; along with this dropped ranges, interrupt-names, #address-cells, #size-cells - added vbattb_xtal as input clock for vbattb Changes in v2: - update compatibles - updated clocks and clock-names for clock-controller node - removed the power domain from the clock-controller as this is controlled by parent node in v2 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 067a26a66c24..827db9f61802 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status =3D "disabled"; }; =20 + vbattb: clock-controller@1005c000 { + compatible =3D "renesas,r9a08g045-vbattb"; + reg =3D <0 0x1005c000 0 0x1000>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names =3D "bclk", "rtx"; + #clock-cells =3D <1>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G045_VBAT_BRESETN>; + status =3D "disabled"; + }; + i2c0: i2c@10090000 { compatible =3D "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; reg =3D <0 0x10090000 0 0x400>; @@ -425,4 +437,12 @@ timer { interrupt-names =3D "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; + + vbattb_xtal: vbattb-xtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board. */ + clock-frequency =3D <0>; + status =3D "disabled"; + }; }; --=20 2.39.2 From nobody Tue Nov 26 08:54:06 2024 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80E041E0B9A for ; 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([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:48:06 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 09/12] arm64: dts: renesas: r9a08g045: Add RTC node Date: Sat, 19 Oct 2024 11:47:35 +0300 Message-Id: <20241019084738.3370489-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v4: - dropped the assigned-clocks, assigned-clock-parents properties as they fit better on vbattb node - moved the RTC close to serial node for ordering Changes in v3: - added CPG clock, power domain, reset - and assigned-clocks, assigned-clock-parents to configure the VBATTCLK - included dt-bindings/clock/r9a08g045-vbattb.h Changes in v2: - updated compatibles arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 827db9f61802..14e105de2f08 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -7,6 +7,7 @@ =20 #include #include +#include =20 / { compatible =3D "renesas,r9a08g045"; @@ -72,6 +73,20 @@ scif0: serial@1004b800 { status =3D "disabled"; }; =20 + rtc: rtc@1004ec00 { + compatible =3D "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; 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([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:48:07 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 10/12] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Date: Sat, 19 Oct 2024 11:47:36 +0300 Message-Id: <20241019084738.3370489-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable the VBATTB controller. It provides the clock for RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v4: - added assigned-clocks, assigned-clock-parents properties - set vbattb_xtal status =3D "okay" - collected tags Changes in v3: - updated patch description - dropped vbattclk - added renesas,vbattb-load-nanofarads on vbattb - moved vbattb before vbattb_xtal Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index 21bfa4e03972..6be0ffdcb87e 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ =20 +#include #include #include =20 @@ -346,6 +347,18 @@ mux { }; }; =20 +&vbattb { + assigned-clocks =3D <&vbattb VBATTB_MUX>; + assigned-clock-parents =3D <&vbattb VBATTB_XC>; + quartz-load-femtofarads =3D <12500>; + status =3D "okay"; +}; + +&vbattb_xtal { + clock-frequency =3D <32768>; + status =3D "okay"; +}; + &wdt0 { timeout-sec =3D <60>; status =3D "okay"; --=20 2.39.2 From nobody Tue Nov 26 08:54:06 2024 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B0911E0DE2 for ; Sat, 19 Oct 2024 08:48:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327694; cv=none; b=KtEvxYbumZrORV7H7jJIiZvWsbYJyF0Joex8CqU9swRt09PSp3QPiPtYuhzsL/bBcXs6svyw1rZq5IMSgK3s+pBnA8MFrVhKiilWfmuIK6pxS5AIvKPR6u8Ze6E4cjQeLMEf6eeCYDfTD8epnyx2qbdXTnMcAKdeVrimBts9C7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327694; c=relaxed/simple; bh=QkgHvw9IBOeGPAakrzCTmrkD96bz5qPFYSsEtoUc+6s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S/68KbNlDQvnIDfdDWyI2PgBQepycPxpxxt+oeM1Df/qkz2knsaYgb5O3w/mg9TMB5vkvBv8mYEqDRpL0T75GCeuTpHqh4djzIZUjSf0CNfxtfM8vwou8buOcXYEbzSEuxv7/mj9ZISp92PVxkqUsGVQZQ611IXEIa9KBIKH3dE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=JC/05x2I; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="JC/05x2I" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-431616c23b5so9549825e9.0 for ; Sat, 19 Oct 2024 01:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1729327690; x=1729932490; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i1BDFdSyg41e2LABdQN1el7m1GZPq2Uu7y0UUTGsVos=; b=JC/05x2IHqKMY4XIqE+GHpMTkBvG0/11CN9YZc3OVSjOKYWFvQ1atbCGQaWR+GH59t QkZz4ydXhituuzlsJ/l31CPa6n1HuCUjFdebymIKmmL5wg3/wqwGUFMw0CX4NlRkX8qq Sd+5hCBt5o1Yv3jZ+y416VU5R3oH/rCdgd6TjG+FelftvsAsACKXFVxUDdqQjOW2ABny tgjIs6e+Gq3Uqr+IR0Xcwf8bzvs2m8JWl9SL4tkg1XnPVdc/XTAEqc7Sr9CQO4MXGTmI GVL7DMuGZS0pPSXJxA0k92zPplTIEg7+N1jgULjon7iXnk1ECU/SVao7m/vrKAYvhwiU HxjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729327690; x=1729932490; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i1BDFdSyg41e2LABdQN1el7m1GZPq2Uu7y0UUTGsVos=; b=GsrS1i07Dt3a4wGy/PDigHbCE8YXUSfyO0VegvoaLIlA+YvO7xWeeZQcBZDuRkXYOk syyfnMoNWKJ/O9xqRv34k8GSVXCuChRAyZ7kMDAnvCuiLOoogglh+4rW1Xv9s61G7RIn zAmJDlcPEJ6GyLN1cAdc87H0OY0ehmZEN6xw0kOz6FLwWDSq7es8gzbLrZ9o5I8VBWzc I951rr/sJ5m1nZlYUDgBdItpBDGV5vQ65qrgKNcsWZjbwhFWfoBSoB6PGiBInmfqGYO0 7XEdHwQ6MI7F1srPTjMWPcsrVmFwEDAX8FFXxNXpezlbLd1gE78GqfGApaej+F7/YgfJ EbOw== X-Forwarded-Encrypted: i=1; AJvYcCUjfrcSeY3tK8oAgXkyKQAVOL2kdeDjwW+KaLsAnqndpQ2Hza0WiNrEL6nnzDOl9REaVQ/c/36mNZ9BC34=@vger.kernel.org X-Gm-Message-State: AOJu0Yy5at2Y9B2705rZnhcoFd52hhsGfuwRZSx9EJxGnzDLFZ0wXeH/ WM3LyQqQMsZVm+dNwRQ5mSSUrDerK7uS/Q/IpV9dMrsAb2m5xJJlDfPVLIruw90= X-Google-Smtp-Source: AGHT+IGHzPKJDiCrpkrv0zEGse3U3VvdpNmMFQCy8z/QXuS15hpNd6JHm2gDYDjdinG8u1jiTCFuqw== X-Received: by 2002:a05:600c:3b85:b0:42f:84ec:3e0 with SMTP id 5b1f17b1804b1-43158721801mr65450245e9.9.1729327690371; Sat, 19 Oct 2024 01:48:10 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.48.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:48:09 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 11/12] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Date: Sat, 19 Oct 2024 11:47:37 +0300 Message-Id: <20241019084738.3370489-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v4: - collected tags Changes in v3: - none Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index 6be0ffdcb87e..939820a925d6 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -347,6 +347,10 @@ mux { }; }; =20 +&rtc { + status =3D "okay"; +}; + &vbattb { assigned-clocks =3D <&vbattb VBATTB_MUX>; assigned-clock-parents =3D <&vbattb VBATTB_XC>; --=20 2.39.2 From nobody Tue Nov 26 08:54:06 2024 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05FA51E0E16 for ; Sat, 19 Oct 2024 08:48:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327695; cv=none; b=uvWBmuYKrjInVvBile/W6InIs+WJ+u3vv8OHOVANUPHE+upaWNIz72GICI98achL8Z9LaA/B49QSzfENyOqAyt5mpbkDoH4arsL4adqe+7THAwU0Y0KJh1kOh2s2F+oY5acxa55zCKxoCGtb1P1QM9dJRk00yat71M6uAvIgo08= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729327695; c=relaxed/simple; bh=8GAcD1p4qmOxAT6LKl7/yGsIxlJCeks3lmvdsRJmH8U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=si/yt9zcOHPijONWzUQg/50apxhPnObfXClhCdz04JM9oKh3JjsUwF5gFdR8cPjf+VnGR3GcqNk/A3dB6hI3Ry9SXaY9DTwE+4EjROtL/5J96EP2mdF5M4AEKhgIYkS/kxE8f6bRw27OfO8EDUmlKzz6r9uFCW/AKjOMc7GGe8o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=BDMnWk26; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="BDMnWk26" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-37d47b38336so2028158f8f.3 for ; Sat, 19 Oct 2024 01:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1729327692; x=1729932492; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iR9u43Hyk1vIKlajLYqnwdEXv51OaTqN1pUoQT3Fdw0=; b=BDMnWk26U1NXmigmt9PPdQJsjydfhPNLC20W/rjKSc0fdXeT9HE4BoXu7dRPs2i4MD 188C70Jx0VaAn8l/X0tc8qti3Ws3KxYeifODbCtRR85A23/AO5etkJKMbrDRSh+Ec8yJ 8TmbGHAd+iKqXTIR5GMRPWcMbRLxZT09JBUAQiFeH6PH0MBlhTPW7u9ZSXi/5MKNI65c n/eKzY5oPCD0FqIXpGm3fRwnbAD0YiTkMvq3AdbAYkDFOrYgm8L1dUIaKpdTJJTtny9h rRMHpaR6bVo1flmmo2xiDMhlwSkN5UkMPWLbhOHKD2BG3VDOlUiqphVfvcZKHnw0eUqp 93wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729327692; x=1729932492; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iR9u43Hyk1vIKlajLYqnwdEXv51OaTqN1pUoQT3Fdw0=; b=UrgTKA+aMPD1kmvA45bKrV9mYPlo/uBHXdA+MXjcwC770GIX9LzHN5q3jLR/HtodfC DWGNFW4WjDf7P+tGsIIKaMpAOvKjYr6EOwGlMbXR+jQJwGbg6+J2I3Y8yW3KiMMbFB/O INW9YdQUbKq0e3KFgSQaqvC8/aIpZWF5KOvmXJmu56wQ5VLQ+h43qUFbbdqPhmAVzMYi WbsdVdjDAdP9pFQFAkVfGZVLQpUTcACR35jjpMAqtXGdn4GywokqycVjryhEjNSU/i22 uS+XxyZTOX2bYNBtze3XqYAh/fJLuhNBTuB8OmakGygyD4zFT8U/9IBONjpUpCX6NemK 0wTQ== X-Forwarded-Encrypted: i=1; AJvYcCXXPjQVZi+Cy0QS9I7AnFGiAufBOLnPjtaeo6KLZTrzhFM95kqQO/HKzVM+RimZImpkfC/emNv3NURMTYY=@vger.kernel.org X-Gm-Message-State: AOJu0Yw9BbIr/5wD65zOZfM+OCUaT0vXyL21emMGbVJm1NCroPpMspjX bhMAkRRRdzW9GPPDdnF5At0PSGRSHswSRkm3oecbs2Vbp/aXx0r5ahvvr/JD6Uk= X-Google-Smtp-Source: AGHT+IHsNssw3nPyESTNLOiP+9Mlv4+US3nWRprCJSeU2x+CacNFKb3J8zoQ9J/1GgCM0O9zmVhHzQ== X-Received: by 2002:a5d:61ce:0:b0:37c:c5be:1121 with SMTP id ffacd0b85a97d-37eab4d1227mr3498805f8f.9.1729327692261; Sat, 19 Oct 2024 01:48:12 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf0eccbasm3898731f8f.81.2024.10.19.01.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:48:11 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 12/12] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags Date: Sat, 19 Oct 2024 11:47:38 +0300 Message-Id: <20241019084738.3370489-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable the Renesas VBATTB clock and RTCA-3 RTC drivers. These are available on the Renesas RZ/G3S SoC. VBATTB is the clock provider for the RTC counter. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v4: - squashed w/ patch "arm64: defconfig: Enable Renesas RTCA-3 flag" from v3 - updated patch description - collected tags Changes in v3: - update patch title and description - dropped CONFIG_MFD_RENESAS_VBATTB Changes in v2: - added CONFIG_MFD_RENESAS_VBATTB - added vendor name in the VBATTB clock flag arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8067bf051377..e3252e24bd4d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1216,6 +1216,7 @@ CONFIG_RTC_DRV_IMX_SC=3Dm CONFIG_RTC_DRV_MT6397=3Dm CONFIG_RTC_DRV_XGENE=3Dy CONFIG_RTC_DRV_TI_K3=3Dm +CONFIG_RTC_DRV_RENESAS_RTCA3=3Dy CONFIG_DMADEVICES=3Dy CONFIG_DMA_BCM2835=3Dy CONFIG_DMA_SUN6I=3Dm @@ -1362,6 +1363,7 @@ CONFIG_SM_VIDEOCC_8250=3Dy CONFIG_QCOM_HFPLL=3Dy CONFIG_CLK_GFM_LPASS_SM8250=3Dm CONFIG_CLK_RCAR_USB2_CLOCK_SEL=3Dy +CONFIG_CLK_RENESAS_VBATTB=3Dy CONFIG_HWSPINLOCK=3Dy CONFIG_HWSPINLOCK_QCOM=3Dy CONFIG_TEGRA186_TIMER=3Dy --=20 2.39.2