From nobody Tue Nov 26 11:42:18 2024 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 233B01DF73F; Sat, 19 Oct 2024 07:10:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729321861; cv=none; b=EgmQ3AOPbiYSCcgUjFnWsyz29TK3crlziQT5BWJS+vV3n9AjcXZGLicmkVM/syQH/gw6BYsEsUwMV5UpShAYGi2TW+m+MRdowH1skZod8E2Ln1uiT5RZyWZWrjT42MNxKVMFS/7t2QaemD+3nkBFjv2jYaVIu6Jb77sBCZtpGn8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729321861; c=relaxed/simple; bh=QKto5A9MIMK/IEg/kWynx+UpUoTjf00hu+AW07gvz90=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CAqk7XtQxuH8ldHB36Hqh16mWlemo6Dz/V+XcApnAlkgBW5uFO1tFRf1X03pEUVofaujt7FzKfxKEWd1QpIQ9D2ZnYBUHckT3sSVV/TJoN0nnhWkbVypIh9mI/qjEs4fLQMI4EhY25yRTiigQWH3GjAWF9v5UqsLHIXm5/ReqVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MbVy//vB; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MbVy//vB" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-5c9362c26d8so6515158a12.1; Sat, 19 Oct 2024 00:10:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729321857; x=1729926657; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5Wui8yC11QzS3zuL6au0E0B/rgxgmkQnWbsEcia4kwc=; b=MbVy//vB3QwMA9iherdI3blVibarD5OV5WjxCFvuIGCmc2a7oi/v/KFqLG4j93DSYJ yoVhZrGEUDMt4NgqxA8auFbRCMJzh41vByPz8BlZe1QfjNAXuzZTj8V2OeHo6/z4gFcV oUJ0iLMzmeojfn2rmKvguuZsZTQ8VaCPnWfBkuZxRPMV/ewWlOk7tdjXOPr6VewcgnFW FKbVbOiDtTvJolzPrWPu6RwYZeYBtLXdDnxuG4nRPE7utCMfEj/Qe5SZL2V8iviPbzgX JuSJvRYbWIlRp8wZof74lcVJNNxbSxI1x7QjJtXS+aIxCA3+n3zRttHfqrJqf2dFQJ74 /p7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729321857; x=1729926657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5Wui8yC11QzS3zuL6au0E0B/rgxgmkQnWbsEcia4kwc=; b=GiEHogC1zMuafG+T/bm5yNWdqIn+vpjRjdGfNjIqMabiFatXa4+ksXp15vCyz8zVDS HYczAfxWXxDPW55EqPhIstjmFIMUDL43mHnvrqiFG1Prby4kW5PZTGVtRf60aGws61M/ 4hgHzXWVm1gKANuf/UFnDKgwfuqDM/m+ORdsW6fGDEA+pBfJwEJNpXVPV395JYf067hT bNPvSdrG3Jv/dIWnaJkx/ipEQF0fAUO315BhLIKRJLQh65FvscMxfjCuubcYt1TRIw2j CYXqxhscsH8NpKPzF+1CHBfUHaPbHIcN6pprvIE9jniR950Q9VeNTNaZ3ZLLDkOEuhvy KuXQ== X-Forwarded-Encrypted: i=1; AJvYcCU82nSR7uVfq8CdvU0oLzcu9A2Mv0u8nJmGznBalkGSl0NsGlVO4H7HQp3ph3p5tLkZuY7HJW93tgryqA==@vger.kernel.org, AJvYcCXqm9K8po3LbViQhWKuDw64Zy+IFj1PXaaq4ldeZkMX8T6/t3E28Kwtd/31zHRV1cLaJXgHat3rXNJ5Co0=@vger.kernel.org X-Gm-Message-State: AOJu0Yw9Dwd067XSOLCKpuhzJMbR819pntxATOH5zNqTnRL3s7b7guSu CsVs9N3v3H+CXqfo0gCRvzhYZqfbx7xyibUPRnLT5O8PUR/DpSKO X-Google-Smtp-Source: AGHT+IExY8gabkNXEofgxZ5SEDsJU6OlXo5CrynzcFrreQZ+IW5eHKcv48BmoDaVxBxV0O8Kka91Xw== X-Received: by 2002:a17:907:3f2a:b0:a99:f209:cea3 with SMTP id a640c23a62f3a-a9a6a412745mr499118066b.11.1729321857016; Sat, 19 Oct 2024 00:10:57 -0700 (PDT) Received: from localhost.localdomain ([79.175.114.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a68c27841sm180566666b.192.2024.10.19.00.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 00:10:56 -0700 (PDT) From: Aleksandar Rikalo To: Thomas Bogendoerfer Cc: Aleksandar Rikalo , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Gregory CLEMENT Subject: [PATCH v7 07/12] MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core Date: Sat, 19 Oct 2024 09:10:32 +0200 Message-Id: <20241019071037.145314-8-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241019071037.145314-1-arikalo@gmail.com> References: <20241019071037.145314-1-arikalo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paul Burton The pm-cps code has up until now used per-CPU variables indexed by core, rather than CPU number, in order to share data amongst sibling CPUs (ie. VPs/threads in a core). This works fine for single cluster systems, but with multi-cluster systems a core number is no longer unique in the system, leading to sharing between CPUs that are not actually siblings. Avoid this issue by using per-CPU variables as they are more generally used - ie. access them using CPU numbers rather than core numbers. Sharing between siblings is then accomplished by: - Assigning the same pointer to entries for each sibling CPU for the nc_asm_enter & ready_count variables, which allow this by virtue of being per-CPU pointers. - Indexing by the first CPU set in a CPUs cpu_sibling_map in the case of pm_barrier, for which we can't use the previous approach because the per-CPU variable is not a pointer. Signed-off-by: Paul Burton Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Tested-by: Serge Semin --- arch/mips/kernel/pm-cps.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index d09ca77e624d..9369a8dc385e 100644 --- a/arch/mips/kernel/pm-cps.c +++ b/arch/mips/kernel/pm-cps.c @@ -57,10 +57,7 @@ static DEFINE_PER_CPU_ALIGNED(u32*, ready_count); /* Indicates online CPUs coupled with the current CPU */ static DEFINE_PER_CPU_ALIGNED(cpumask_t, online_coupled); =20 -/* - * Used to synchronize entry to deep idle states. Actually per-core rather - * than per-CPU. - */ +/* Used to synchronize entry to deep idle states */ static DEFINE_PER_CPU_ALIGNED(atomic_t, pm_barrier); =20 /* Saved CPU state across the CPS_PM_POWER_GATED state */ @@ -112,9 +109,10 @@ int cps_pm_enter_state(enum cps_pm_state state) cps_nc_entry_fn entry; struct core_boot_config *core_cfg; struct vpe_boot_config *vpe_cfg; + atomic_t *barrier; =20 /* Check that there is an entry function for this state */ - entry =3D per_cpu(nc_asm_enter, core)[state]; + entry =3D per_cpu(nc_asm_enter, cpu)[state]; if (!entry) return -EINVAL; =20 @@ -150,7 +148,7 @@ int cps_pm_enter_state(enum cps_pm_state state) smp_mb__after_atomic(); =20 /* Create a non-coherent mapping of the core ready_count */ - core_ready_count =3D per_cpu(ready_count, core); + core_ready_count =3D per_cpu(ready_count, cpu); nc_addr =3D kmap_noncoherent(virt_to_page(core_ready_count), (unsigned long)core_ready_count); nc_addr +=3D ((unsigned long)core_ready_count & ~PAGE_MASK); @@ -158,7 +156,8 @@ int cps_pm_enter_state(enum cps_pm_state state) =20 /* Ensure ready_count is zero-initialised before the assembly runs */ WRITE_ONCE(*nc_core_ready_count, 0); - coupled_barrier(&per_cpu(pm_barrier, core), online); + barrier =3D &per_cpu(pm_barrier, cpumask_first(&cpu_sibling_map[cpu])); + coupled_barrier(barrier, online); =20 /* Run the generated entry code */ left =3D entry(online, nc_core_ready_count); @@ -629,12 +628,14 @@ static void *cps_gen_entry_code(unsigned cpu, enum cp= s_pm_state state) =20 static int cps_pm_online_cpu(unsigned int cpu) { - enum cps_pm_state state; - unsigned core =3D cpu_core(&cpu_data[cpu]); + unsigned int sibling, core; void *entry_fn, *core_rc; + enum cps_pm_state state; + + core =3D cpu_core(&cpu_data[cpu]); =20 for (state =3D CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) { - if (per_cpu(nc_asm_enter, core)[state]) + if (per_cpu(nc_asm_enter, cpu)[state]) continue; if (!test_bit(state, state_support)) continue; @@ -646,16 +647,19 @@ static int cps_pm_online_cpu(unsigned int cpu) clear_bit(state, state_support); } =20 - per_cpu(nc_asm_enter, core)[state] =3D entry_fn; + for_each_cpu(sibling, &cpu_sibling_map[cpu]) + per_cpu(nc_asm_enter, sibling)[state] =3D entry_fn; } =20 - if (!per_cpu(ready_count, core)) { + if (!per_cpu(ready_count, cpu)) { core_rc =3D kmalloc(sizeof(u32), GFP_KERNEL); if (!core_rc) { pr_err("Failed allocate core %u ready_count\n", core); return -ENOMEM; } - per_cpu(ready_count, core) =3D core_rc; + + for_each_cpu(sibling, &cpu_sibling_map[cpu]) + per_cpu(ready_count, sibling) =3D core_rc; } =20 return 0; --=20 2.25.1