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charset="utf-8" From: Paul Burton Parts of code in the MIPS GIC driver operate on the GIC local register block for each online CPU, accessing each via the GIC's other/redirect register block. Abstract the process of iterating over online CPUs & configuring the other/redirect region to access their registers through a new for_each_online_cpu_gic() macro. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Tested-by: Serge Semin Tested-by: Gregory CLEMENT --- drivers/irqchip/irq-mips-gic.c | 59 +++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 76253e864f23..6c7a7d2f0438 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -66,6 +66,44 @@ static struct gic_all_vpes_chip_data { bool mask; } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; =20 +static int __gic_with_next_online_cpu(int prev) +{ + unsigned int cpu; + + /* Discover the next online CPU */ + cpu =3D cpumask_next(prev, cpu_online_mask); + + /* If there isn't one, we're done */ + if (cpu >=3D nr_cpu_ids) + return cpu; + + /* + * Move the access lock to the next CPU's GIC local register block. + * + * Set GIC_VL_OTHER. Since the caller holds gic_lock nothing can + * clobber the written value. + */ + write_gic_vl_other(mips_cm_vp_id(cpu)); + + return cpu; +} + +/** + * for_each_online_cpu_gic() - Iterate over online CPUs, access local regi= sters + * @cpu: An integer variable to hold the current CPU number + * @gic_lock: A pointer to raw spin lock used as a guard + * + * Iterate over online CPUs & configure the other/redirect register region= to + * access each CPUs GIC local register block, which can be accessed from t= he + * loop body using read_gic_vo_*() or write_gic_vo_*() accessor functions = or + * their derivatives. + */ +#define for_each_online_cpu_gic(cpu, gic_lock) \ + guard(raw_spinlock_irqsave)(gic_lock); \ + for ((cpu) =3D __gic_with_next_online_cpu(-1); \ + (cpu) < nr_cpu_ids; \ + (cpu) =3D __gic_with_next_online_cpu(cpu)) + static void gic_clear_pcpu_masks(unsigned int intr) { unsigned int i; @@ -350,37 +388,27 @@ static struct irq_chip gic_local_irq_controller =3D { static void gic_mask_local_irq_all_vpes(struct irq_data *d) { struct gic_all_vpes_chip_data *cd; - unsigned long flags; int intr, cpu; =20 intr =3D GIC_HWIRQ_TO_LOCAL(d->hwirq); cd =3D irq_data_get_irq_chip_data(d); cd->mask =3D false; =20 - raw_spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + for_each_online_cpu_gic(cpu, &gic_lock) write_gic_vo_rmask(BIT(intr)); - } - raw_spin_unlock_irqrestore(&gic_lock, flags); } =20 static void gic_unmask_local_irq_all_vpes(struct irq_data *d) { struct gic_all_vpes_chip_data *cd; - unsigned long flags; int intr, cpu; =20 intr =3D GIC_HWIRQ_TO_LOCAL(d->hwirq); cd =3D irq_data_get_irq_chip_data(d); cd->mask =3D true; =20 - raw_spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + for_each_online_cpu_gic(cpu, &gic_lock) write_gic_vo_smask(BIT(intr)); - } - raw_spin_unlock_irqrestore(&gic_lock, flags); } =20 static void gic_all_vpes_irq_cpu_online(void) @@ -469,7 +497,6 @@ static int gic_irq_domain_map(struct irq_domain *d, uns= igned int virq, irq_hw_number_t hwirq) { struct gic_all_vpes_chip_data *cd; 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charset="utf-8" From: Paul Burton Use CM's GCR_CL_REDIRECT register to access registers in remote clusters, so users of gic_with_each_online_cpu() gain support for multi-cluster with no further changes. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Signed-off-by: Thomas Gleixner Tested-by: Serge Semin Tested-by: Gregory CLEMENT --- drivers/irqchip/irq-mips-gic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 6c7a7d2f0438..29bdfdce2123 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -88,6 +88,12 @@ static int __gic_with_next_online_cpu(int prev) return cpu; } =20 +static inline void gic_unlock_cluster(void) +{ + if (mips_cps_multicluster_cpus()) + mips_cm_unlock_other(); +} + /** * for_each_online_cpu_gic() - Iterate over online CPUs, access local regi= sters * @cpu: An integer variable to hold the current CPU number @@ -102,6 +108,7 @@ static int __gic_with_next_online_cpu(int prev) guard(raw_spinlock_irqsave)(gic_lock); \ for ((cpu) =3D __gic_with_next_online_cpu(-1); \ (cpu) < nr_cpu_ids; \ + gic_unlock_cluster(), \ (cpu) =3D __gic_with_next_online_cpu(cpu)) =20 static void gic_clear_pcpu_masks(unsigned int intr) --=20 2.25.1 From nobody Tue Nov 26 08:51:56 2024 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 748911DE3A3; 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charset="utf-8" From: Chao-ying Fu In multi-cluster MIPS I6500 systems, there is a GIC per cluster. The default shared interrupt setup configured in gic_of_init() will only apply to the GIC in the cluster containing the boot CPU, leaving the GICs of other clusters unconfigured. Similarly configure other clusters. Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Tested-by: Serge Semin Tested-by: Gregory CLEMENT --- drivers/irqchip/irq-mips-gic.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 29bdfdce2123..d93a076620c7 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -764,7 +764,7 @@ static int gic_cpu_startup(unsigned int cpu) static int __init gic_of_init(struct device_node *node, struct device_node *parent) { - unsigned int cpu_vec, i, gicconfig; + unsigned int cpu_vec, i, gicconfig, cl, nclusters; unsigned long reserved; phys_addr_t gic_base; struct resource res; @@ -845,11 +845,29 @@ static int __init gic_of_init(struct device_node *nod= e, =20 board_bind_eic_interrupt =3D &gic_bind_eic_interrupt; =20 - /* Setup defaults */ - for (i =3D 0; i < gic_shared_intrs; i++) { - change_gic_pol(i, GIC_POL_ACTIVE_HIGH); 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charset="utf-8" From: Paul Burton The MIPS I6500 CPU & CM (Coherence Manager) 3.5 introduce the concept of multiple clusters to the system. In these systems, each cluster contains its own GIC, so the GIC isn't truly global any longer. Access to registers in the GICs of remote clusters is possible using a redirect register block much like the redirect register blocks provided by the CM & CPC, and configured through the same GCR_REDIRECT register that mips_cm_lock_other() abstraction builds upon. It is expected that external interrupts are connected identically on all clusters. That is, if there is a device providing an interrupt connected to GIC interrupt pin 0 then it should be connected to pin 0 of every GIC in the system. For the most part, the GIC can be treated as though it is still truly global, so long as interrupts in the cluster are configured properly. This patch introduces support for such multi-cluster systems in the MIPS GIC irqchip driver. A newly introduced gic_irq_lock_cluster() function allows: 1) Configure access to a GIC in a remote cluster via the redirect register block, using mips_cm_lock_other(). Or: 2) Detect that the interrupt in question is affine to the local cluster and plain old GIC register access to the GIC in the local cluster should be used. It is possible to access the local cluster's GIC registers via the redirect block, but keeping the special case for them is both good for performance (because we avoid the locking & indirection overhead of using the redirect block) and necessary to maintain compatibility with systems using CM revisions prior to 3.5 which don't support the redirect block. The gic_irq_lock_cluster() function relies upon an IRQs effective affinity in order to discover which cluster the IRQ is affine to. In order to track this & allow it to be updated at an appropriate point during gic_set_affinity() we select the generic support for effective affinity using CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK. gic_set_affinity() is the one function which gains much complexity. It now deconfigures routing to any VP(E), ie. CPU, on the old cluster when moving affinity to a new cluster. gic_shared_irq_domain_map() moves its update of the IRQs effective affinity to before its use of gic_irq_lock_cluster(), to ensure that operation is on the cluster the IRQ is affine to. The remaining changes are straightforward use of the gic_irq_lock_cluster() function to select between local cluster & remote cluster code-paths when configuring interrupts. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Tested-by: Serge Semin Tested-by: Gregory CLEMENT --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-mips-gic.c | 161 +++++++++++++++++++++++++++++---- 2 files changed, 143 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 341cd9ca5a05..fa011868ec9e 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -345,6 +345,7 @@ config KEYSTONE_IRQ =20 config MIPS_GIC bool + select GENERIC_IRQ_EFFECTIVE_AFF_MASK select GENERIC_IRQ_IPI if SMP select IRQ_DOMAIN_HIERARCHY select MIPS_CM diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index d93a076620c7..f42f69bbd6fb 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -111,6 +111,41 @@ static inline void gic_unlock_cluster(void) gic_unlock_cluster(), \ (cpu) =3D __gic_with_next_online_cpu(cpu)) =20 +/** + * gic_irq_lock_cluster() - Lock redirect block access to IRQ's cluster + * @d: struct irq_data corresponding to the interrupt we're interested in + * + * Locks redirect register block access to the global register block of th= e GIC + * within the remote cluster that the IRQ corresponding to @d is affine to, + * returning true when this redirect block setup & locking has been perfor= med. + * + * If @d is affine to the local cluster then no locking is performed and t= his + * function will return false, indicating to the caller that it should acc= ess + * the local clusters registers without the overhead of indirection throug= h the + * redirect block. + * + * In summary, if this function returns true then the caller should access= GIC + * registers using redirect register block accessors & then call + * mips_cm_unlock_other() when done. If this function returns false then t= he + * caller should trivially access GIC registers in the local cluster. + * + * Returns true if locking performed, else false. + */ +static bool gic_irq_lock_cluster(struct irq_data *d) +{ + unsigned int cpu, cl; + + cpu =3D cpumask_first(irq_data_get_effective_affinity_mask(d)); + BUG_ON(cpu >=3D NR_CPUS); + + cl =3D cpu_cluster(&cpu_data[cpu]); + if (cl =3D=3D cpu_cluster(¤t_cpu_data)) + return false; + + mips_cm_lock_other(cl, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + return true; +} + static void gic_clear_pcpu_masks(unsigned int intr) { unsigned int i; @@ -157,7 +192,12 @@ static void gic_send_ipi(struct irq_data *d, unsigned = int cpu) { irq_hw_number_t hwirq =3D GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); =20 - write_gic_wedge(GIC_WEDGE_RW | hwirq); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_wedge(GIC_WEDGE_RW | hwirq); + mips_cm_unlock_other(); + } else { + write_gic_wedge(GIC_WEDGE_RW | hwirq); + } } =20 int gic_get_c0_compare_int(void) @@ -225,7 +265,13 @@ static void gic_mask_irq(struct irq_data *d) { unsigned int intr =3D GIC_HWIRQ_TO_SHARED(d->hwirq); =20 - write_gic_rmask(intr); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_rmask(intr); + mips_cm_unlock_other(); + } else { + write_gic_rmask(intr); + } + gic_clear_pcpu_masks(intr); } =20 @@ -234,7 +280,12 @@ static void gic_unmask_irq(struct irq_data *d) unsigned int intr =3D GIC_HWIRQ_TO_SHARED(d->hwirq); unsigned int cpu; =20 - write_gic_smask(intr); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_smask(intr); + mips_cm_unlock_other(); + } else { + write_gic_smask(intr); + } =20 gic_clear_pcpu_masks(intr); cpu =3D cpumask_first(irq_data_get_effective_affinity_mask(d)); @@ -245,7 +296,12 @@ static void gic_ack_irq(struct irq_data *d) { unsigned int irq =3D GIC_HWIRQ_TO_SHARED(d->hwirq); =20 - write_gic_wedge(irq); + if (gic_irq_lock_cluster(d)) { + write_gic_redir_wedge(irq); + mips_cm_unlock_other(); + } else { + write_gic_wedge(irq); + } } =20 static int gic_set_type(struct irq_data *d, unsigned int type) @@ -285,9 +341,16 @@ static int gic_set_type(struct irq_data *d, unsigned i= nt type) break; } =20 - change_gic_pol(irq, pol); - change_gic_trig(irq, trig); - change_gic_dual(irq, dual); + if (gic_irq_lock_cluster(d)) { + change_gic_redir_pol(irq, pol); + change_gic_redir_trig(irq, trig); + change_gic_redir_dual(irq, dual); + mips_cm_unlock_other(); + } else { + change_gic_pol(irq, pol); + change_gic_trig(irq, trig); + change_gic_dual(irq, dual); + } =20 if (trig =3D=3D GIC_TRIG_EDGE) irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, @@ -305,25 +368,72 @@ static int gic_set_affinity(struct irq_data *d, const= struct cpumask *cpumask, bool force) { unsigned int irq =3D GIC_HWIRQ_TO_SHARED(d->hwirq); + unsigned int cpu, cl, old_cpu, old_cl; unsigned long flags; - unsigned int cpu; =20 + /* + * The GIC specifies that we can only route an interrupt to one VP(E), + * ie. CPU in Linux parlance, at a time. Therefore we always route to + * the first online CPU in the mask. + */ cpu =3D cpumask_first_and(cpumask, cpu_online_mask); if (cpu >=3D NR_CPUS) return -EINVAL; =20 - /* Assumption : cpumask refers to a single CPU */ - raw_spin_lock_irqsave(&gic_lock, flags); + old_cpu =3D cpumask_first(irq_data_get_effective_affinity_mask(d)); + old_cl =3D cpu_cluster(&cpu_data[old_cpu]); + cl =3D cpu_cluster(&cpu_data[cpu]); =20 - /* Re-route this IRQ */ - write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); + raw_spin_lock_irqsave(&gic_lock, flags); =20 - /* Update the pcpu_masks */ - gic_clear_pcpu_masks(irq); - if (read_gic_mask(irq)) - set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); + /* + * If we're moving affinity between clusters, stop routing the + * interrupt to any VP(E) in the old cluster. + */ + if (cl !=3D old_cl) { + if (gic_irq_lock_cluster(d)) { + write_gic_redir_map_vp(irq, 0); + mips_cm_unlock_other(); + } else { + write_gic_map_vp(irq, 0); + } + } =20 + /* + * Update effective affinity - after this gic_irq_lock_cluster() will + * begin operating on the new cluster. + */ irq_data_update_effective_affinity(d, cpumask_of(cpu)); + + /* + * If we're moving affinity between clusters, configure the interrupt + * trigger type in the new cluster. + */ + if (cl !=3D old_cl) + gic_set_type(d, irqd_get_trigger_type(d)); + + /* Route the interrupt to its new VP(E) */ + if (gic_irq_lock_cluster(d)) { + write_gic_redir_map_pin(irq, + GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_redir_map_vp(irq, BIT(mips_cm_vp_id(cpu))); + + /* Update the pcpu_masks */ + gic_clear_pcpu_masks(irq); + if (read_gic_redir_mask(irq)) + set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); + + mips_cm_unlock_other(); + } else { + write_gic_map_pin(irq, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); + + /* Update the pcpu_masks */ + gic_clear_pcpu_masks(irq); + if (read_gic_mask(irq)) + set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); + } + raw_spin_unlock_irqrestore(&gic_lock, flags); =20 return IRQ_SET_MASK_OK; @@ -471,11 +581,21 @@ static int gic_shared_irq_domain_map(struct irq_domai= n *d, unsigned int virq, unsigned long flags; =20 data =3D irq_get_irq_data(virq); + irq_data_update_effective_affinity(data, cpumask_of(cpu)); =20 raw_spin_lock_irqsave(&gic_lock, flags); - write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); - write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); - irq_data_update_effective_affinity(data, cpumask_of(cpu)); + + /* Route the interrupt to its VP(E) */ + if (gic_irq_lock_cluster(data)) { + write_gic_redir_map_pin(intr, + GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_redir_map_vp(intr, BIT(mips_cm_vp_id(cpu))); + mips_cm_unlock_other(); + } else { + write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); + } + raw_spin_unlock_irqrestore(&gic_lock, flags); =20 return 0; @@ -651,6 +771,9 @@ static int gic_ipi_domain_alloc(struct irq_domain *d, u= nsigned int virq, if (ret) goto error; =20 + /* Set affinity to cpu. */ + irq_data_update_effective_affinity(irq_get_irq_data(virq + i), + cpumask_of(cpu)); ret =3D irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); 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charset="utf-8" From: Paul Burton In a multi-cluster MIPS system, there are multiple GICs - one in each cluster - each of which has its independent counter. The counters in each GIC are not synchronized in any way, so they can drift relative to one another through the lifetime of the system. This is problematic for a clock source which ought to be global. Avoid problems by always accessing cluster 0's counter, using cross-cluster register access. This adds overhead so it is applied only on multi-cluster systems. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Tested-by: Serge Semin Acked-by: Thomas Bogendoerfer Tested-by: Gregory CLEMENT --- drivers/clocksource/mips-gic-timer.c | 39 +++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mip= s-gic-timer.c index 110347707ff9..7907b740497a 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -166,6 +166,37 @@ static u64 gic_hpt_read(struct clocksource *cs) return gic_read_count(); } =20 +static u64 gic_hpt_read_multicluster(struct clocksource *cs) +{ + unsigned int hi, hi2, lo; + u64 count; + + mips_cm_lock_other(0, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + + if (mips_cm_is64) { + count =3D read_gic_redir_counter(); + goto out; + } + + hi =3D read_gic_redir_counter_32h(); + while (true) { + lo =3D read_gic_redir_counter_32l(); + + /* If hi didn't change then lo didn't wrap & we're done */ + hi2 =3D read_gic_redir_counter_32h(); + if (hi2 =3D=3D hi) + break; + + /* Otherwise, repeat with the latest hi value */ + hi =3D hi2; + } + + count =3D (((u64)hi) << 32) + lo; +out: + mips_cm_unlock_other(); + return count; +} + static struct clocksource gic_clocksource =3D { .name =3D "GIC", .read =3D gic_hpt_read, @@ -203,6 +234,11 @@ static int __init __gic_clocksource_init(void) gic_clocksource.rating =3D 200; gic_clocksource.rating +=3D clamp(gic_frequency / 10000000, 0, 99); =20 + if (mips_cps_multicluster_cpus()) { + gic_clocksource.read =3D &gic_hpt_read_multicluster; + gic_clocksource.vdso_clock_mode =3D VDSO_CLOCKMODE_NONE; + } + ret =3D clocksource_register_hz(&gic_clocksource, gic_frequency); if (ret < 0) pr_warn("Unable to register clocksource\n"); @@ -261,7 +297,8 @@ static int __init gic_clocksource_of_init(struct device= _node *node) * stable CPU frequency or on the platforms with CM3 and CPU frequency * change performed by the CPC core clocks divider. */ - if (mips_cm_revision() >=3D CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) { + if ((mips_cm_revision() >=3D CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) = && + !mips_cps_multicluster_cpus()) { sched_clock_register(mips_cm_is64 ? gic_read_count_64 : gic_read_count_2x32, gic_count_width, gic_frequency); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Paul Burton In multi-cluster MIPS I6500 systems there is a GIC in each cluster, each with its own counter. When a cluster powers up the counter will be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register. In single cluster systems, it has been fine to clear COUNTSTOP once in gic_clocksource_of_init() to start the counter. In multi-cluster systems, this will only have started the counter in the boot cluster, and any CPUs in other clusters will find their counter stopped which will break the GIC clock_event_device. Resolve this by having CPUs clear the COUNTSTOP bit when they come online, using the existing gic_starting_cpu() CPU hotplug callback. This will allow CPUs in secondary clusters to ensure that the cluster's GIC counter is running as expected. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Serge Semin Tested-by: Gregory CLEMENT --- drivers/clocksource/mips-gic-timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mip= s-gic-timer.c index 7907b740497a..abb685a080a5 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -115,6 +115,9 @@ static void gic_update_frequency(void *data) =20 static int gic_starting_cpu(unsigned int cpu) { + /* Ensure the GIC counter is running */ + clear_gic_config(GIC_CONFIG_COUNTSTOP); + gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); return 0; } @@ -288,9 +291,6 @@ static int __init gic_clocksource_of_init(struct device= _node *node) pr_warn("Unable to register clock notifier\n"); } =20 - /* And finally start the counter */ - clear_gic_config(GIC_CONFIG_COUNTSTOP); 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charset="utf-8" From: Paul Burton The pm-cps code has up until now used per-CPU variables indexed by core, rather than CPU number, in order to share data amongst sibling CPUs (ie. VPs/threads in a core). This works fine for single cluster systems, but with multi-cluster systems a core number is no longer unique in the system, leading to sharing between CPUs that are not actually siblings. Avoid this issue by using per-CPU variables as they are more generally used - ie. access them using CPU numbers rather than core numbers. Sharing between siblings is then accomplished by: - Assigning the same pointer to entries for each sibling CPU for the nc_asm_enter & ready_count variables, which allow this by virtue of being per-CPU pointers. - Indexing by the first CPU set in a CPUs cpu_sibling_map in the case of pm_barrier, for which we can't use the previous approach because the per-CPU variable is not a pointer. Signed-off-by: Paul Burton Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Tested-by: Serge Semin Tested-by: Gregory CLEMENT --- arch/mips/kernel/pm-cps.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index d09ca77e624d..9369a8dc385e 100644 --- a/arch/mips/kernel/pm-cps.c +++ b/arch/mips/kernel/pm-cps.c @@ -57,10 +57,7 @@ static DEFINE_PER_CPU_ALIGNED(u32*, ready_count); /* Indicates online CPUs coupled with the current CPU */ static DEFINE_PER_CPU_ALIGNED(cpumask_t, online_coupled); =20 -/* - * Used to synchronize entry to deep idle states. Actually per-core rather - * than per-CPU. - */ +/* Used to synchronize entry to deep idle states */ static DEFINE_PER_CPU_ALIGNED(atomic_t, pm_barrier); =20 /* Saved CPU state across the CPS_PM_POWER_GATED state */ @@ -112,9 +109,10 @@ int cps_pm_enter_state(enum cps_pm_state state) cps_nc_entry_fn entry; struct core_boot_config *core_cfg; struct vpe_boot_config *vpe_cfg; + atomic_t *barrier; =20 /* Check that there is an entry function for this state */ - entry =3D per_cpu(nc_asm_enter, core)[state]; + entry =3D per_cpu(nc_asm_enter, cpu)[state]; if (!entry) return -EINVAL; =20 @@ -150,7 +148,7 @@ int cps_pm_enter_state(enum cps_pm_state state) smp_mb__after_atomic(); =20 /* Create a non-coherent mapping of the core ready_count */ - core_ready_count =3D per_cpu(ready_count, core); + core_ready_count =3D per_cpu(ready_count, cpu); nc_addr =3D kmap_noncoherent(virt_to_page(core_ready_count), (unsigned long)core_ready_count); nc_addr +=3D ((unsigned long)core_ready_count & ~PAGE_MASK); @@ -158,7 +156,8 @@ int cps_pm_enter_state(enum cps_pm_state state) =20 /* Ensure ready_count is zero-initialised before the assembly runs */ WRITE_ONCE(*nc_core_ready_count, 0); - coupled_barrier(&per_cpu(pm_barrier, core), online); + barrier =3D &per_cpu(pm_barrier, cpumask_first(&cpu_sibling_map[cpu])); + coupled_barrier(barrier, online); =20 /* Run the generated entry code */ left =3D entry(online, nc_core_ready_count); @@ -629,12 +628,14 @@ static void *cps_gen_entry_code(unsigned cpu, enum cp= s_pm_state state) =20 static int cps_pm_online_cpu(unsigned int cpu) { - enum cps_pm_state state; - unsigned core =3D cpu_core(&cpu_data[cpu]); + unsigned int sibling, core; void *entry_fn, *core_rc; + enum cps_pm_state state; + + core =3D cpu_core(&cpu_data[cpu]); =20 for (state =3D CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) { - if (per_cpu(nc_asm_enter, core)[state]) + if (per_cpu(nc_asm_enter, cpu)[state]) continue; if (!test_bit(state, state_support)) continue; @@ -646,16 +647,19 @@ static int cps_pm_online_cpu(unsigned int cpu) clear_bit(state, state_support); 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charset="utf-8" From: Paul Burton In preparation for supporting multi-cluster systems, introduce a struct cluster_boot_config as an extra layer in the boot configuration maintained by the MIPS Coherent Processing System (CPS) SMP implementation. For now only one struct cluster_boot_config will be allocated & we'll simply defererence its core_config field to find the struct core_boot_config array which can be used to boot as usual. Signed-off-by: Paul Burton Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Tested-by: Serge Semin Tested-by: Gregory CLEMENT --- arch/mips/include/asm/smp-cps.h | 6 ++- arch/mips/kernel/asm-offsets.c | 3 ++ arch/mips/kernel/cps-vec.S | 19 ++++++-- arch/mips/kernel/pm-cps.c | 5 +- arch/mips/kernel/smp-cps.c | 82 +++++++++++++++++++++------------ 5 files changed, 81 insertions(+), 34 deletions(-) diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cp= s.h index ab94e50f62b8..a629e948a6fd 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -22,7 +22,11 @@ struct core_boot_config { struct vpe_boot_config *vpe_config; }; =20 -extern struct core_boot_config *mips_cps_core_bootcfg; +struct cluster_boot_config { + struct core_boot_config *core_config; +}; + +extern struct cluster_boot_config *mips_cps_cluster_bootcfg; =20 extern void mips_cps_core_boot(int cca, void __iomem *gcr_base); extern void mips_cps_core_init(void); diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index cb1045ebab06..b29944160b28 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -404,6 +404,9 @@ void output_cps_defines(void) { COMMENT(" MIPS CPS offsets. "); =20 + OFFSET(CLUSTERBOOTCFG_CORECONFIG, cluster_boot_config, core_config); + DEFINE(CLUSTERBOOTCFG_SIZE, sizeof(struct cluster_boot_config)); + OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask); OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config); DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config)); diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index f876309130ad..2ae7034a3d5c 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -19,6 +19,10 @@ #define GCR_CPC_BASE_OFS 0x0088 #define GCR_CL_COHERENCE_OFS 0x2008 #define GCR_CL_ID_OFS 0x2028 +#define CM3_GCR_Cx_ID_CLUSTER_SHF 8 +#define CM3_GCR_Cx_ID_CLUSTER_MSK (0xff << 8) +#define CM3_GCR_Cx_ID_CORENUM_SHF 0 +#define CM3_GCR_Cx_ID_CORENUM_MSK (0xff << 0) =20 #define CPC_CL_VC_STOP_OFS 0x2020 #define CPC_CL_VC_RUN_OFS 0x2028 @@ -271,12 +275,21 @@ LEAF(mips_cps_core_init) */ LEAF(mips_cps_get_bootcfg) /* Calculate a pointer to this cores struct core_boot_config */ + PTR_LA v0, mips_cps_cluster_bootcfg + PTR_L v0, 0(v0) lw t0, GCR_CL_ID_OFS(s1) +#ifdef CONFIG_CPU_MIPSR6 + ext t1, t0, CM3_GCR_Cx_ID_CLUSTER_SHF, 8 + li t2, CLUSTERBOOTCFG_SIZE + mul t1, t1, t2 + PTR_ADDU \ + v0, v0, t1 +#endif + PTR_L v0, CLUSTERBOOTCFG_CORECONFIG(v0) + andi t0, t0, CM3_GCR_Cx_ID_CORENUM_MSK li t1, COREBOOTCFG_SIZE mul t0, t0, t1 - PTR_LA t1, mips_cps_core_bootcfg - PTR_L t1, 0(t1) - PTR_ADDU v0, t0, t1 + PTR_ADDU v0, v0, t0 =20 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */ li t9, 0 diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index 9369a8dc385e..3de0e05e0511 100644 --- a/arch/mips/kernel/pm-cps.c +++ b/arch/mips/kernel/pm-cps.c @@ -101,12 +101,14 @@ static void coupled_barrier(atomic_t *a, unsigned onl= ine) int cps_pm_enter_state(enum cps_pm_state state) { unsigned cpu =3D smp_processor_id(); + unsigned int cluster =3D cpu_cluster(¤t_cpu_data); unsigned core =3D cpu_core(¤t_cpu_data); unsigned online, left; cpumask_t *coupled_mask =3D this_cpu_ptr(&online_coupled); u32 *core_ready_count, *nc_core_ready_count; void *nc_addr; cps_nc_entry_fn entry; + struct cluster_boot_config *cluster_cfg; struct core_boot_config *core_cfg; struct vpe_boot_config *vpe_cfg; atomic_t *barrier; @@ -136,7 +138,8 @@ int cps_pm_enter_state(enum cps_pm_state state) if (!mips_cps_smp_in_use()) return -EINVAL; =20 - core_cfg =3D &mips_cps_core_bootcfg[core]; + cluster_cfg =3D &mips_cps_cluster_bootcfg[cluster]; + core_cfg =3D &cluster_cfg->core_config[core]; vpe_cfg =3D &core_cfg->vpe_config[cpu_vpe_id(¤t_cpu_data)]; vpe_cfg->pc =3D (unsigned long)mips_cps_pm_restore; vpe_cfg->gp =3D (unsigned long)current_thread_info(); diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 395622c37325..f71e2bb58318 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -40,7 +40,7 @@ static DECLARE_BITMAP(core_power, NR_CPUS); static uint32_t core_entry_reg; static phys_addr_t cps_vec_pa; =20 -struct core_boot_config *mips_cps_core_bootcfg; +struct cluster_boot_config *mips_cps_cluster_bootcfg; =20 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) { @@ -212,8 +212,10 @@ static void __init cps_smp_setup(void) =20 static void __init cps_prepare_cpus(unsigned int max_cpus) { - unsigned ncores, core_vpes, c, cca; + unsigned int nclusters, ncores, core_vpes, c, cl, cca; bool cca_unsuitable, cores_limited; + struct cluster_boot_config *cluster_bootcfg; + struct core_boot_config *core_bootcfg; =20 mips_mt_set_cpuoptions(); =20 @@ -255,40 +257,54 @@ static void __init cps_prepare_cpus(unsigned int max_= cpus) =20 setup_cps_vecs(); =20 - /* Allocate core boot configuration structs */ - ncores =3D mips_cps_numcores(0); - mips_cps_core_bootcfg =3D kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), - GFP_KERNEL); - if (!mips_cps_core_bootcfg) { - pr_err("Failed to allocate boot config for %u cores\n", ncores); - goto err_out; - } + /* Allocate cluster boot configuration structs */ + nclusters =3D mips_cps_numclusters(); + mips_cps_cluster_bootcfg =3D kcalloc(nclusters, + sizeof(*mips_cps_cluster_bootcfg), + GFP_KERNEL); =20 - /* Allocate VPE boot configuration structs */ - for (c =3D 0; c < ncores; c++) { - core_vpes =3D core_vpe_count(0, c); - mips_cps_core_bootcfg[c].vpe_config =3D kcalloc(core_vpes, - sizeof(*mips_cps_core_bootcfg[c].vpe_config), - GFP_KERNEL); - if (!mips_cps_core_bootcfg[c].vpe_config) { - pr_err("Failed to allocate %u VPE boot configs\n", - core_vpes); + for (cl =3D 0; cl < nclusters; cl++) { + /* Allocate core boot configuration structs */ + ncores =3D mips_cps_numcores(cl); + core_bootcfg =3D kcalloc(ncores, sizeof(*core_bootcfg), + GFP_KERNEL); + if (!core_bootcfg) goto err_out; + mips_cps_cluster_bootcfg[cl].core_config =3D core_bootcfg; + + /* Allocate VPE boot configuration structs */ + for (c =3D 0; c < ncores; c++) { + core_vpes =3D core_vpe_count(cl, c); + core_bootcfg[c].vpe_config =3D kcalloc(core_vpes, + sizeof(*core_bootcfg[c].vpe_config), + GFP_KERNEL); + if (!core_bootcfg[c].vpe_config) + goto err_out; } } =20 /* Mark this CPU as booted */ - atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask, - 1 << cpu_vpe_id(¤t_cpu_data)); + cl =3D cpu_cluster(¤t_cpu_data); + c =3D cpu_core(¤t_cpu_data); + cluster_bootcfg =3D &mips_cps_cluster_bootcfg[cl]; + core_bootcfg =3D &cluster_bootcfg->core_config[c]; + atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(¤t_cpu_data)); =20 return; err_out: /* Clean up allocations */ - if (mips_cps_core_bootcfg) { - for (c =3D 0; c < ncores; c++) - kfree(mips_cps_core_bootcfg[c].vpe_config); - kfree(mips_cps_core_bootcfg); - mips_cps_core_bootcfg =3D NULL; + if (mips_cps_cluster_bootcfg) { + for (cl =3D 0; cl < nclusters; cl++) { + cluster_bootcfg =3D &mips_cps_cluster_bootcfg[cl]; + ncores =3D mips_cps_numcores(cl); + for (c =3D 0; c < ncores; c++) { + core_bootcfg =3D &cluster_bootcfg->core_config[c]; + kfree(core_bootcfg->vpe_config); + } + kfree(mips_cps_cluster_bootcfg[c].core_config); + } + kfree(mips_cps_cluster_bootcfg); + mips_cps_cluster_bootcfg =3D NULL; } =20 /* Effectively disable SMP by declaring CPUs not present */ @@ -376,17 +392,23 @@ static void boot_core(unsigned int core, unsigned int= vpe_id) =20 static void remote_vpe_boot(void *dummy) { + unsigned int cluster =3D cpu_cluster(¤t_cpu_data); unsigned core =3D cpu_core(¤t_cpu_data); - struct core_boot_config *core_cfg =3D &mips_cps_core_bootcfg[core]; + struct cluster_boot_config *cluster_cfg =3D + &mips_cps_cluster_bootcfg[cluster]; + struct core_boot_config *core_cfg =3D &cluster_cfg->core_config[core]; =20 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data)); } =20 static int cps_boot_secondary(int cpu, struct task_struct *idle) { + unsigned int cluster =3D cpu_cluster(&cpu_data[cpu]); unsigned core =3D cpu_core(&cpu_data[cpu]); unsigned vpe_id =3D cpu_vpe_id(&cpu_data[cpu]); - struct core_boot_config *core_cfg =3D &mips_cps_core_bootcfg[core]; + struct cluster_boot_config *cluster_cfg =3D + &mips_cps_cluster_bootcfg[cluster]; + struct core_boot_config *core_cfg =3D &cluster_cfg->core_config[core]; struct vpe_boot_config *vpe_cfg =3D &core_cfg->vpe_config[vpe_id]; unsigned int remote; int err; @@ -544,12 +566,14 @@ static void cps_kexec_nonboot_cpu(void) static int cps_cpu_disable(void) { unsigned cpu =3D smp_processor_id(); + struct cluster_boot_config *cluster_cfg; struct core_boot_config *core_cfg; =20 if (!cps_pm_support_state(CPS_PM_POWER_GATED)) return -EINVAL; =20 - core_cfg =3D &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)]; + cluster_cfg =3D &mips_cps_cluster_bootcfg[cpu_cluster(¤t_cpu_data)]; + core_cfg =3D &cluster_cfg->core_config[cpu_core(¤t_cpu_data)]; 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charset="utf-8" From: Paul Burton Probe for & boot CPUs (cores & VPs) in secondary clusters (ie. not the cluster that began booting Linux) when they are present in systems with CM 3.5 or higher. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Tested-by: Serge Semin Tested-by: Gregory CLEMENT --- arch/mips/include/asm/mips-cm.h | 18 +++ arch/mips/include/asm/smp-cps.h | 1 + arch/mips/kernel/mips-cm.c | 4 +- arch/mips/kernel/smp-cps.c | 205 ++++++++++++++++++++++++++++---- 4 files changed, 207 insertions(+), 21 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-c= m.h index 1e782275850a..4d47163647dd 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -255,6 +255,12 @@ GCR_ACCESSOR_RW(32, 0x130, l2_config) GCR_ACCESSOR_RO(32, 0x150, sys_config2) #define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0) =20 +/* GCR_L2-RAM_CONFIG - Configuration & status of L2 cache RAMs */ +GCR_ACCESSOR_RW(64, 0x240, l2_ram_config) +#define CM_GCR_L2_RAM_CONFIG_PRESENT BIT(31) +#define CM_GCR_L2_RAM_CONFIG_HCI_DONE BIT(30) +#define CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED BIT(29) + /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */ GCR_ACCESSOR_RW(32, 0x300, l2_pft_control) #define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12) @@ -266,6 +272,18 @@ GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b) #define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8) #define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0) =20 +/* GCR_L2_TAG_ADDR - Access addresses in L2 cache tags */ +GCR_ACCESSOR_RW(64, 0x600, l2_tag_addr) + +/* GCR_L2_TAG_STATE - Access L2 cache tag state */ +GCR_ACCESSOR_RW(64, 0x608, l2_tag_state) + +/* GCR_L2_DATA - Access data in L2 cache lines */ +GCR_ACCESSOR_RW(64, 0x610, l2_data) + +/* GCR_L2_ECC - Access ECC information from L2 cache lines */ +GCR_ACCESSOR_RW(64, 0x618, l2_ecc) + /* GCR_L2SM_COP - L2 cache op state machine control */ GCR_ACCESSOR_RW(32, 0x620, l2sm_cop) #define CM_GCR_L2SM_COP_PRESENT BIT(31) diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cp= s.h index a629e948a6fd..10d3ebd890cb 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -23,6 +23,7 @@ struct core_boot_config { }; =20 struct cluster_boot_config { + unsigned long *core_power; struct core_boot_config *core_config; }; =20 diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 3eb2cfb893e1..9854bc2b6895 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -308,7 +308,9 @@ void mips_cm_lock_other(unsigned int cluster, unsigned = int core, FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp); =20 if (cm_rev >=3D CM_REV_CM3_5) { - val |=3D CM_GCR_Cx_OTHER_CLUSTER_EN; + if (cluster !=3D cpu_cluster(¤t_cpu_data)) + val |=3D CM_GCR_Cx_OTHER_CLUSTER_EN; + val |=3D CM_GCR_Cx_OTHER_GIC_EN; val |=3D FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster); val |=3D FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block); } else { diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index f71e2bb58318..4f344c890a23 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -36,12 +36,56 @@ enum label_id { =20 UASM_L_LA(_not_nmi) =20 -static DECLARE_BITMAP(core_power, NR_CPUS); static uint32_t core_entry_reg; static phys_addr_t cps_vec_pa; =20 struct cluster_boot_config *mips_cps_cluster_bootcfg; =20 +static void power_up_other_cluster(unsigned int cluster) +{ + u32 stat, seq_state; + unsigned int timeout; + + mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, + CM_GCR_Cx_OTHER_BLOCK_LOCAL); + stat =3D read_cpc_co_stat_conf(); + mips_cm_unlock_other(); + + seq_state =3D stat & CPC_Cx_STAT_CONF_SEQSTATE; + seq_state >>=3D __ffs(CPC_Cx_STAT_CONF_SEQSTATE); + if (seq_state =3D=3D CPC_Cx_STAT_CONF_SEQSTATE_U5) + return; + + /* Set endianness & power up the CM */ + mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + write_cpc_redir_sys_config(IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)); + write_cpc_redir_pwrup_ctl(1); + mips_cm_unlock_other(); + + /* Wait for the CM to start up */ + timeout =3D 1000; + mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, + CM_GCR_Cx_OTHER_BLOCK_LOCAL); + while (1) { + stat =3D read_cpc_co_stat_conf(); + seq_state =3D stat & CPC_Cx_STAT_CONF_SEQSTATE; + seq_state >>=3D __ffs(CPC_Cx_STAT_CONF_SEQSTATE); + if (seq_state =3D=3D CPC_Cx_STAT_CONF_SEQSTATE_U5) + break; + + if (timeout) { + mdelay(1); + timeout--; + } else { + pr_warn("Waiting for cluster %u CM to power up... STAT_CONF=3D0x%x\n", + cluster, stat); + mdelay(1000); + } + } + + mips_cm_unlock_other(); +} + static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) { return min(smp_max_threads, mips_cps_numvps(cluster, core)); @@ -152,6 +196,9 @@ static void __init cps_smp_setup(void) pr_cont(","); pr_cont("{"); =20 + if (mips_cm_revision() >=3D CM_REV_CM3_5) + power_up_other_cluster(cl); + ncores =3D mips_cps_numcores(cl); for (c =3D 0; c < ncores; c++) { core_vpes =3D core_vpe_count(cl, c); @@ -179,8 +226,8 @@ static void __init cps_smp_setup(void) =20 /* Indicate present CPUs (CPU being synonymous with VPE) */ for (v =3D 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { - set_cpu_possible(v, cpu_cluster(&cpu_data[v]) =3D=3D 0); - set_cpu_present(v, cpu_cluster(&cpu_data[v]) =3D=3D 0); + set_cpu_possible(v, true); + set_cpu_present(v, true); __cpu_number_map[v] =3D v; __cpu_logical_map[v] =3D v; } @@ -188,9 +235,6 @@ static void __init cps_smp_setup(void) /* Set a coherent default CCA (CWB) */ change_c0_config(CONF_CM_CMASK, 0x5); =20 - /* Core 0 is powered up (we're running on it) */ - bitmap_set(core_power, 0, 1); - /* Initialise core 0 */ mips_cps_core_init(); =20 @@ -272,6 +316,10 @@ static void __init cps_prepare_cpus(unsigned int max_c= pus) goto err_out; mips_cps_cluster_bootcfg[cl].core_config =3D core_bootcfg; =20 + mips_cps_cluster_bootcfg[cl].core_power =3D + kcalloc(BITS_TO_LONGS(ncores), sizeof(unsigned long), + GFP_KERNEL); + /* Allocate VPE boot configuration structs */ for (c =3D 0; c < ncores; c++) { core_vpes =3D core_vpe_count(cl, c); @@ -283,11 +331,12 @@ static void __init cps_prepare_cpus(unsigned int max_= cpus) } } =20 - /* Mark this CPU as booted */ + /* Mark this CPU as powered up & booted */ cl =3D cpu_cluster(¤t_cpu_data); c =3D cpu_core(¤t_cpu_data); cluster_bootcfg =3D &mips_cps_cluster_bootcfg[cl]; core_bootcfg =3D &cluster_bootcfg->core_config[c]; + bitmap_set(cluster_bootcfg->core_power, cpu_core(¤t_cpu_data), 1); atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(¤t_cpu_data)); =20 return; @@ -315,13 +364,118 @@ static void __init cps_prepare_cpus(unsigned int max= _cpus) } } =20 -static void boot_core(unsigned int core, unsigned int vpe_id) +static void init_cluster_l2(void) { - u32 stat, seq_state; - unsigned timeout; + u32 l2_cfg, l2sm_cop, result; + + while (1) { + l2_cfg =3D read_gcr_redir_l2_ram_config(); + + /* If HCI is not supported, use the state machine below */ + if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_PRESENT)) + break; + if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED)) + break; + + /* If the HCI_DONE bit is set, we're finished */ + if (l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_DONE) + return; + } + + l2sm_cop =3D read_gcr_redir_l2sm_cop(); + if (WARN(!(l2sm_cop & CM_GCR_L2SM_COP_PRESENT), + "L2 init not supported on this system yet")) + return; + + /* Clear L2 tag registers */ + write_gcr_redir_l2_tag_state(0); + write_gcr_redir_l2_ecc(0); + + /* Ensure the L2 tag writes complete before the state machine starts */ + mb(); + + /* Wait for the L2 state machine to be idle */ + do { + l2sm_cop =3D read_gcr_redir_l2sm_cop(); + } while (l2sm_cop & CM_GCR_L2SM_COP_RUNNING); + + /* Start a store tag operation */ + l2sm_cop =3D CM_GCR_L2SM_COP_TYPE_IDX_STORETAG; + l2sm_cop <<=3D __ffs(CM_GCR_L2SM_COP_TYPE); + l2sm_cop |=3D CM_GCR_L2SM_COP_CMD_START; + write_gcr_redir_l2sm_cop(l2sm_cop); + + /* Ensure the state machine starts before we poll for completion */ + mb(); + + /* Wait for the operation to be complete */ + do { + l2sm_cop =3D read_gcr_redir_l2sm_cop(); + result =3D l2sm_cop & CM_GCR_L2SM_COP_RESULT; + result >>=3D __ffs(CM_GCR_L2SM_COP_RESULT); + } while (!result); + + WARN(result !=3D CM_GCR_L2SM_COP_RESULT_DONE_OK, + "L2 state machine failed cache init with error %u\n", result); +} + +static void boot_core(unsigned int cluster, unsigned int core, + unsigned int vpe_id) +{ + struct cluster_boot_config *cluster_cfg; + u32 access, stat, seq_state; + unsigned int timeout, ncores; + + cluster_cfg =3D &mips_cps_cluster_bootcfg[cluster]; + ncores =3D mips_cps_numcores(cluster); + + if ((cluster !=3D cpu_cluster(¤t_cpu_data)) && + bitmap_empty(cluster_cfg->core_power, ncores)) { + power_up_other_cluster(cluster); + + mips_cm_lock_other(cluster, core, 0, + CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + + /* Ensure cluster GCRs are where we expect */ + write_gcr_redir_base(read_gcr_base()); + write_gcr_redir_cpc_base(read_gcr_cpc_base()); + write_gcr_redir_gic_base(read_gcr_gic_base()); + + init_cluster_l2(); + + /* Mirror L2 configuration */ + write_gcr_redir_l2_only_sync_base(read_gcr_l2_only_sync_base()); + write_gcr_redir_l2_pft_control(read_gcr_l2_pft_control()); + write_gcr_redir_l2_pft_control_b(read_gcr_l2_pft_control_b()); + + /* Mirror ECC/parity setup */ + write_gcr_redir_err_control(read_gcr_err_control()); + + /* Set BEV base */ + write_gcr_redir_bev_base(core_entry_reg); + + mips_cm_unlock_other(); + } + + if (cluster !=3D cpu_cluster(¤t_cpu_data)) { + mips_cm_lock_other(cluster, core, 0, + CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + + /* Ensure the core can access the GCRs */ + access =3D read_gcr_redir_access(); + access |=3D BIT(core); + write_gcr_redir_access(access); + + mips_cm_unlock_other(); + } else { + /* Ensure the core can access the GCRs */ + access =3D read_gcr_access(); + access |=3D BIT(core); + write_gcr_access(access); + } =20 /* Select the appropriate core */ - mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); + mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); =20 /* Set its reset vector */ write_gcr_co_reset_base(core_entry_reg); @@ -387,7 +541,17 @@ static void boot_core(unsigned int core, unsigned int = vpe_id) mips_cm_unlock_other(); =20 /* The core is now powered up */ - bitmap_set(core_power, core, 1); + bitmap_set(cluster_cfg->core_power, core, 1); + + /* + * Restore CM_PWRUP=3D0 so that the CM can power down if all the cores in + * the cluster do (eg. if they're all removed via hotplug. + */ + if (mips_cm_revision() >=3D CM_REV_CM3_5) { + mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); + write_cpc_redir_pwrup_ctl(0); + mips_cm_unlock_other(); + } } =20 static void remote_vpe_boot(void *dummy) @@ -413,10 +577,6 @@ static int cps_boot_secondary(int cpu, struct task_str= uct *idle) unsigned int remote; int err; =20 - /* We don't yet support booting CPUs in other clusters */ - if (cpu_cluster(&cpu_data[cpu]) !=3D cpu_cluster(&raw_current_cpu_data)) - return -ENOSYS; - vpe_cfg->pc =3D (unsigned long)&smp_bootstrap; vpe_cfg->sp =3D __KSTK_TOS(idle); vpe_cfg->gp =3D (unsigned long)task_thread_info(idle); @@ -425,14 +585,15 @@ static int cps_boot_secondary(int cpu, struct task_st= ruct *idle) =20 preempt_disable(); =20 - if (!test_bit(core, core_power)) { + if (!test_bit(core, cluster_cfg->core_power)) { /* Boot a VPE on a powered down core */ - boot_core(core, vpe_id); + boot_core(cluster, core, vpe_id); goto out; } =20 if (cpu_has_vp) { - mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); + mips_cm_lock_other(cluster, core, vpe_id, + CM_GCR_Cx_OTHER_BLOCK_LOCAL); write_gcr_co_reset_base(core_entry_reg); mips_cm_unlock_other(); } @@ -639,11 +800,15 @@ static void cps_cpu_die(unsigned int cpu) { } =20 static void cps_cleanup_dead_cpu(unsigned cpu) { + unsigned int cluster =3D cpu_cluster(&cpu_data[cpu]); unsigned core =3D cpu_core(&cpu_data[cpu]); unsigned int vpe_id =3D cpu_vpe_id(&cpu_data[cpu]); ktime_t fail_time; unsigned stat; int err; + struct cluster_boot_config *cluster_cfg; + + cluster_cfg =3D &mips_cps_cluster_bootcfg[cluster]; =20 /* * Now wait for the CPU to actually offline. Without doing this that @@ -695,7 +860,7 @@ static void cps_cleanup_dead_cpu(unsigned cpu) } while (1); =20 /* Indicate the core is powered off */ - bitmap_clear(core_power, core, 1); + bitmap_clear(cluster_cfg->core_power, core, 1); } else if (cpu_has_mipsmt) { /* * Have a CPU with access to the offlined CPUs registers wait --=20 2.25.1 From nobody Tue Nov 26 08:51:56 2024 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D28741DFE0F; Sat, 19 Oct 2024 07:11:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729321866; cv=none; b=ibQTMeJNeaXNF/eLM0PLrFtW3S7CKzjzeqYneukA+4KUoLokwxr4D8N/2sc5dKWttmlH+Hm5qLIhS5IjoVZV2MgnyMvyd+kR58KsuX+cayvBpvUzLEAsCes3pgMCUO8lDtasLblDRzCySf/hZWInYHeg2IDrhldlzKtCRKAUPRE= ARC-Message-Signature: i=1; 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Sat, 19 Oct 2024 00:11:02 -0700 (PDT) From: Aleksandar Rikalo To: Thomas Bogendoerfer Cc: Aleksandar Rikalo , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Gregory CLEMENT Subject: [PATCH v7 10/12] dt-bindings: mips: cpu: Add property for broken HCI information Date: Sat, 19 Oct 2024 09:10:35 +0200 Message-Id: <20241019071037.145314-11-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241019071037.145314-1-arikalo@gmail.com> References: <20241019071037.145314-1-arikalo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Gregory CLEMENT Some CM3.5 reports show that Hardware Cache Initialization is complete, but in reality it's not the case. They also incorrectly indicate that Hardware Cache Initialization is supported. This optional property allows warning about this broken feature that cannot be detected at runtime. Signed-off-by: Gregory CLEMENT Signed-off-by: Aleksandar Rikalo Tested-by: Gregory CLEMENT --- Documentation/devicetree/bindings/mips/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentati= on/devicetree/bindings/mips/cpus.yaml index a85137add668..57e93c07ab1b 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -47,6 +47,12 @@ properties: clocks: maxItems: 1 =20 + cm3-l2-config-hci-broken: + type: boolean + description: + If present, indicates that the HCI (Hardware Cache Initialization) + information for the L2 cache in multi-cluster configuration is broke= n. + device_type: true =20 allOf: --=20 2.25.1 From nobody Tue Nov 26 08:51:56 2024 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8193C1DFE31; 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charset="utf-8" From: Gregory CLEMENT Some CM3.5 devices incorrectly report that hardware cache initialization has completed, and also claim to support hardware cache initialization when they don't actually do so. This commit fixes this issue by retrieving the correct information from the device tree and allowing the system to bypass the hardware cache initialization step. Instead, it relies on manual operation. As a result, multi-user support is now possible for these CPUs. Signed-off-by: Gregory CLEMENT Signed-off-by: Aleksandar Rikalo Tested-by: Gregory CLEMENT --- arch/mips/kernel/smp-cps.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 4f344c890a23..265cf52c0dd1 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -39,6 +39,7 @@ UASM_L_LA(_not_nmi) static uint32_t core_entry_reg; static phys_addr_t cps_vec_pa; =20 +static bool l2_hci_broken; struct cluster_boot_config *mips_cps_cluster_bootcfg; =20 static void power_up_other_cluster(unsigned int cluster) @@ -254,6 +255,22 @@ static void __init cps_smp_setup(void) #endif /* CONFIG_MIPS_MT_FPAFF */ } =20 +static void __init check_hci_quirk(void) +{ + struct device_node *np; + + np =3D of_cpu_device_node_get(0); + if (!np) { + pr_debug("%s: No cpu node in the device tree\n", __func__); + return; + } + + if (of_property_read_bool(np, "cm3-l2-config-hci-broken")) { + pr_info("HCI (Hardware Cache Init for the L2 cache) in GCR_L2_RAM_CONFIG= from the CM3 is broken"); + l2_hci_broken =3D true; + } +} + static void __init cps_prepare_cpus(unsigned int max_cpus) { unsigned int nclusters, ncores, core_vpes, c, cl, cca; @@ -307,6 +324,9 @@ static void __init cps_prepare_cpus(unsigned int max_cp= us) sizeof(*mips_cps_cluster_bootcfg), GFP_KERNEL); =20 + if (nclusters > 1) + check_hci_quirk(); + for (cl =3D 0; cl < nclusters; cl++) { /* Allocate core boot configuration structs */ ncores =3D mips_cps_numcores(cl); @@ -368,7 +388,7 @@ static void init_cluster_l2(void) { u32 l2_cfg, l2sm_cop, result; =20 - while (1) { + while (!l2_hci_broken) { l2_cfg =3D read_gcr_redir_l2_ram_config(); =20 /* If HCI is not supported, use the state machine below */ --=20 2.25.1 From nobody Tue Nov 26 08:51:56 2024 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41B921E00B9; Sat, 19 Oct 2024 07:11:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sat, 19 Oct 2024 00:11:06 -0700 (PDT) Received: from localhost.localdomain ([79.175.114.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a68c27841sm180566666b.192.2024.10.19.00.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 00:11:05 -0700 (PDT) From: Aleksandar Rikalo To: Thomas Bogendoerfer Cc: Aleksandar Rikalo , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Gregory CLEMENT Subject: [PATCH v7 12/12] MIPS: mobileye: dts: eyeq6h: Enable cluster support Date: Sat, 19 Oct 2024 09:10:37 +0200 Message-Id: <20241019071037.145314-13-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241019071037.145314-1-arikalo@gmail.com> References: <20241019071037.145314-1-arikalo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Gregory CLEMENT The CM3.5 device used in EyeQ6H SoCs incorrectly reports the status for Hardware Cache Initialization (HCI). This commit adds a property to acknowledge this issue, which enables the use of the second CPU cluster. Signed-off-by: Gregory CLEMENT Signed-off-by: Aleksandar Rikalo Tested-by: Gregory CLEMENT --- arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/m= obileye/eyeq6h.dtsi index 1db3c3cda2e3..4ea85dfd4eed 100644 --- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi @@ -18,6 +18,7 @@ cpu@0 { compatible =3D "img,i6500"; reg =3D <0>; clocks =3D <&occ_cpu>; + cm3-l2-config-hci-broken; }; }; =20 --=20 2.25.1