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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a15211401sm562854e87.249.2024.10.19.08.44.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 08:44:57 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 19 Oct 2024 18:44:50 +0300 Subject: [PATCH 1/6] dt-bindings: phy: qcom,sc8280xp-qmp-usb32dp: Add SAR2130P compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-sar2130p-phys-v1-1-bf06fcea2421@linaro.org> References: <20241019-sar2130p-phys-v1-0-bf06fcea2421@linaro.org> In-Reply-To: <20241019-sar2130p-phys-v1-0-bf06fcea2421@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1186; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=7YeWftVlP2Q/gQUZRfbjxaxvlZtz7wnpUr40ZoRjqrc=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnE9P04c176Lp6PlkKHTtQNcyBZlmQqiRmS90eL BqCRp/dG1KJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxPT9AAKCRAU23LtvoBl uLwREAC/Rot4b1mZDwpJkc19mL9TWbVb4G7FYdhmYx0lS0TPeLkuKAF5GGgvRkUz+Gw98ONtcPL x8FMGvCINy4j4Rzklsp3JhvEXwWB2DnEEQ6AJR8JQcjh0y4L8aV7J8f7D5tfh1iT3O0KFndwwCJ C9asvyApUBtYVNB8Uc9zXApjrRwYSKsVKQpwSSNERy81HZUGpHAtNIixGk4DWZ5snbeHrCEdUcL V5AsyjvJzvnuaSIAbziYxNBleOu36T1g6Dhp6PcnJqjY6+xw99sfVAeQO3LtJGm+cYvn4UTl6mT S8l768DGzojR1qt6sITTvpuLYEKHHyR4W8JJzj3izsQke9HBZpI7i+I9LgLhscwRVOCxt0TGYBG O5pdm6NA1IJRN9kipSwYSo89tTJjsC5LztG/YhncjZVBVIBk/S4GpogN6oHpReeTGK2jpgIKZSp 9mxiKSc27AFg0y8HaD3Fx2PwSfLec6KC7TOSQRsIjQDRNBk7moR2BpYUop0VxWco3MZOUDfA6lJ iVzKhquWsBzHZiUxtTX/1ZCjkGB+mf8xa3Cr8vvWDWM73cA9uyBCSSsw23n0ncj0N0+EpgMXf0v 2egTt5NoY9Gvrjdk3dqM87gcYXQd2LpPsf3ULsmUJojY7c3xLMeJRn7e0Cv2mjvpxcxOCkAIr+v lpNUmQvwR/pEssg== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Document compatible for the USB+DP Combo PHY on SAR2130P platform. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | = 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml index 2d0d7e9e643117f5ec625e49270ac94c70603e7e..358a6736a951ca5db7cff7385b3= 657976a667358 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,sar2130p-qmp-usb3-dp-phy - qcom,sc7180-qmp-usb3-dp-phy - qcom,sc7280-qmp-usb3-dp-phy - qcom,sc8180x-qmp-usb3-dp-phy @@ -127,6 +128,7 @@ allOf: properties: compatible: enum: + - qcom,sar2130p-qmp-usb3-dp-phy - qcom,sc8280xp-qmp-usb43dp-phy - qcom,sm6350-qmp-usb3-dp-phy - qcom,sm8550-qmp-usb3-dp-phy --=20 2.39.5 From nobody Tue Nov 26 08:27:33 2024 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6EDA18C333 for ; Sat, 19 Oct 2024 15:45:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729352705; cv=none; b=Ao2v9hJCBmRv8C7kUXvKmFM4Lq4nSc3wbmKKZqDQ5uiohT0webbhxSE5h38oKMcf22SnarJlyWH2xApf5WmJFpDJkep25FtnAL/MZWJvMyy+/3gn+RUYaz6ipl3HLSakpF2mFhU2zrHr4kcL7Ucf3RsMtEfAjIeFGMi6DkRi35Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729352705; c=relaxed/simple; bh=5Y/fABq9b4vk+PutXYP52URTjzKP/DzFXovrE11VWQU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vqm5MZjfDZ9PFP+YDgjwFlex3tbqx91iDFA+XJbTp2EMWXh+xZ47kXwJLLSwE85FHMUEimKL5qVTdjvgRByPABsSbwK8S5/s6Mq1VcmjWI7Q7tWkVoaJBEG0rRlvy4FVahwLOU0/7N8tpGSQgpfkpyKet3lnwsgbEx4TgxDMHrw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=EWOA8Ub1; arc=none smtp.client-ip=209.85.208.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EWOA8Ub1" Received: by mail-lj1-f177.google.com with SMTP id 38308e7fff4ca-2fabb837ddbso44116371fa.1 for ; Sat, 19 Oct 2024 08:45:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729352701; x=1729957501; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gYfkdNF3O8TZS4V0T1JegIJYADXSJj7bD5ghT8EX1Qg=; b=EWOA8Ub1XQChankSp9rkAGqUxRsWu7kRSrdWaLbnMtulLezgkJUHD5r55B9SKNqQEC PtqY1+o7ZlNQMKjkVqrdrlGGqk4Qkd2mGV3L1j3kPOX2h0P9GCWwmEd8ZySyPp/T7HNQ H8EcJ5y179BJhApZbLqXelds/M1LQaf+s7ktWWLh8cvIHwXuBgvoQcVUMCJkiBqXVeK/ +vlwWqi+iNmwNXE4WHCdlvttkXft2QnGcsW0Z0XtIAWJ7G8ySGmbAss1xIP9PHIg5Ofy 9fouvBDGjOhaULAnKgeIgePeqi2KhDuvzVo3LE+BRhQr1BzRt9TlswoKUtsGUVhJiHQB Ap0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729352701; x=1729957501; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gYfkdNF3O8TZS4V0T1JegIJYADXSJj7bD5ghT8EX1Qg=; b=NNYhWTaxEzPVWUk6veZ6U9ey0RZ7PG8XcjVP/hoPH0s2Og0m0qBtH04nV103lhrx15 CybVRJRYhZBQsyLHO/IHZuRt/N8WKzceBd2X8xy2suFMAaxaANzOnVe+O9UAtN8/Usby IU6gQqTQxdpqMEJX8UvODtiYbhKiGNzuGFJFgMCsYMMceyUVKGCz3nrj05Rmk2dZF/7s oevDWXjZXoQKya9J3Rzxvfb6aEGH14qxtxMtNDzvht1mErGjK2Q013KoNY2/cMpxTGGT KmP+lwNmBIF4J4SuEJfHhc/xNSl9/Qf6AhPoKWP+RF5/glM5djm8wX6faubRj282y7dC n7Hg== X-Forwarded-Encrypted: i=1; AJvYcCX8lyN4G/cZOloWoVli71MIsoX910jevpT27604BabjjVLxRl8nav2t3HQUfVv9QKnN9V6wJgYF9rZJX3g=@vger.kernel.org X-Gm-Message-State: AOJu0YyW7w6JlAw0RibMK/1GhbHm52RSe2jxUTX/3tX2piS07CkHYS4Q aUqGC/nfnX6ZJ1qgkemdSymCd/GPfaJ5kmZkS9cllDZioaFUBCUzBHWVuMHQHsw= X-Google-Smtp-Source: AGHT+IGH6Y5P6FyFHKtLYJ0fUjT05rH9kh6VARZhWP0R9zDdHuzkdQyoqFz2sXtSlq05GusZGgw/YA== X-Received: by 2002:a05:6512:1188:b0:539:8f3c:4586 with SMTP id 2adb3069b0e04-53a154da832mr5560399e87.55.1729352701053; Sat, 19 Oct 2024 08:45:01 -0700 (PDT) Received: from [127.0.1.1] (2001-14ba-a0c3-3a00-70b-e6fc-b322-6a1b.rev.dnainternet.fi. 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Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 = ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 3c16330a58ec68da32486637e02ae89af9a06a3a..9b3b6fedd70ee924e7757ce531b= dab0fb6a3cd8d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy + - qcom,sar2130p-qmp-gen3x2-pcie-phy - qcom,sc8180x-qmp-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy @@ -139,6 +140,7 @@ allOf: compatible: contains: enum: + - qcom,sar2130p-qmp-gen3x2-pcie-phy - qcom,sc8180x-qmp-pcie-phy - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy --=20 2.39.5 From nobody Tue Nov 26 08:27:33 2024 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1AA118D65C for ; Sat, 19 Oct 2024 15:45:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729352707; cv=none; b=Yzsh9HO3fneF3d0rEcbgC30YhyEbYXs/LMOcV10fa6oqWMSRHVoQWpdjiHia10czwV2DJhDevP0nJ4MmCQm2WO0xK4/I+o+J9vmKfgv0s3bqQrWsKQpVkOH9J7adYFsbyVYdOIQsehNFH6SBobfjutZ6fPK3wSoIeDOulc2zbqY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729352707; c=relaxed/simple; bh=wqC70bOah27TMfxQ2glRfy3QrAMoCD3pFAIgaonQdmQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ntaOX4l+KYo7dWMb02TsT9NFCLqeWqd65b8/SwuPMcVpxH3QpDg68OqPx44sDpAwUMHbjCPQ68J5HX8M+skc8rECrdfk0k/Wma8TtXXEt7o5+re5f4iyOHQfD8aPCMy6e3RsSQNU9jDOtWFp86VuTQakyQiNmG4Q1zbzzPpytYI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=m0CxVHr/; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="m0CxVHr/" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-539983beb19so3461477e87.3 for ; Sat, 19 Oct 2024 08:45:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729352703; x=1729957503; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rN0Z8gyf6mR0qAxMHxD4icK0YDjnXtFcT7Z/8yHw46M=; b=m0CxVHr/P64bmL5Z4pQ0VND/XKe0MODqgsiA60ux0DmAhi8pLxWyqUy5VKyxIYXh/S pxqHqiMaoBflvIAA5ejjq5EFOhZEaUg4b+1xXMMnjeTQ01A8kzIMUFNhfByISUpWd8yE zxoY5MV3zW9GS9hpUAg9PZAe4ueAQ1CQsob3LjJeX5/EOtk5/OOND8ACi3Wnn+Pwh7gE L2sg8vDhpzQdPZCUMYVsamAVsEla8kAD6sYFLvpXZgADp5vyjHH1xYXh9UnETt3GWKal 6o3GGgtCgVnsf/l/B7/AtipEEwUkSTRFWhW90q3kjcLDQu5jE07jY7Xce1UtVuXmWHmD H5GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729352703; x=1729957503; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rN0Z8gyf6mR0qAxMHxD4icK0YDjnXtFcT7Z/8yHw46M=; b=hUZDDLXwYIumivlBptt9zcIOIrer/XPXdL1lVTL6M20iFm3Nt99uf6qXra+oTQl36V AqgMyVFXo5hllKBQAYzfWiNTRQ15HbUTC4qBBHZySlbaoj1vMWAvnNd+kUWY4UQBC0ji 2Qttu2igsPXOpiQF9XzbSWdnRvLTmE8ibvIF7nusZGVgEJQ/SnY6hoe8gUAHBgdmcgvm c8xpt2XBr7Mp1nth1CPL9g9dhvCAUnOK0KlGqtsKYvpJEZXUXgwW9C1Sq5NBKQmc5Kax YPx6SxrLY56F3706xH1fQjaZyev0177PRoFUoQV6HBeTiF1HxGAmTcnzI64FSQYrf84W 1aww== X-Forwarded-Encrypted: i=1; AJvYcCWn6fFlyWEioOBQc+vIj/kH/d6Np1hzfoqQtWhaZBNL/GsixnMvXbMcN+J+T9KiJ2K6yxBaF6Z+Lqkf2oY=@vger.kernel.org X-Gm-Message-State: AOJu0Yz3aWTMLz9A7oxPjhOKBzLeQ7HvYxyGcOG4dFAxPnL7/l0/8K0/ rAG/Kl0ZkUuuNteBpBZzqKZUDAEPSlTWl0AeKMXrD7QnduA/UFqIyvl61Fb+PAI= X-Google-Smtp-Source: AGHT+IEay7Vo2Kk2nzsC3j+Ne4YxOJWR+srmUQz0G5GEAGaEz01t6UUWXMTE04zP6RKDs3g7ratJzQ== X-Received: by 2002:a05:6512:3b2a:b0:539:8e77:9129 with SMTP id 2adb3069b0e04-53a154e7787mr3021542e87.44.1729352702668; Sat, 19 Oct 2024 08:45:02 -0700 (PDT) Received: from [127.0.1.1] (2001-14ba-a0c3-3a00-70b-e6fc-b322-6a1b.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a15211401sm562854e87.249.2024.10.19.08.45.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 08:45:02 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 19 Oct 2024 18:44:52 +0300 Subject: [PATCH 3/6] phy: qualcomm: qmp-combo: add support for SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-sar2130p-phys-v1-3-bf06fcea2421@linaro.org> References: <20241019-sar2130p-phys-v1-0-bf06fcea2421@linaro.org> In-Reply-To: <20241019-sar2130p-phys-v1-0-bf06fcea2421@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6620; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=wqC70bOah27TMfxQ2glRfy3QrAMoCD3pFAIgaonQdmQ=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnE9P07to+EHtNhIlWbSg8/s0Np9BFsUq0QQW0q 2NgqCJ8zUyJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxPT9AAKCRAU23LtvoBl uE9VD/0cApzW125RB8c12QVXYjdBT86M/q1XHNZ2hJTJOJ5V8mrLWJUuzYz9SszXd3J2P27xQKV BwV5fDv92xDagGuX5xiXbTZq2P0EKbYVR2KVViQ/wv4DqTs6jH3VgAf4hQjw7WWHij5A+UmKJTe 1fbkzZtDiqyhtTzmz7kOLLwOraChF9vZZ7lDVolJRxEf0ZIkmuf1obePDMOwAl2U5K9TLoXYkzY Yml8VRoWSsWEMBZ6YCKgtr+EnwZeFBaawRNl3bT+kQUbqyXCf+elfSmuhl/UjrzopXvYphBVQqf wwQ/iv6Yp2DwsYLT6XUZieEFs97lid+FgWFhBg63KWMtapLJ9sz4usxrlPCYTOFtQ+yVVn5srmx TRQlC9a43iuDZBIPUrnTN1+dtwS+N56kctHbPa91w7QxlG1JCM2bI8l7eQCLA0I5oYmbxCr+c47 3BmrM6CFgOFevcDm8KvRUZMjX3YDkc1msmpbhah6GgfmYr4xVNolkjMtaUcCY/9sikGobwtkYIL d2go8E0XA0x8YbiscRQiRF7F4C80XnnRh38gUik/ugiknduGdtJYdEMJrpm4ppPsrssvpKiK4NB wDViJqSc1+SaQrybx97Ts8hkrfarFy33NyWRXNVC/wg32xEGXndSxhxM9wFZnzgardAwLMInzni yuoZQ74HMUOSXlA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Extend the USB+DP combo QMP PHY driver to support the SAR2130P platform. It mosly follows the SM8550 QMP PHY, but the QSERDES programming differs, most likely because of the parent clock rate differences. NOTE: The DP part wasn't yet tested, but it is not possible to support just the USB part of the PHY. DP part might require additional fixes later. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 100 ++++++++++++++++++++++++++= ++++ 1 file changed, 100 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 643045c9024eaa5de81f64ecfd10ff8845faf120..05ec1a0226460d23873db1dfe9d= cbc6ce1953b2e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -400,6 +400,57 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_t= bl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), }; =20 +static const struct qmp_phy_init_tbl sar2130p_usb3_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), +}; + static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), @@ -1730,6 +1781,51 @@ static const struct qmp_combo_offsets qmp_combo_offs= ets_v5 =3D { .dp_dp_phy =3D 0x2200, }; =20 +static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg =3D { + .offsets =3D &qmp_combo_offsets_v3, + + .serdes_tbl =3D sar2130p_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sar2130p_usb3_serdes_tbl), + .tx_tbl =3D sm8550_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8550_usb3_tx_tbl), + .rx_tbl =3D sm8550_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8550_usb3_rx_tbl), + .pcs_tbl =3D sm8550_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8550_usb3_pcs_tbl), + .pcs_usb_tbl =3D sm8550_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), + + .dp_serdes_tbl =3D qmp_v6_dp_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), + + .serdes_tbl_rbr =3D qmp_v6_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + + .swing_hbr_rbr =3D &qmp_dp_v5_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 =3D &qmp_dp_v5_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 =3D &qmp_dp_v5_pre_emphasis_hbr3_hbr2, + + .dp_aux_init =3D qmp_v4_dp_aux_init, + .configure_dp_tx =3D qmp_v4_configure_dp_tx, + .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .calibrate_dp_phy =3D qmp_v4_calibrate_dp_phy, + + .regs =3D qmp_v6_usb3phy_regs_layout, + .reset_list =3D msm8996_usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), +}; 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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a15211401sm562854e87.249.2024.10.19.08.45.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 08:45:03 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 19 Oct 2024 18:44:53 +0300 Subject: [PATCH 4/6] phy: qualcomm: qmp-pcie: split PCS_LANE1 region Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-sar2130p-phys-v1-4-bf06fcea2421@linaro.org> References: <20241019-sar2130p-phys-v1-0-bf06fcea2421@linaro.org> In-Reply-To: <20241019-sar2130p-phys-v1-0-bf06fcea2421@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7955; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=UXDmPJ/23z2ls62ryM86x4tjZRAeCfpbFyCc69y6OPU=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnE9P1qY1h1AOxKKBEm0O74ADM+dBq1qmX6rzRp np5nfdjlS2JAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxPT9QAKCRAU23LtvoBl uNe7D/49mcsIppX3ofS6BCffYDKaPjm6GlPF+t3IzWGGSpsEugPUAkdRUySh7kOLSH/viWaCBuR wiiKg0EQc18fgXHj+ZiMQlBHq67wRvjbPiTK/KRdLJPjSmyRzdaO4D1+GThr8UcBDcmeB3e91hG MLLZ0EZ1+AJebvijywzvNYHBPbZ47qwa0ehVrvmBf+mRkOfzBQYa8ZsoViA/QLZoowy4g8W1RP1 gTcpuxfcgyFLLVRRuGu53e52InObpAdipHxPdQ+n1CxhOgv5nPksMGms2gT31lLyEUHQqi3tK+w 4GO2ZlGzagpdaMItnZsCm1kiaA+z+v3r83C4fV/XqSuj6NqKDOVBjpY7qUlTxepxQO/difIMv01 0sbUKK1K1jAyPXT1t7QqWhxfS+MXy/ZTyGB4laRpEBMIwVOLtXV/FX0r+2l3uUN3/04z0FJmei8 MztM1dSJVf5W1JAAeAHO3Zanvz5oMTU4AoPjtyrONucPz5XiO8FCOpqx3aeMvVwgJynBR6q+lTU +bGP3HZKPEbcgQPj70KtojbymF0KvqKjzhIUA5h+sE9hmi4E++OwiLs0sYm0CnpwU2GF6W7DuKW 1l+JVbuTDIrFD9CqH1KWBxhyMRcfD7r2iFg25gYFaEcfxLrakuAfnqXUrCB0ctx8j4KhzNcONbu +ONEftQvj1Gklsw== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled this way as it simplified handled of devices with the old bindings. Nowadays it can be handled as is, without hacks. Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 32 ++++++++++++++++++= ---- drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 5 ++-- drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 5 ++-- 3 files changed, 33 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 873f2f9844c66d7bd0b3bb3ab4bbd8be9a37cebd..1ca1f21b1cc225f435da9c775c9= 7dfa142117f95 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1773,7 +1773,7 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_r= c_pcs_misc_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), }; =20 -static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] =3D { +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_lane1_tbl[] =3D= { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), }; @@ -1907,6 +1907,9 @@ static const struct qmp_phy_init_tbl sdx65_qmp_pcie_p= cs_misc_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d), QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), +}; + +static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), }; @@ -2582,8 +2585,6 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4= _pcie_rc_pcs_misc_tbl[] =3D { static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[]= =3D { QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), }; @@ -2728,6 +2729,7 @@ struct qmp_pcie_offsets { u16 serdes; u16 pcs; u16 pcs_misc; + u16 pcs_lane1; u16 tx; u16 rx; u16 tx2; @@ -2752,6 +2754,8 @@ struct qmp_phy_cfg_tbls { int pcs_num; const struct qmp_phy_init_tbl *pcs_misc; int pcs_misc_num; + const struct qmp_phy_init_tbl *pcs_lane1; + int pcs_lane1_num; const struct qmp_phy_init_tbl *ln_shrd; int ln_shrd_num; }; @@ -2811,6 +2815,7 @@ struct qmp_pcie { void __iomem *serdes; void __iomem *pcs; void __iomem *pcs_misc; + void __iomem *pcs_lane1; void __iomem *tx; void __iomem *rx; void __iomem *tx2; @@ -2927,6 +2932,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets= _v4_20 =3D { .serdes =3D 0x1000, .pcs =3D 0x1200, .pcs_misc =3D 0x1600, + .pcs_lane1 =3D 0x1e00, .tx =3D 0x0000, .rx =3D 0x0200, .tx2 =3D 0x0800, @@ -2957,6 +2963,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets= _v5_20 =3D { .serdes =3D 0x1000, .pcs =3D 0x1200, .pcs_misc =3D 0x1400, + .pcs_lane1 =3D 0x1e00, .tx =3D 0x0000, .rx =3D 0x0200, .tx2 =3D 0x0800, @@ -3440,8 +3447,8 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg= =3D { .tbls_ep =3D &(const struct qmp_phy_cfg_tbls) { .serdes =3D sdx55_qmp_pcie_ep_serdes_tbl, .serdes_num =3D ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), - .pcs_misc =3D sdx55_qmp_pcie_ep_pcs_misc_tbl, - .pcs_misc_num =3D ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), + .pcs_lane1 =3D sdx55_qmp_pcie_ep_pcs_lane1_tbl, + .pcs_lane1_num =3D ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_lane1_tbl), }, =20 .reset_list =3D sdm845_pciephy_reset_l, @@ -3540,6 +3547,8 @@ static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg= =3D { .pcs_num =3D ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl), .pcs_misc =3D sdx65_qmp_pcie_pcs_misc_tbl, .pcs_misc_num =3D ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), + .pcs_lane1 =3D sdx65_qmp_pcie_pcs_lane1_tbl, + .pcs_lane1_num =3D ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl), }, .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), @@ -3739,6 +3748,8 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pc= iephy_cfg =3D { .pcs_num =3D ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl), .pcs_misc =3D sa8775p_qmp_gen4_pcie_pcs_misc_tbl, .pcs_misc_num =3D ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), + .pcs_lane1 =3D sdx65_qmp_pcie_pcs_lane1_tbl, + .pcs_lane1_num =3D ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl), }, =20 .tbls_rc =3D &(const struct qmp_phy_cfg_tbls) { @@ -3945,6 +3956,7 @@ static void qmp_pcie_init_registers(struct qmp_pcie *= qmp, const struct qmp_phy_c void __iomem *rx2 =3D qmp->rx2; void __iomem *pcs =3D qmp->pcs; void __iomem *pcs_misc =3D qmp->pcs_misc; + void __iomem *pcs_lane1 =3D qmp->pcs_lane1; void __iomem *ln_shrd =3D qmp->ln_shrd; =20 if (!tbls) @@ -3969,6 +3981,7 @@ static void qmp_pcie_init_registers(struct qmp_pcie *= qmp, const struct qmp_phy_c =20 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); + qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num); =20 if (cfg->lanes >=3D 4 && qmp->tcsr_4ln_config) { qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, @@ -4420,6 +4433,14 @@ static int qmp_pcie_parse_dt_legacy(struct qmp_pcie = *qmp, struct device_node *np } } =20 + /* + * For all platforms where legacy bindings existed, PCS_LANE1 was + * mapped as a part of the PCS_MISC region. + */ + if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 !=3D 0) + qmp->pcs_lane1 =3D qmp->pcs_misc + + (cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc); + clk =3D devm_get_clk_from_child(dev, np, NULL); if (IS_ERR(clk)) { return dev_err_probe(dev, PTR_ERR(clk), @@ -4487,6 +4508,7 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) qmp->serdes =3D base + offs->serdes; qmp->pcs =3D base + offs->pcs; qmp->pcs_misc =3D base + offs->pcs_misc; + qmp->pcs_lane1 =3D base + offs->pcs_lane1; qmp->tx =3D base + offs->tx; qmp->rx =3D base + offs->rx; =20 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h index ac872a9eff9a8fe7fc3307759288aee15d17bd24..ab892d1067c219e8db0ba059192= 1b38a9cebebe7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h @@ -13,7 +13,8 @@ #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 -#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 -#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 + +#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x024 +#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x028 =20 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h index cdf8c04ea078a985be82d561ad0918dfdece9987..283d63c8159338b57a5026b6c2a= 86e3cce21097c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h @@ -17,7 +17,8 @@ #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 -#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24 -#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28 + +#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0x024 +#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0x028 =20 #endif --=20 2.39.5 From nobody Tue Nov 26 08:27:33 2024 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E943217BEC5 for ; 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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a15211401sm562854e87.249.2024.10.19.08.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 08:45:05 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 19 Oct 2024 18:44:54 +0300 Subject: [PATCH 5/6] phy: qualcomm: qmp-pcie: define several new registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-sar2130p-phys-v1-5-bf06fcea2421@linaro.org> References: <20241019-sar2130p-phys-v1-0-bf06fcea2421@linaro.org> In-Reply-To: <20241019-sar2130p-phys-v1-0-bf06fcea2421@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2284; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=W4/vDRwVV7Of/fJJlqT46Dx7PzvQidb+t0kRpal68/c=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnE9P11KkGH2U3FfSVJk4GXFitZtpTXBBZzkDtV X5dZJTX5mKJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxPT9QAKCRAU23LtvoBl uNRiD/0ZwTFkuQxkkN7LyCCEOioAKMZH5mREhcnSqNdH9AXwgMFg458S24lOEL8+qMDN6Jw4hv3 KGJVUkKe9RvHoV1+DH9EzeJ9a4g4dP4lOU1CB58hgyNSACs6p1zXGld2DgrBH+G5R+vyZf/G+t5 nCE/cdQ5SMHDSqaOZvs/vgjOXDyN/DbMrv4kwO0mb+sUaoiIl7Fjlj8ZQdX0Jmyv2hy/NDxj3hL WZ2ptAkziXlieQiV31phKG2xzVx/HfF/fLSs9zWSU2Kh2bDK8BLMchFYQsPQwMw1w/12ccaiJxy RWTE0y4CCmWdcEZQtT7OSvRFEKxkzszAduFKp27P4Hk9J2ZtkqVKn1zQQzI7zurMmjTzMrwGKrt YMZP7xEhElvVBH4Ljlimcn/T2wVGYenE2AJnv2DJ+XTvpQghrSQsRJHLg/QXJPiwO5mxZHHnTU7 f/HIaFev5UcegC5E7Zb55XBErHGJv4PWZXhA2QXcKZjIMIBHW1LfFzP1QFN9oomEhqmxM1wxMal aLh9GQhYd5RvoDV5jGhh/i9a4u7M8eP5gBYxsh9YJMKFpA3qLyyxJxlhcQ9EJ0RrbgKwb15lGs1 AB+PPB/a8RHn4P4zR4EUQKZdrWYil77tDytAjuuQdVuAne6lWQ/MXx2dtei8qA+Au1EFlkJCJK6 rENgrAGiegI9QXQ== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Define several registers to be used by PCIe QMP PHYs on v6 platforms. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 3 +++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h | 2 ++ drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h | 1 + 3 files changed, 6 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h b/drivers/phy/= qualcomm/phy-qcom-qmp-pcs-pcie-v6.h index 0ca79333d94261610f7274968c96362dcfb1f354..45397cb3c0c6fd2cd989ddc6005= 10589792a3b1a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h @@ -14,4 +14,7 @@ #define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 #define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 =20 +#define QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2 0x024 +#define QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2 0x028 + #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h b/drivers/phy/qualc= omm/phy-qcom-qmp-pcs-v6.h index 08299d2b78f096fa5f9388a4d54ddfa85667b18c..aa5afb921f12c07e0648f69433a= 2e6e2fb756c07 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h @@ -17,6 +17,8 @@ #define QPHY_V6_PCS_LOCK_DETECT_CONFIG3 0x0cc #define QPHY_V6_PCS_LOCK_DETECT_CONFIG6 0x0d8 #define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB 0x168 +#define QPHY_V6_PCS_G3S2_PRE_GAIN 0x170 #define QPHY_V6_PCS_RX_SIGDET_LVL 0x188 #define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 #define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h b/drivers/= phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h index 23ffcfae9efab4a9e081414f9b3bbd0079d34f18..f47fdc9cecda8c4fe46c83e6449= d68c033cd7fe2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h @@ -6,6 +6,7 @@ #ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ #define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ =20 +#define QSERDES_V6_TX_BIST_MODE_LANENO 0x00 #define QSERDES_V6_TX_CLKBUF_ENABLE 0x08 #define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c #define QSERDES_V6_TX_TX_DRV_LVL 0x14 --=20 2.39.5 From nobody Tue Nov 26 08:27:33 2024 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58259191F65 for ; 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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a15211401sm562854e87.249.2024.10.19.08.45.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 08:45:07 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 19 Oct 2024 18:44:55 +0300 Subject: [PATCH 6/6] phy: qualcomm: qmp-pcie: add support for SAR2130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-sar2130p-phys-v1-6-bf06fcea2421@linaro.org> References: <20241019-sar2130p-phys-v1-0-bf06fcea2421@linaro.org> In-Reply-To: <20241019-sar2130p-phys-v1-0-bf06fcea2421@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8219; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=C8i0BK5hjIYTgbsrEcYZTdHLVO8L8ePy9YX6HVa1xfY=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnE9P2jko6w3kde7neGna5/ktrSulyIWKbhpVaq Gw/j0M3XYmJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxPT9gAKCRAU23LtvoBl uNpxD/sH67BmvGIsCeTk2/f2+RjXjSizWLw255nagDz+VvPSXDK2NKczpGmGvAEpk3WZ1q8mkr9 n12VBvcnSplCaqpQsK6Z2gNbrGC50/+bOuyhOqCqNAy8W9sn9TOHj0TAloC0JAkWDAXbBQRjMqm KLLM35Wmn9WbyfY23FUgYslHsT5zgDqZS+5cUhxzPHvQXNnX7Eqg0mNKjTHsT69CFO62E3xjs5t WGYrPxYuih4dneR5do3i2hLILqtavUW1sANLSH2LwpMenf9JYvRA/h5AdMGiAlwPb9CtgsCA4Le 0Wph+kiFgpxpvh/xohlz7n2qagXv9WC77a4Fhz6SblHTO5zPkO5Ep7NDtsHtO5Y8K7hHzFyRz/f Zz4SB5zmorU9wQDRSpsbk1hBOL6cXT4B4v7D8BXd/PoZH+bFvSlatWvmSPFbh6FYPtu6VL6W02g hgRQ3OZmHh7Mqhj/8eUL5Mosp+tS8PE3TxkesXE3ec9CG4rrzxX9RJhgojJfwPtbSAbNiZ0GuxO souURaX92m/v3MZbVgWD4y/ssqqs173fFmuXFSDIeReHc7jYjBoXIOuTEt1W9X/8DE/eAC9Hgl6 +6POGIaXqK36vRBEi2ZsnCz5nd4zwtb5SWlY5/7E2AWN0+M7dVKssZyfMeOSMpiBmiaAAtsmMnv u4v/c011+4PsJ0Q== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Add PCIe QMP PHY configuration for the Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 141 +++++++++++++++++++++++++++= ++++ 1 file changed, 141 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 1ca1f21b1cc225f435da9c775c97dfa142117f95..c2ba411c6c90fbbc1b3e96b02e8= e63c565f254f9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2725,6 +2725,101 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_ge= n4x2_pcie_ep_pcs_alt_tbl[] =3D QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00), }; =20 +static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_serdes_tb= l[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), +}; + +static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_pcs_lane1_tb= l[] =3D { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2, 0x01), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2, 0x01), +}; + +static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_tx_tbl[] = =3D { + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_BIST_MODE_LANENO, 0x00, 2), +}; + +static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl[]= =3D { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_G3S2_PRE_GAIN, 0x2e), +}; + +static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_serdes_tb= l[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), +}; + +static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl[]= =3D { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17), +}; + +static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_= tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x14), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), +}; + struct qmp_pcie_offsets { u16 serdes; u16 pcs; @@ -3290,6 +3385,49 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = =3D { .skip_start_delay =3D true, }; =20 +static const struct qmp_phy_cfg sar2130p_qmp_gen3x2_pciephy_cfg =3D { + .lanes =3D 2, + + .offsets =3D &qmp_pcie_offsets_v5, + + .tbls =3D { + .tx =3D sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx =3D sm8550_qmp_gen3x2_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), + .pcs =3D sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_lane1 =3D sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl, + .pcs_lane1_num =3D ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl), + }, + .tbls_rc =3D &(const struct qmp_phy_cfg_tbls) { + .serdes =3D sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl), + .tx =3D sar2130p_qmp_gen3x2_pcie_rc_tx_tbl, + .tx_num =3D ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_tx_tbl), + .pcs =3D sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl), + .pcs_misc =3D sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + .tbls_ep =3D &(const struct qmp_phy_cfg_tbls) { + .serdes =3D sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl), + .pcs =3D sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl), + .pcs_misc =3D sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl), + }, + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D pciephy_v5_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, +}; + static const struct qmp_phy_cfg sc8180x_pciephy_cfg =3D { .lanes =3D 2, =20 @@ -4639,6 +4777,9 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy", .data =3D &sa8775p_qmp_gen4x4_pciephy_cfg, + }, { + .compatible =3D "qcom,sar2130p-qmp-gen3x2-pcie-phy", + .data =3D &sar2130p_qmp_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,sc8180x-qmp-pcie-phy", .data =3D &sc8180x_pciephy_cfg, --=20 2.39.5