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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a151f0c65sm576590e87.125.2024.10.19.09.26.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 09:26:46 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 19 Oct 2024 19:26:41 +0300 Subject: [PATCH 1/2] dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-sar2130p-llcc-v1-1-4e09063d04f2@linaro.org> References: <20241019-sar2130p-llcc-v1-0-4e09063d04f2@linaro.org> In-Reply-To: <20241019-sar2130p-llcc-v1-0-4e09063d04f2@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1998; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=vgPnlY0IikzOPmVwLN9lODbxv/uthexJm6oKQROqQsA=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnE93BYjEY4XqP0KZVJzk6aH9hIVcXbCahGqDAh B0zQEHakcmJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxPdwQAKCRAU23LtvoBl uPKhEACTPrRR0EmeM/yHbf9uozCAROAKN9UvPcTfYhBE2yGpIkM8MJgZeUm9+sYv9+Wxo7BQwBE sHDIBTpgVEUEzRJi9VqAQLX5lWpNBIMGyRWann6Bjm4LvkisdG+V19zUEgVTDJyVaovDsvV6Hvf sVbpCxEtnbBQYZpiqSUuk777+njiOsGsraHmDisWUJ8c077YrULQIVLf0CntLk1D56+5BDmG1In lEOL8nm9q938e/tJRoVPs1OAfGMufwvDpInppcnkJJg2zCTddHiWdSXNsRXFMHmmSpc/6HigXf2 tUuphQk0oK7T8azDgfjr6tHBo7yw4rtuGlQjohOqkSLPoCiRiQ0U/+9grPH8Ys8rRGxuzyqDIjc IN2MUTDe+Sy2cSotIa+y3JuRFE9AV34CuSaywvy/z/OCiZgkEIe6se5IUUMFFwXiQKD/kJoeR04 z5VJTqsQQIj/S5AcOq1hAjurFzryhlPiCDyPsU3l+P6LONPOx+1VlgTywoLnndXjFuIb2g9ktAx MVAiTiP0D4tFQblyIO/D0pm7bsv2SQapy/eaDTzs0ISgWXXJWCF9Cn+ZYfa/2rs8ja1gyOqBttu E0mzg1CGBrLqRbIFB9jjBIZqdO7QNJ4/nN62wpiBRm+UMkFp4RUhNZJHnhYalNHC3mQfd9Rn5aA Cizq/ln6LFDjlog== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Describe the last level cache controller on the SAR2130P and SAR1130P platforms. They have 2 banks and also a separate register set to control scratchpad slice. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/cache/qcom,llcc.yaml | 28 ++++++++++++++++++= ++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Docum= entation/devicetree/bindings/cache/qcom,llcc.yaml index 68ea5f70b75f031cd8b23cf48d566c3a760dab77..2edacf28944c78b53b51744d787= f5d529ad83f3c 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -22,6 +22,8 @@ properties: enum: - qcom,qdu1000-llcc - qcom,sa8775p-llcc + - qcom,sar1130p-llcc + - qcom,sar2130p-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sc8180x-llcc @@ -62,6 +64,32 @@ required: - reg-names =20 allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sar1130p-llcc + - qcom,sar2130p-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast OR register region + - description: LLCC broadcast AND register region + - description: LLCC scratchpad broadcast OR register region + - description: LLCC scratchpad broadcast AND register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + - const: llcc_broadcast_and_base + - const: llcc_scratchpad_broadcast_base + - const: llcc_scratchpad_broadcast_and_base + - if: properties: compatible: --=20 2.39.5 From nobody Tue Nov 26 08:37:41 2024 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 384C818DF65 for ; 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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a151f0c65sm576590e87.125.2024.10.19.09.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 09:26:47 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 19 Oct 2024 19:26:42 +0300 Subject: [PATCH 2/2] soc: qcom: llcc: add support for SAR2130P and SAR1130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241019-sar2130p-llcc-v1-2-4e09063d04f2@linaro.org> References: <20241019-sar2130p-llcc-v1-0-4e09063d04f2@linaro.org> In-Reply-To: <20241019-sar2130p-llcc-v1-0-4e09063d04f2@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=14449; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=9IJyzCE4GaHn616VyWC1aCINwEhMZfazYzFsYxs/DqI=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnE93ChdRgcGcy1StCcOqdbrzX1XQ7bAfWV7lXt QWzfprHOVeJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxPdwgAKCRAU23LtvoBl uIjcD/91iaxwyPN09zf37Dw1Z9JD6lfhxpce9Mn1iqpdaIOQTlztbZQe5YuRxmrNEWRBBRdunJ5 lDB02e7xai2w3X2nqRBQKzcvzABkR344huF9EVNt2YvWXiepWaW9B/SQzxz3oggOx4EdUvBN3jE iiXi9lhOmNTLth2AUBcO/aBFkGIJ+ZJ3UWK8cJNnLPTKKOJzRv7GsxY+UqSSYaTynCNpKEFpMV1 GZG6TaQbxgVcMmAv3h2+TM5Jf/bEscKEH6CZ+eaRY+b32lbTJt7vzn7lJkrwRNaVzt9XTN4xcvC /C1K4R4GShUZ2IfNDJ91qnSY2GFZ87H818WjX8pZQWcsGNfhuiR+7IfadWXQrtsSTwk/0W3BlO8 yHKnsYZg/YihEiZ7yXl15ASg2XFiEiSa+EPQGG7lHgbNSBHYMhtAoJ0a9lZYBeIhOls7xDidJeh SHpRjKv6YFAr5dkcxU1XrmCTQmW3vSs/1u0oFRsHy8dkLJkItb6sl5KWKWKh/MMXjMS6NJZ2aRT fNVe6U9tKsytfSZY6Wi0MKy0NUd8amBwg3ojWpu5yKOHaZXzfaKOMhFDCm1ibxeurlFudl0/Kr+ DWDUfetQ8ukHayBU+qNg0fKQGqCZk7zIHhkRwSNxUAGpCd5bXo46c2/vBnplI0tvagC26UZVFdi +5b2GXSK04f5xMA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Implement necessary support for the LLCC control on the SAR1130P and SAR2130P platforms. These two platforms use different ATTR1_MAX_CAP shift and also require manual override for num_banks. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/llcc-qcom.c | 468 +++++++++++++++++++++++++++++++++= +++- include/linux/soc/qcom/llcc-qcom.h | 12 + 2 files changed, 474 insertions(+), 6 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index a470285f54a875bf2262aac7b0f84ed8fd028ef1..ef84fe3b2af4e777126a8308bfd= 4ec47b28aeae2 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -32,6 +32,7 @@ #define ATTR1_FIXED_SIZE_SHIFT 0x03 #define ATTR1_PRIORITY_SHIFT 0x04 #define ATTR1_MAX_CAP_SHIFT 0x10 +#define ATTR1_MAX_CAP_SHIFT_sar 0x0e #define ATTR0_RES_WAYS_MASK GENMASK(15, 0) #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16) #define ATTR0_BONUS_WAYS_SHIFT 0x10 @@ -140,6 +141,11 @@ struct qcom_llcc_config { bool need_llcc_cfg; bool no_edac; bool irq_configured; + /* + * special workarounds for SAR2130P and similar platforms which have + * slightly different register mapping. + */ + bool is_sar_chip; }; =20 struct qcom_sct_config { @@ -298,6 +304,408 @@ static const struct llcc_slice_config sa8775p_data[] = =3D { }, }; =20 +static const struct llcc_slice_config sar1130p_data[] =3D { + { + .usecase_id =3D LLCC_CPUSS, + .slice_id =3D 1, + .max_cap =3D 4096, + .priority =3D 1, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_VIDSC0, + .slice_id =3D 2, + .max_cap =3D 512, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_AUDIO, + .slice_id =3D 6, + .max_cap =3D 1024, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_CMPT, + .slice_id =3D 10, + .max_cap =3D 1024, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPUHTW, + .slice_id =3D 11, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPU, + .slice_id =3D 12, + .max_cap =3D 3072, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .write_scid_en =3D true, + }, { + .usecase_id =3D LLCC_MMUHWT, + .slice_id =3D 13, + .max_cap =3D 512, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + }, { + .usecase_id =3D LLCC_DISP, + .slice_id =3D 16, + .max_cap =3D 12800, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_CVP, + .slice_id =3D 28, + .max_cap =3D 256, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_APTCM, + .slice_id =3D 26, + .max_cap =3D 2048, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x3, + .cache_mode =3D true, + .dis_cap_alloc =3D true, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_WRCACHE, + .slice_id =3D 31, + .max_cap =3D 256, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_AENPU, + .slice_id =3D 30, + .max_cap =3D 3072, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_LEFT, + .slice_id =3D 17, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_RIGHT, + .slice_id =3D 18, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_LEFT, + .slice_id =3D 22, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_RIGHT, + .slice_id =3D 23, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, +}; + +static const struct llcc_slice_config sar2130p_data[] =3D { + { + .usecase_id =3D LLCC_CPUSS, + .slice_id =3D 1, + .max_cap =3D 6144, + .priority =3D 1, + .fixed_size =3D 0, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_VIDSC0, + .slice_id =3D 2, + .max_cap =3D 128, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_AUDIO, + .slice_id =3D 6, + .max_cap =3D 1024, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_CMPT, + .slice_id =3D 10, + .max_cap =3D 1024, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPUHTW, + .slice_id =3D 11, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPU, + .slice_id =3D 12, + .max_cap =3D 1536, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .write_scid_en =3D true, + }, { + .usecase_id =3D LLCC_MMUHWT, + .slice_id =3D 13, + .max_cap =3D 1024, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_DISP, + .slice_id =3D 16, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_APTCM, + .slice_id =3D 26, + .max_cap =3D 2048, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x3, + .cache_mode =3D true, + .dis_cap_alloc =3D true, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_WRCACHE, + .slice_id =3D 31, + .max_cap =3D 256, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_VIEYE, + .slice_id =3D 7, + .max_cap =3D 7168, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_VIDPTH, + .slice_id =3D 8, + .max_cap =3D 7168, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPUMV, + .slice_id =3D 9, + .max_cap =3D 2048, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVA_LEFT, + .slice_id =3D 20, + .max_cap =3D 7168, + .priority =3D 5, + .fixed_size =3D true, + .bonus_ways =3D 0x3ffffffc, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVA_RIGHT, + .slice_id =3D 21, + .max_cap =3D 7168, + .priority =3D 5, + .fixed_size =3D true, + .bonus_ways =3D 0x3ffffffc, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVAGAIN, + .slice_id =3D 25, + .max_cap =3D 1024, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_AENPU, + .slice_id =3D 30, + .max_cap =3D 3072, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_VIPTH, + .slice_id =3D 29, + .max_cap =3D 1024, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_LEFT, + .slice_id =3D 17, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_RIGHT, + .slice_id =3D 18, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_LEFT, + .slice_id =3D 22, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_RIGHT, + .slice_id =3D 23, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_SPAD, + .slice_id =3D 24, + .max_cap =3D 7168, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, +}; + static const struct llcc_slice_config sc7180_data[] =3D { { .usecase_id =3D LLCC_CPUSS, @@ -2687,6 +3095,28 @@ static const struct qcom_llcc_config sa8775p_cfg[] = =3D { }, }; =20 +static const struct qcom_llcc_config sar1130p_cfg[] =3D { + { + .sct_data =3D sar1130p_data, + .size =3D ARRAY_SIZE(sar1130p_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + .is_sar_chip =3D true, + }, +}; + +static const struct qcom_llcc_config sar2130p_cfg[] =3D { + { + .sct_data =3D sar2130p_data, + .size =3D ARRAY_SIZE(sar2130p_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + .is_sar_chip =3D true, + }, +}; + static const struct qcom_llcc_config sc7180_cfg[] =3D { { .sct_data =3D sc7180_data, @@ -2839,6 +3269,16 @@ static const struct qcom_sct_config sa8775p_cfgs =3D= { .num_config =3D ARRAY_SIZE(sa8775p_cfg), }; =20 +static const struct qcom_sct_config sar1130p_cfgs =3D { + .llcc_config =3D sar1130p_cfg, + .num_config =3D ARRAY_SIZE(sar1130p_cfg), +}; + +static const struct qcom_sct_config sar2130p_cfgs =3D { + .llcc_config =3D sar2130p_cfg, + .num_config =3D ARRAY_SIZE(sar2130p_cfg), +}; + static const struct qcom_sct_config sc7180_cfgs =3D { .llcc_config =3D sc7180_cfg, .num_config =3D ARRAY_SIZE(sc7180_cfg), @@ -3146,7 +3586,10 @@ static int _qcom_llcc_cfg_program(const struct llcc_= slice_config *config, */ max_cap_cacheline =3D max_cap_cacheline / drv_data->num_banks; max_cap_cacheline >>=3D CACHE_LINE_SIZE_SHIFT; - attr1_val |=3D max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; + if (cfg->is_sar_chip) + attr1_val |=3D max_cap_cacheline << ATTR1_MAX_CAP_SHIFT_sar; + else + attr1_val |=3D max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; =20 attr1_cfg =3D LLCC_TRP_ATTR1_CFGn(config->slice_id); =20 @@ -3383,12 +3826,23 @@ static int qcom_llcc_probe(struct platform_device *= pdev) goto err; cfg =3D &cfgs->llcc_config[cfg_index]; =20 - ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_ba= nks); - if (ret) - goto err; + /* + * For some reason register returns incorrect value here. + * List compatibles instead of using .is_sar_chip since there might be + * SAR-like chips which have other number of banks. + */ + if (of_device_is_compatible(dev->of_node, "qcom,sar1130p-llcc") || + of_device_is_compatible(dev->of_node, "qcom,sar2130p-llcc")) { + num_banks =3D 2; + } else { + ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_b= anks); + if (ret) + goto err; + + num_banks &=3D LLCC_LB_CNT_MASK; + num_banks >>=3D LLCC_LB_CNT_SHIFT; + } =20 - num_banks &=3D LLCC_LB_CNT_MASK; - num_banks >>=3D LLCC_LB_CNT_SHIFT; drv_data->num_banks =3D num_banks; =20 drv_data->regmaps =3D devm_kcalloc(dev, num_banks, sizeof(*drv_data->regm= aps), GFP_KERNEL); @@ -3486,6 +3940,8 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) static const struct of_device_id qcom_llcc_of_match[] =3D { { .compatible =3D "qcom,qdu1000-llcc", .data =3D &qdu1000_cfgs}, { .compatible =3D "qcom,sa8775p-llcc", .data =3D &sa8775p_cfgs }, + { .compatible =3D "qcom,sar1130p-llcc", .data =3D &sar1130p_cfgs }, + { .compatible =3D "qcom,sar2130p-llcc", .data =3D &sar2130p_cfgs }, { .compatible =3D "qcom,sc7180-llcc", .data =3D &sc7180_cfgs }, { .compatible =3D "qcom,sc7280-llcc", .data =3D &sc7280_cfgs }, { .compatible =3D "qcom,sc8180x-llcc", .data =3D &sc8180x_cfgs }, diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index 2f20281d4ad4352ef59e7b19148cd324c7991012..8e5d78fb4847a232ab17a66c277= 5552dcb287752 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -54,7 +54,19 @@ #define LLCC_CAMEXP4 52 #define LLCC_DISP_WB 53 #define LLCC_DISP_1 54 +#define LLCC_VIEYE 57 +#define LLCC_VIDPTH 58 +#define LLCC_GPUMV 59 +#define LLCC_EVA_LEFT 60 +#define LLCC_EVA_RIGHT 61 +#define LLCC_EVAGAIN 62 +#define LLCC_VIPTH 63 #define LLCC_VIDVSP 64 +#define LLCC_DISP_LEFT 65 +#define LLCC_DISP_RIGHT 66 +#define LLCC_EVCS_LEFT 67 +#define LLCC_EVCS_RIGHT 68 +#define LLCC_SPAD 69 =20 /** * struct llcc_slice_desc - Cache slice descriptor --=20 2.39.5