From nobody Tue Nov 26 11:26:30 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88C0C17DE2D; Sat, 19 Oct 2024 15:38:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729352329; cv=none; b=oTSUIFPYsBgVg67cmMzMuiEgEh8gYW5hdCjbQ3lUzh7Y7hIyGsjTa3wFqczv30M+4869c8RzJTf33q9RdheQ5+ZuB+m+CQ5Nekalww+Hf0FHJ2LpPzh11KXkclzaBYwjB6F5LJ0T7zXEjhXmdHI5Ls+mp9VZ7+Df9Sw6s1/SOe8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729352329; c=relaxed/simple; bh=mVQmN0s+yxLNnXQjp2K8qu5YCOAaJkDNG2R7E0GN6xg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=pOtxbzR2ZXqKh9OA6NuixU+WQzIIfIvMAe0SgdpX4/hfI7aS5Nw2fdd/jaM61mZBHfogEgyzpyH/2YaVCUsVSjArmRGqMT0uID0QrulsM335RImscZ6G94T0EPoYAEw2UcajMwzyHvESMiHxfubrj06qO7nFrsg7JelbNBAwrds= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=PruUAdaN; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="PruUAdaN" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49J6UlBg005504; Sat, 19 Oct 2024 15:38:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= INktPbV7W46TlKLbtoIPptr+tVe/VWFjdGeKJyhJUdg=; b=PruUAdaNqfK7pqq6 RNgcgDfkBbgddoRAE8R88Oe8fLuzrWVRFtnaQedpgbl2ivH5yQ/FjPYEnMAiWFUI Bu8guglpXuwQCvaE07ZPWiWhVH8oZSZE3WQz9pF9mtPd/q3t4blzqGEVebW/5Aad X5p/EpqymOPsuvbVPQleWUBUkpSF8p1whGSQJ9Jw4cCujjPatL2Xvqh9+/rkeaGB Agv7I3n+drw97dkJjHfs8NE5LFvk36n22TeBTk6muQD3DnMugCulBqBCL1NkGVpN qQwm2/jfN9Qb14TClPuX9vOWD947pvaU9hpv9JmtPXz0+mOPZACt49MAV22kfp72 A5LCkA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42c6rj0su0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 19 Oct 2024 15:38:36 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49JFcZNb025640 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 19 Oct 2024 15:38:35 GMT Received: from hu-mahap-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 19 Oct 2024 08:38:28 -0700 From: Mahadevan Date: Sat, 19 Oct 2024 20:46:39 +0530 Subject: [PATCH v4 5/5] arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241019-patchv3_1-v4-5-a95d8f0eae37@quicinc.com> References: <20241019-patchv3_1-v4-0-a95d8f0eae37@quicinc.com> In-Reply-To: <20241019-patchv3_1-v4-0-a95d8f0eae37@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mahadevan , Neil Armstrong , Bjorn Andersson , "Konrad Dybcio" CC: , , , , , Kalyan Thota , Jayaprakash Madisetty X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729352274; l=3798; i=quic_mahap@quicinc.com; s=20241001; h=from:subject:message-id; bh=mVQmN0s+yxLNnXQjp2K8qu5YCOAaJkDNG2R7E0GN6xg=; b=eN1i3kLgWaSsy0AaiWSu1NQhbRsWAuA5DE1xuN/kWpnIuEz+NsX5OCMXD1ZIls0dUUhhPb0VH gJGqIOYbF64AI97WNpYzJq9aXd2Rpr1j+vcWDDSUhZ35BxORKf/Fdfj X-Developer-Key: i=quic_mahap@quicinc.com; a=ed25519; pk=Xc9CA438o9mZKp4uZ8vZMclALnJ8XtlKn/n3Y42mMBI= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 6K4kK0WjQU-_Pnkli8Z2ATEifnEHhOSD X-Proofpoint-ORIG-GUID: 6K4kK0WjQU-_Pnkli8Z2ATEifnEHhOSD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 bulkscore=0 malwarescore=0 mlxscore=0 spamscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410190113 Add devicetree changes to enable MDSS0 display-subsystem its display-controller(DPU) for Qualcomm SA8775P platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Mahadevan --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 8fd68a8aa916e6595134b470f87b18b509178a51..5f6b7b59ec707490b162649d0fd= 97f85b1489e45 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -2937,6 +2938,94 @@ camcc: clock-controller@ade0000 { #power-domain-cells =3D <1>; }; =20 + mdss0: display-subsystem@ae00000 { + compatible =3D "qcom,sa8775p-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + /* same path used twice */ + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x1000 0x402>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss0_mdp: display-controller@ae01000 { + compatible =3D "qcom,sa8775p-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdss0_mdp_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <0>; + + mdss0_mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + }; + dispcc0: clock-controller@af00000 { compatible =3D "qcom,sa8775p-dispcc0"; reg =3D <0x0 0x0af00000 0x0 0x20000>; --=20 2.34.1